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GS72116ATP/J/T/U SOJ, TSOP, FP-BGA, TQFP Commercial Temp Industrial Temp Features
* Fast access time: 7, 8, 10, 12 ns * CMOS low power operation: 145/125/100/85 mA at minimum cycle time * Single 3.3 V power supply * All inputs and outputs are TTL-compatible * Byte control * Fully static operation * Industrial Temperature Option: -40 to 85C * Package line up J: 400 mil, 44-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package T: 10 mm x 10 mm, 44-pin TQFP U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
128K x 16 2Mb Asynchronous SRAM
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
7, 8, 10, 12 ns 3.3 V VDD Center VDD and VSS
SOJ 128K x 16-Pin Configuration
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC
Top view
44-pin SOJ
Description
The GS72116A is a high speed CMOS Static RAM organized as 131,072 words by 16 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS72116A is available in a 6 mm x 8 mm Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
Package J
Pin Descriptions Symbol
A0-A16 DQ1-DQ16 CE LB UB WE OE VDD VSS NC
Description
Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3 V power supply Ground No connect
Rev: 1.04a 10/2002
1/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin TQFP 128K x 16-Pin Configuration
A16 A15 A14 A13 A12 A11 A10 A9 OE UB LB
CE DQ1 DQ2 DQ3 DQ4
VDD VSS
1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23
DQ16
DQ15 DQ14 DQ13
VSS VDD
DQ12 DQ11 DQ10 DQ9 NC
DQ5 DQ6 DQ7 DQ8
10 11 12 13 14 15 16 17 18 19 20 21 22
WE A0 A1 A2 A3 A4 NC A5 A6 A7 A8
Package T
Fine Pitch BGA 128K x 16-Bump Configuration
1 2 3 4 5 6
A B C D E F G H
LB DQ16
OE UB
A0 A3 A5 NC NC A8 A10 A13
A1 A4 A6 A7 A16 A9 A11 A14
A2 CE DQ2 DQ4 DQ5 DQ7 WE A15
NC DQ1 DQ3
VDD VSS
DQ14 DQ15
VSS VDD
DQ13 DQ12
DQ11 DQ10 DQ9 NC NC A12
DQ6 DQ8 NC
6 mm x 8 mm, 0.75 mm Bump Pitch Top View Package U
Rev: 1.04a 10/2002
2/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
TSOP-II 128K x 16-Pin Configuration
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC
Top view
44-pin TSOP II
Package TP
Block Diagram
A0 Address Input Buffer
Row Decoder
Memory Array
A16 CE WE Control OE UB _____ LB _____
Column Decoder
I/O Buffer
DQ1
DQ16
Rev: 1.04a 10/2002
3/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Truth Table CE
H
OE
X
WE
X
LB
X L
UB
X L H L L H L X H
DQ1 to DQ8
Not Selected Read Read High Z Write Write Not Write, High Z High Z High Z
DQ9 to DQ16
Not Selected Read High Z Read Write Not Write, High Z Write High Z High Z
VDD Current
ISB1, ISB2
L
L
H
L H L
L
X
L
L H
IDD
L L
H X
H X
X H
Note: X: "H" or "L"
Absolute Maximum Ratings
Parameter
Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature
Symbol
VDD VIN VOUT PD TSTG
Rating
-0.5 to +4.6 -0.5 to VDD +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) 0.7 -55 to 150
Unit
V V V W
o
C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.04a 10/2002
4/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/12 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range
Symbol
VDD VIH VIL TAc TAI
Min
3.0 2.0 -0.3 0 -40
Typ
3.3 -- -- -- --
Max
3.6 VDD +0.3 0.8 70 85
Unit
V V V
o
C
oC
Note: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than -2 V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance Output Capacitance
Symbol
CIN COUT
Test Condition
VIN = 0 V VOUT = 0 V
Max
5 7
Unit
pF pF
Notes: 1. Tested at TA = 25C, f = 1 MHz 2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
IIL ILO VOH VOL
Test Conditions
VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = -4mA ILO = +4mA
Min
- 1 uA -1 uA 2.4 --
Max
1 uA 1 uA -- 0.4 V
Rev: 1.04a 10/2002
5/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Power Supply Currents
Parameter Symbol Test Conditions
CE VIL All other inputs VIH or VIL Min. cycle time IOUT = 0 mA CE VIH All other inputs VIH or VIL Min. cycle time CE VDD - 0.2 V All other inputs VDD - 0.2 V or 0.2 V
0 to 70C 7 ns 8 ns 10 ns 12 ns 7 ns
-40 to 85C 8 ns 10 ns 12 ns
Operating Supply Current
IDD (max)
145 mA
125 mA
100 mA
85 mA
150 mA
130 mA
105 mA
90 mA
Standby Current
ISB1 (max)
25 mA
20 mA
20 mA
15 mA
30 mA
25 mA
25 mA
20 mA
Standby Current
ISB2 (max)
5 mA
10 mA
AC Test Conditions
Parameter
Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load
Conditions
VIH = 2.4 V VIL = 0.4 V tr = 1 V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2
Output Load 1
DQ 50 VT = 1.4 V 30pF1
Output Load 2
3.3 V DQ 5pF1 589 434
Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Rev: 1.04a 10/2002
6/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U AC Characteristics
Read Cycle
Parameter Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in High Z (CE) Output disable to output in High Z (OE) Byte disable to output in High Z (UB, LB) Symbol tRC tAA tAC tAB tOE tOH tLZ* tOLZ* tBLZ* tHZ* tOHZ* tBHZ* -7 Min 7 -- -- -- -- 3 3 0 0 -- -- -- Max -- 7 7 3 3 -- -- -- -- 3.5 3 3 Min 8 -- -- -- -- 3 3 0 0 -- -- -- -8 Max -- 8 8 3.5 3.5 -- -- -- -- 4 3.5 3.5 Min 10 -- -- -- -- 3 3 0 0 -- -- -- -10 Max -- 10 10 4 4 -- -- -- -- 5 4 4 Min 12 -- -- -- -- 3 3 0 0 -- -- -- -12 Max -- 12 12 5 5 -- -- -- -- 6 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
tRC Address tAA tOH Data Out Previous Data Data valid
Rev: 1.04a 10/2002
7/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Read Cycle 2: WE = VIH
tRC Address tAA CE tAC tLZ UB, LB OE tBLZ tOE Data Out tOLZ High impedance tAB tBHZ tOHZ Data valid tHZ
Write Cycle
Parameter Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z Symbol tWC tAW tCW tBW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ* -7 Min 7 5 5 5 3.5 0 5 0 0 0 3 -- Max -- -- -- -- -- -- -- -- -- -- -- 3 Min 8 5.5 5.5 5.5 4 0 5.5 0 0 0 3 -- -8 Max -- -- -- -- -- -- -- -- -- -- -- 3.5 Min 10 7 7 7 5 0 7 0 0 0 3 -- -10 Max -- -- -- -- -- -- -- -- -- -- -- 4 Min 12 8 8 8 6 0 8 0 0 0 3 -- -12 Max -- -- -- -- -- -- -- -- -- -- -- 5
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
* These parameters are sampled and are not 100% tested.
Rev: 1.04a 10/2002
8/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Write Cycle 1: WE control
tWC Address tAW OE tCW CE tBW UB, LB tAS WE tDW Data In tWHZ Data Out tDH Data valid tWLZ High impedance tWP tWR
Write Cycle 2: CE control
tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1
High impedance
Rev: 1.04a 10/2002
9/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Write Cycle 3: UB, LB control
tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1
High impedance
Rev: 1.04a 10/2002
10/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin, 400 mil SOJ
Symbol A A1 A2 HE B B1 c 1 e 22
A
Dimension in inch min -- 0.025 -- -- nom -- -- 0.018 0.008 max 0.148 -- -- --
Dimension in mm min -- 0.635 2.667 -- 0.660 -- 28.44 -- 9.144 2.083 -- 0o nom -- -- 2.794 0.457 0.711 0.203 28.58 1.27 9.398 2.210 -- -- max 3.759 -- 2.921 -- 0.813 -- 28.70 -- 9.652 2.70 0.102 7o
D 44 23
L c
0.105 0.110 0.115 0.026 0.028 0.032 1.120 1.125 1.130 -- 0.05 --
GE
E
D E e HE
0.395 0.400 0.405 10.033 10.160 10.287 0.435 0.440 0.445 11.049 11.176 11.303 0.360 0.370 0.380 0.082 0.087 0.106 -- 0o -- -- 0.004 7o
A
A2
A1
y
B B1 Detail A
GE Q L y Q
Note: 1. Dimension D& E do not include interlead flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: inches
Rev: 1.04a 10/2002
11/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin, 400 mil TSOP-II
Dimension in inch 44 D 23 c Symbol A A1 A2 HE
A
Dimension in mm min -- 0.05 0.95 0.25 -- 18.31 10.06 -- 11.56 0.40 -- -- 0
o
min -- 0.002 0.037 0.01 -- 0.721 0.396 -- 0.455 0.016 -- -- 0
o
nom -- -- 0.039 0.014 0.006 0.725 0.400 0.031 0.463 0.020 0.031 -- --
max 0.047 -- 0.041 0.018 -- 0.729 0.404 -- 0.471 0.024 -- 0.004 5
o
nom -- -- 1.00 0.35 0.15 18.41 10.16 0.80 11.76 0.50 0.80 -- --
max 1.20 -- 1.05 0.45 -- 18.51 10.26 -- 11.96 0.60 -- 0.10 5o
E
B c D E e HE L
1 A2
e
22 B
A
A1
y L1 L
L1 y Q Q
Detail A
Note: 1. Dimension D& E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Controlling dimension: mm
Rev: 1.04a 10/2002
12/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin TQFP (LQFP) Package
D1
A2 A1
E1
L1 C e b
Body Size E1 10 D1 10
Lead Count 44
Standoff A1 0.1
Body Thickness A2 1.4
Lead Length L1 1.0
Lead Width b 0.3
Lead Thickness c 0.127
Lead Pitch e 0.8
Units: mm
Rev: 1.04a 10/2002
13/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U 44 Pin TQFP (LQFP) Package
D1 A2 A1
E1
L1 C e Body Size Standoff Lead Count E1 D1 A1
10 10 44 0.1 Units: mm
b Lead Thickness c
0.127
Body Thickness A2
1.4
Lead Length Lead Width L1 b
1.0 0.3
Lead Pitch e
0.8
Rev: 1.04a 10/2002
14/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U 6 mm x 10 mm Fine Pitch BGA
8.00 0.10 6.00 0.10 0.22 0.05 3 2 1 6 0.75(typ).
15/18 (c) 2001, Giga Semiconductor, Inc.
Top View
1.20(max)
pin A1 index
Bottom View
pin A1 index
5
4
Rev: 1.04a 10/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Ball Dia. 0.35 Pitch 0.75
3.75 5.25
0.36(typ)
0.10
G
D
C
H
A
B
E
F
D
units: mm
GS72116ATP/J/T/U
Ordering Information Part Number*
GS72116ATP-7 GS72116ATP-8 GS72116ATP-10 GS72116ATP-12 GS72116ATP-7I GS72116ATP-8I GS72116ATP-10I GS72116ATP-12I GS72116AJ-7 GS72116AJ-8 GS72116AJ-10 GS72116AJ-12 GS72116AJ-7I GS72116AJ-8I GS72116AJ-10I GS72116AJ-12I GS72116AT-7 GS72116AT-8 GS72116AT-10 GS72116AT-12 GS72116AT-7I GS72116AT-8I GS72116AT-10I GS72116AT-12I
Package
400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP
Access Time
7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns
Temp. Range
Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Status
Rev: 1.04a 10/2002
16/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Ordering Information Part Number*
GS72116AU-7 GS72116AU-8 GS72116AU-10 GS72116AU-12 GS72116AU-7I GS72116AU-8I GS72116AU-10I GS72116AU-12I
*
Package
6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA
Access Time
7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns
Temp. Range
Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Status
Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. For example: GS72116ATP-8T
Rev: 1.04a 10/2002
17/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U 2Mb Asynchronous Datasheet Revision History
Rev. Code: Old; New
72116A_r1 72116A_r1; 72116A_r1_01 72116A_r1_01; 72116A_r1_02 72116A_r1_02; 72116A_r1_03 72116A_r1_03; 72116A_r1_04 Content Content Content Content
Types of Changes Format or Content
Page #/Revisions/Reason
* Creation of new datasheet * Added 6 ns speed bin to entire document * Updated all power numbers * Changed 6 mm x 10 mm FP_BGA package designator from U to X * Updated Recommended Operating Conditions table on page 5 * Removed 15 ns bin * Changed FPBGA package from 6 x 10 to 6 x 8 (package U) * Removed 6 ns speed bin from entire document * Added 7 ns speed bin to entire document
Rev: 1.04a 10/2002
18/18
(c) 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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