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| UL (R) LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 YLCNTR/YLOL FCK 1 2 V DD (+5V) 3 D0 D1 D2 D3 D4 D5 D6 D7 4 5 6 7 8 9 10 11 LS7266R1 (631) 271-0400 FAX (631) 271-0405 December 2002 PIN ASSIGNMENT - TOP VIEW 28-Pin Package 28 27 26 25 24 23 22 21 20 19 18 17 16 15 YRCNTR/YABG YFLG1 YFLG2 YA YB XFLG2 XFLG1 XB XA XLCNTR/XLOL XRCNTR/XABG X/Y RD CS A3800 24-BIT DUAL-AXIS QUADRATURE COUNTER FEATURES: * 30 MHz count frequency in non-quadrature mode, 17MHz in x4 quadrature mode. * Dual 24-bit counters to support X and Y axes in motion control applications. * Dual 24-bit comparators. * Digital filtering of the input quadrature clocks * Programmable 8-bit separate filter clock prescalers for each axis. * Error flags for noise exceeding filter band width. * Programmable Index Input and other programmable I/Os. * Independent mode programmability for each axis. * Programmable count modes: Quadrature (x1, x2, x4) / Non-quadrature, Normal / Modulo-N / Range Limit / Non-Recycle, Binary / BCD. * 8-bit 3-State data I/O bus. * 5V operation (VDD-VSS). * TTL/CMOS compatible I/Os. * LS7266R1 (DIP); LS7266R1-SD (Skinny DIP); LS7266R1-S (SOIC); LS7266R1-TS (TSSOP) LS726 6R1 V SS (GND) 12 C/D 13 WR 14 LS7266R1 Registers: LS7266R1 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X, whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode of the three most significant bits (D7-D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects between control and data information for Read/Write. Following is a complete list of LS7266R1 registers. Preset Registers: XPR and YPR Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data write cycles. PR 7 HI BYTE (PR2) 07 MID BYTE (PR1) 07 0 LO BYTE (PR0) Counters: XCNTR and YCNTR Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its associated A/B inputs. Each CNTR can be loaded with the content of its associated PR. Output Latches: XOL and YOL Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read cycles. OL 7 HI BYTE (OL2) 07 MID BYTE (OL1) 07 0 LO BYTE (OL0) Byte Pointers: XBP and YBP The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is automatically incremented to address the next byte. 7266R1-121002-1 Flag Register: XFLAG and YFLAG The FLAG registers hold the status information of the CNTRs and can be read out on the data bus. The E bit of a FLAG register is set to 1 when the noise pulses at the quadrature inputs are wide enough to be validated by the input filter circuits. E = 1 indicates excessive noise at the inputs but not a definite count error. Once set, E can only be reset via the RLD. FLAG 7 6 5 4 3 2 1 0 BT: Borrow Toggle flip-flop. Toggles every time CNTR underflows. CT: Carry toggle flip-flop. Toggles every time CNTR overflows. CPT: Compare toggle flip-flop. Toggles every time PR equals CNTR. S: Sign flag. Set to1 when CNTR underflows. Reset to 0 when CNTR overflows. E: Error flag. Set to 1 when excessive noise is present at the count inputs in quadrature mode. Irrelevant in non-quadrature mode. U/D: Up/Down flag. Set to 1 when counting up and reset to 0 when counting down. IDX: Index. Set to 1 when selected index input is at active level. 0: Not used. Always reset to 0. Filter Clock Prescalers: XPSC and YPSC Each PSC is an 8-bit programmable modulo-N down counter, driven by the FCK clock. The factor N is down loaded into a PSC from the associated PR low byte register PR0. The PSCs provide the ability to generate independent filter clock frequencies for each channel. The PSCs generate the internal filter clock, FCKn used to validate inputs XA, XB, YA, YB in the quadrature mode. Final filter clock frequency fFCKn = ( fFCK/(n+1) ) , where n = PSC = 0 to FFH. For proper counting in the quadrature mode, fFCKn 8fQA (or 8fQB), where fQA and fQB are the clock frequencies at inputs A and B. In non-quadrature mode filter clock is not needed and the FCK input (Pin 2), should be tied to VDD. Reset and Load Signal Decoders: XRLD and YRLD Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer CNTR to OL, reset CNTR, reset FLAG and reset BP. RLD 7 6 5 4 3 2 1 0 0: NOP 1: Reset BP 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 0 1 7266R1-111196-2 : NOP : Reset CNTR : Reset BT, CT, CPT,S : Reset E : NOP : Transfer PR to CNTR (Note: All 24-bits are transferred in parallel) : Transfer CNTR to OL (Note: All 24-bits are transferred in parallel) : Transfer PR0 to PSC : Select RLD : Select the RLD addressed by X/Y input : Select both XRLD and YRLD together (Note: D7 = 1 overrides X/Y input) Counter Mode Registers: XCMR and YCMR The CNTR operational mode is programmed by writing into the CMRs. CMR 7 6 5 4 3 2 1 0 0: 1: 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 1 : Select CMR 0 0: Select CMR addressed by X/Y input 1: Select both XCMR and YCMR together (Note: D7=1 overrides X/Y input) : Non-quadrature : Quadrature X1 Binary count BCD count : Normal count : Range Limit : Non-recycle count : Modulo-N : Quadrature X2 : Quadrature X4 DEFINITIONS OF COUNT MODES: Range Limit. In range limit count mode, an upper and a lower limit is set, mimicking limit switches in the mechanical counterpart. The upper limit is set by the content of the PR and the lower limit is set to be 0. The CNTR freezes at CNTR = PR when counting up and at CNTR=0 when counting down. At either of these limits, the counting is resumed only when the count direction is reversed. Non-Recycle. In non-recycle count mode, the CNTR is disabled, whenever a count overflow or underflow takes place. The end of cycle is marked by the generation of a Carry (in Up Count) or a Borrow (in Down Count). The CNTR is re-enabled when a reset or load operation is performed on the CNTR. Modulo-N. In modulo-N count mode, a count boundary is set between 0 and the content of PR. When counting up, at CNTR=PR, the CNTR is reset to 0 and the up count is continued from that point. When counting down, at CNTR=0, the CNTR is loaded with the content of PR and down count is continued from that point. The modulo-N is true bidirectional in that the divide-by-N output frequency is generated in both up and down direction of counting for same N and does not require the complement of N in the UP instance. In frequency divider application, the modulo-N output frequency can be obtained at either the Compare (FLG1) or the Borrow (FLG2) output. Modulo-N output frequency, fN = (fi / (N+ 1) ) where fi = Input count frequency and N = PR. The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7266R1-111196-3 Input/Output Control Register: XIOR and YIOR The functional modes of the programmable input and output pins are written into the IORs. IOR 7 6 5 4 3 2 1 0 0 : Disable inputs A and B 1 : Enable inputs A and B 0 : LCNTR/LOL pin is Load CNTR input 1 : LCNTR/LOL pin is Load OL input 0 : RCNTR/ABG pin is Reset CNTR input 1 : RCNTR/ABG pin is A and B Enable gate 0 0 1 0 0 1 1 1 0 1 : Select IOR : FLG1 pin is Carry/Borrow output and FLG2 pin is U/D (FLAG register bit 5) : FLG1 is IDX (FLAG register bit 6); FLG2 is E (FLAG register bit 4) : FLG1 pin is CARRY output; FLG2 pin is BORROW output : FLG1 pin is COMPARE output; FLG2 pin is BORROW output 0: Select IOR addressed by X/Y input 1: Select both XIOR and YIOR together (Note: D7=1 overrides X/Y input) INDEX CONTROL REGISTERS: XIDR and YIDR Either the LCNTR/LOL or the RCNTR/ABG inputs can be initialized to operate as an index input. When initialized as such, the index signal from the encoder, applied to one of these inputs performs either the Reset CNTR or the Load CNTR or the Load OL operation synchronously with the quadrature clocks. Note that only one of these inputs can be selected as the Index input at a time and hence only one type of indexing function can be performed in any given set-up. The index function must be disabled in non-quadrature count mode. IDR 7 6 5 4 3 2 1 0 0: Disable Index (See Note 3) 1: Enable Index (See Note 3) 0: Negative Index Polarity 1: Positive Index Polarity 0: LCNTR/LOL pin is indexed (See Note 1) 1: RCNTR/ABG pin is indexed (See Note 2) Not used 1 1 : Select IDR : 0: Select IDR addressed by X/Y input 1: Select both XIDR and YIDR (Note: D7=1 overrides X/Y input) Note 1 Function selected for this pin via IOR, becomes the operating INDEX function. : Note 2: RCNTR/ABG input must also be initialized as the reset CNTR input via IOR Note 3: "Enable Index" causes the synchronous mode for the selected index input (as described in Pin 18 and Pin 19 sections of the I/O Description) to be enabled. "Disable Index" causes the non-synchronous mode to be enabled. The input, however, is not disabled in either selection. 7266R1-120899-4 REGISTER ADDRESSING MODES D7 X X X 0 0 1 0 0 1 0 0 1 0 0 1 X X X X D6 X X X 0 0 0 0 0 0 1 1 1 1 1 1 X X X X D5 X X X 0 0 0 1 1 1 0 0 0 1 1 1 X X X X C/D X 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 RD X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 WR X X/Y X 0 1 0 1 X 0 1 X 0 1 X 0 1 X 0 1 0 1 CS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCTION Disable both axes for Read/Write Write to XPR byte segment addressed by XBP (Note 3) Write to YPR byte segment addressed by YBP (Note 3) Write to XRLD Write to YRLD Write to both XRLD and YRLD Write to XCMR Write to YCMR Write to both XCMR and YCMR Write to XIOR Write to YIOR Write to both XIOR and YIOR Write to XIDR Write to YIDR Write to both XIDR and YIDR Read XOL byte segment addressed by XBP (Note 3) Read YOL byte segment addressed by YBP (Note 3) Read XFLAG Read YFLAG X = Don't Care Note 3 : Relevant BP is automatically incremented at the trailing edge of RD or WR pulse Absolute Maximum Ratings: Parameter Symbol Voltage at any input VIN Supply Voltage VDD Operating Temperature TA Storage Temperature TSTG Values VSS - 0.3 to VDD + 0.3 +7.0 -25 to +80 -65 to +150 Unit V V oC oC DC Electrical Characteristics. (TA = -25C to +80C, VDD = 4.5V to 5.5V) Parameter Supply Voltage Supply Current Input Logic Low Input Logic High Output Low Voltage Output High Voltage Input Leakage Current Data Bus Leakage Current Output Source Current Output Sink Current 7266R1-111196-5 Symbol VDD IDD VIL VIH VOL VOH IILK IDLK IOSRC IOSNK Min. Value 4.5 2.0 VDD - 0.5 1.0 5.0 Max.Value 5.5 800 0.8 0.5 30 60 - Unit V A V V V V nA nA mA mA Remarks All clocks off IOSNK = 5mA IOSRC = 1mA Data bus off VO = VDD - 0.5V VO = 0.5V Transient Characteristics. (TA = -25C to +80C, VDD = 4.5V to 5.5V) Parameter Read Cycle (See Fig. 1) RD Pulse Width CS Set-up Time CS Hold Time C/D Set-up Time C/D Hold Time X/Y Set-up Time X/Y Hold Time Data Bus Access Time Data Bus Release Time Back to Back Read delay Write Cycle (See Fig. 2) WR Pulse Width CS Set-up Time CS Hold Time C/D Set-up Time C/D Hold Time X/Y Set-up Time X/Y Hold Time Data Bus Set-up Time Data Bus Hold Time Back to Back Write Delay Quadrature Mode (See Fig. 3-5) FCK High Pulse Width FCK Low Pulse Width FCK Frequency Mod-n Filter Clock(FCKn)Period FCKn frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay X1/X2/X4 Count Clock Pulse Width Index Input Pulse Width Index Skew from A Carry/Borrow/Compare Output Width Symbol tr1 tr2 tr3 tr4 tr5 tr6 tr7 tr8 tr9 tr10 Min. Value 50 50 0 50 10 50 10 50 60 Max.Value 25 - Unit ns ns ns ns ns ns ns ns ns ns Remarks Access starts when both RD and CS are low. Release starts when either RD or CS is terminated. - tW1 tW2 tW3 tW4 tW5 tW6 tW7 tW8 tW9 tW10 30 30 0 30 10 30 10 30 10 60 - ns ns ns ns ns ns ns ns ns ns - t1 t2 fFCK t3 fFCKn t4 t5 fQA, fQB tQ1 tQ2 tidx tAi tQ3 14 14 28 57 115 5t3 28 85 28 35 35 4.3 6t3 - ns ns MHz ns MHz ns ns MHz ns ns ns ns 28 - t3 = (n+1) (t1+t2), where n = PSC = 0 to FFH t4 2t3 t5 4t3 fQA = fQB = 1/8t3 tQ2 = t3 tidx 3t3 tAi t3 tQ3 = t3 Non-Quadrature Mode (See Fig. 6-7) Clock A - High Pulse Width t6 Clock A - Low Pulse Width t7 Direction Input B Set-up Time t8S Direction Input B Hold Time t8H Gate Input (ABG) Set-up Time tGS Gate Input (ABG) Hold Time tGH Clock Frequency (non-Mod-N) fA Clock Frequency (Mod-N) fAN Clock to Carry or Borrow Out Delay 16 16 20 20 20 20 16 20 50 30 25 30 - ns ns ns ns ns ns MHz MHz ns ns ns ns fA = (1/ (t6 + t7) ) t10 = t7 - Carry or Borrow Out Pulse Width Load CNTR, Reset CNTR and Load OL Pulse Width Clock to Compare Out Delay 7266R1-011498-6 t9 t10 t11 t12 INPUTS/OUTPUTS X-AXIS I/Os: XA (Pin 20) XB (Pin 21) Either quadrature encoded clocks or non-quadrature clocks can be applied to XA and XB. In quadrature mode XA and XB are digitally filtered and decoded for UP/DN clock. In non-quadrature mode, the filter and the decoder circuits are by-passed. Also, in non-quadrature mode XA serves as the count input and XB as the UP/DOWN direction control input, with XB = 1 selecting Up Count mode and XB = 0, selecting Down Count mode. X-axis programmable input, to operate as either direct load XCNTR or direct load XOL or synchronous load XCNTR or synchronous load XOL. The synchronous load mode is intended for interfacing with the encoder Index output in quadrature clock mode. In direct load mode, a logic low level is the active level at this input. In synchronous load mode the active level can be programmed to be either logic low or logic high. Both quarter-cycle and half-cycle Index signals are supported by this input in the indexed Load mode. The synchronous function must be disabled in non-quadrature count mode (See description of IDR on P. 4) X-axis programmable input to operate either as direct reset XCNTR or count enable/disable gate or synchronous reset XCNTR. The synchronous reset XCNTR mode is intended for interfacing with the encoder Index output in quadrature clock mode. In direct reset XCNTR mode, a logic low level is the active level at this input whereas in synchronous reset XCNTR mode the active level can be programmed to be either a logic low or a logic high. Both quarter-cycle and half-cycle index signals are supported by this input in the indexed reset CNTR mode. The synchronous function must be disabled in non-quadrature count mode (See description of IDR on P. 4). In count enable/disable mode, a logic high at this input enables the counter and a logic low level disables the counter. X-axis programmable output to operate either as XCARRY (Active low), or XCOMPARE (generated when XPR=XCNTR; Active low), or XIDX (XFLAG bit 6) or XCARRY/XBORROW (Active low). X-axis programmable output to operate as either XBORROW (Active low) or XU/D (XFLAG bit 5) or XE (XFLAG bit 4). X-axis count input A X-axis count input B XLCNTR/XLOL (Pin 19) XRCNTR/XABG (Pin 18) XFLG1 (Pin 22) XFLG2 (Pin 23) Y-AXIS I/Os: All the X-axis inputs/outputs are duplicated for the Y-axis with similar functionalities. YA (Pin 25) YB (Pin 24) YLCNTR/YLOL (Pin 1) YRCNTR/YABG (Pin 28) YFLG1 (Pin 27) YFLG2 (Pin 26) COMMON I/Os: WR (Pin 14) RD (Pin 16) CS (Pin 15) C/D (Pin 13) Write input. Control/data bytes are written at the trailing edge of low level pulse applied to this input. Read input. A low level applied to this input enables the FLAGs and OLs to be read on the data bus. Chip select input. A low level applied to this input enables the chip for Read and Write. Control/Data input. This input selects between a control register or a data register for Read/Write. When low, a data register is selected. When high, a control register is selected. Data Bus input/output. The 8-bit three-state data bus is the I/O port through which all data transfers take place between the LS7266R1 and the host processor. Filter clock input in quadrature mode. The FCK is divided down internally by two 8-bit programmable prescalers, one for each channel. Selects between X and Y axes for Read or Write. X/Y = 0 selects X-axis and X/Y = 1 selects Y-axis. X/Y is overridden by D7 =1 in Control Write Mode (C/D = 1). +5VDC GND D0-D7 (Pins 4-11) FCK (Pin 2) X/Y (Pin 17) VDD (Pin 3) VSS (Pin 12) 7266R1-011498-7 tr1 RD tr2 CS tr4 C/D tr6 X/Y tr8 DB tr9 VALID DATA tr10 tr3 tr5 tr7 VALID DATA FIGURE 1. READ CYCLE tw1 tw10 WR CS tw2 tw4 tw5 tw7 tw9 INPUT DATA tw3 C/D tw6 X/Y tw8 DB INPUT DATA FIGURE 2. WRITE CYCLE t1 t2 FCK t3 FCKn (Note 4) A B t4 t5 t4 t4 t4 t5 FIGURE 3. FILTER CLOCK FCK AND QUADRATURE CLOCKS A AND B Note 4: FCKn is the final modulo-n internal filter clock, arbitrarily shown here as modulo-1. 7266R1-111196-8 UP A tAi B INDEXI (Note 5) X1 CLOCK (Note 6) X2 CLOCK (Note 6) X4 CLOCK (Note 6) tAi DOWN tidx tQ1 tQ2 IDX (Note 7) FIGURE 4. QUADRATURE CLOCK A, B AND INDEX INPUT Note 5: Shown here is positive index with solid line depicting 1/4 cycle index and dotted line depicting 1/2 cycle index. Either LCNTR/LOL or RCNTR/ABG input can be used as the INDEX input. Note 6: X1, X2 and X4 clocks are the final internal Up/Down count clocks derived from filtered and decoded Quadrature Clock inputs, A and B. Note 7: IDX is the synchronized internal "load OL" or "load CNTR" or "reset CNTR" signal based on LCNTR/LOL or RCNTR/ABG input being selected as the INDEX input, respectively. This signal is identical with FLAG register bit 6. UP A B X4 CLOCK (Internal) CNTR CY FFFFFD FFFFFE FFFFFF DOWN t tQ2 0 1 2 3 2 1 0 FFFFFF FFFFFE tQ3 BW COMPARE (Note 8) tQ3 tQ3 CT(FLAG-B1) BT(FLAG-B0) CPT(FLAG-B2) FIGURE 5. CARRY, BORROW, COMPARE, CARRY TOGGLE, BORROW TOGGLE AND COMPARE TOGGLE IN X4 QUADRATURE, NORMAL, BINARY COUNT MODE. Note 8: COMPARE is generated when PR = CNTR. In this timing diagram it is arbitrarily assumed that PR = 1. 7266R1-062896-9 DOWN DIRECTION (B) UP DOWN t8S tGS t8H COUNT IN (A) tGH GATE (ABG) COUNT DISABLE COUNT ENABLE FIGURE 6. COUNT (A), DIRECTION (B) AND GATE (ABG) INPUTS IN NON-QUADRATURE MODE A B t9 CY CNTR DISABLED BW CNTR DISABLED CNTR 999998 999999 t9 t10 CNTR DISABLED 0 999999 0 1 2 1 0 999999 N N-1 N-2 CNTR ENABLED RCNTR CNTR ENABLED LCNTR t11 t11 CNTR ENABLED FIGURE 7. NON-RECYCLE, NON-QUADRATURE, BCD MODE A B UP DOWN CNTR 0 1 2 3 0 t12 1 2 1 0 3 2 1 0 3 2 COMP BW FIGURE 8. MODULO - N, NON-QUADRATURE (Shown with N = 3) A B CNTR COMP BW 0 1 2 UP 3 4 (CNTR FROZEN) 3 DOWN UP 1 0 (CNTR FROZEN) 1 2 2 FIGURE 9. RANGE LIMIT, NON-QUADRATURE(Shown with PR = 4) 7266R1-011498-10 8 WRITE INPUT REG (8) FLAG (8) SBYTE0 SBYTE0 8 BP SBYTE1 SBYTE2 8 SBYTE2 8 8 SBYTE1 PR2 8 (8) 8 PR1 (8) PR0 8 (8) RLD CMR IOR IDR 24 PRO 8 CNTR 24 FCK PRESCALER DIRECTION FCKn ERROR COMPARATOR (24) COUNT CLOCK BYTE 0 DIRECTION BYTE 1 BYTE 2 8 SBYTE2 8 SBYTE1 8 SBYTE0 CLOCK GEN/FILTER B A FCK (24) PSC (8) 24 OL2 8 (8) OL1 8 (8) OL0 8 (8) 8 INTERNAL BUS 8 READ/WRITE I/O BUF 8 DATA-BUS FIGURE 10. SINGLE-AXIS BLOCK DIAGRAM SHOWING MAJOR DATA PATHS 7266R1-111196-11 ISA BUS D7 D6 D5 D4 D3 D2 D1 D0 PC AT/XT LS7266R1 D0 D1 D2 D3 D4 D5 D6 D7 4 5 6 7 8 9 10 11 D0 D1 D2 D3 D4 D5 D6 D7 I4 WR RD C/D X/Y CS I6 I3 I7 I5 IOW IOR A0 A1 AEN A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IOR IOW ADDRESS DECODER FIGURE 11A. LS7266R1 INTERFACE EXAMPLES A1-A23 MC68000 MC68010 MC68HC000 D0-D7 R/W LDS ADDRESS DECODE A1 A2 CS C/D X/Y D0-D7 RD LS7266R1 WR DTACK FIGURE 11B. LS7266R1 INTERFACE EXAMPLES 7266R1-111196-12 C Sample Routines for Interfacing with LS7266R1 #include // IDR #define IDR(arg) (arg | 0xE0) #define XIDR(arg) (arg | 0x60) #define YIDR(arg) XIDR(arg) #define DisIDX 0x00 #define EnIDX 0x01 #define NIDX 0x00 #define PIDX 0x02 #define LIDX 0x00 #define RIDX 0x04 void Init_7266(int Addr); /* Initialize 7266 as follows Modulo N count mode for N = 0x123456 Binary Counting Index on LCNTR/LOL Input CY and BW outputs RCNTR/ABG controls Counters A and B Enabled */ void Init_7266(int Addr) { /Setup IOR Reg. outp(XCMD(Addr),IOR(DisAB + LOL + ABGate + CYBW)); //Disable Counters and Set CY BW Mode //Setup RLD Reg. outp(XCMD(Addr),RLD(Rst_BP + Rst_FLAGS)); //Reset Byte Pointer(BP) And Flags outp(XDATA(Addr),0x06); //Load 6 to PR0 to setup Transfer to PS0 outp(XCMD(Addr),RLD(Rst_E + Trf_PS0_PSC)); //Reset E Flag and Transfer PR0 to PSC outp(XCMD(Addr),RLD(Rst_BP + Rst_CNTR)); //Reset BP and Reset Counter //Setup IDR Reg. outp(XCMD(Addr),IDR(EnIDX + NIDX + LIDX)); //Enable Negative Index on LCNTR/LOL Input //Setup CMR Reg. outp(XCMD(Addr),CMR(BINCnt + ModN + QDX4)); //Set Binary Mondulo N Quadrature X4 7266R1-011598-13 //Setup PR Reg. for Modulo N Counter to 0x123456 outp(XDATA(Addr),0x56); //Least significant Byte first outp(XDATA(Addr),0x34); //then middle byte outp(XDATA(Addr),0x12); //then most significant byte //Enable Counters outp(XCMD(Addr),IOR(EnAB)); } /* Write_7266_PR Input: Addr has Address of 7266 counter. Data: has 24 bit data to be written to PR register */ void Write_7266_PR(int Addr,unsigned long Data); void Write_7266_PR(int Addr,unsigned long Data) { outp(XCMD(Addr),RLD(Rst_BP)); //Reset Byte Pointer to Synchronize Byte Writing outp(XDATA(Addr),(unsigned char)Data); Data >>= 8; outp (XDATA(Addr),(unsigned char)Data); Data >>= 8; outp(XDATA(Addr),(unsigned char)Data); } /* Read_7266_OL Input: Addr has Address of 7266 counter. Output: Data returns 24 bit OL register value. */ unsigned long Read_7266_OL(int Addr); unsigned long Read_7266_OL(int Addr) { unsigned long Data=0; outp(XCMD(Addr),(RLD(Rst_BP + Trf_Cntr_OL)); //Reset Byte Pointer to Synchronize Byte reading and Transferring of data from counters to OL. Data |=(unsigned long)inp(XDATA(Addr)); //read byte 0 from OL lrotr(Data,8); //Rotate for next Byte Data |=(unsigned long)inp(XDATA(Addr)); //read byte 1 from OL lrotr(Data,8); //Rotate for next Byte Data |=(unsigned long)inp(XDATA(Addr)); //read byte 2 from OL lrotr(Data,16); //Rotate for last Byte return(Data); } /* Get_7266_Flags Input: Addr has Address of 7266 counter. returns Flags of counter */ unsigned char Get_7266_Flags(int Addr); unsigned char Get_7266_Flags(int Addr) { return(inp(XCMD(Addr))); } 7266R1-011598-14 |
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