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CXD2085M
ID-1 Detection
Description The CXD2085M is an IC which has the function of detecting ID-1 (EIAJ, CPX1204) from the video signal. Features * Can detect the ID-1 signal on the NTSC video signal. * Includes I2C bus interface. Also, IC can operate without the I2C bus. * Includes a 2-bit general-purpose I/O port function. (When using I2C bus) Applications TVs Structure Silicon gate CMOS IC 16 pin SOP (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.5 to +7.0 * Input voltage VI VSS - 0.5 to VDD + 0.5 * Output voltage VO VSS - 0.5 to VDD + 0.5 * Storage temperature Tstg -55 to +150 Recommended Operating Conditions * Supply voltage VDD 4.75 to 5.25 * Operating temperature Topr -20 to +70
V V V C
V C
Block Diagram
VDIN
7
Slicer ID-1 decoder
16 O169
VSIN
6
Sync separator
15 OLBX
9 SCL I 2C bus interface 10 SDA 13 XI 12 XO
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98511-PS
CXD2085M
Pin Description Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 XRST TST MCON ISET AVDD VSIN VDIN AVSS SCL SDA VDD XO XI VSS OLBX O169 I/O I/O TTL TTL O I CMOS I I/O I I ANALOG ANALOG I/O I I I I Input level TTL1, 4 TTL2 CMOS ANALOG Reset at "0". Test input; connect to Vss. Switching between use and no use of I2C bus; No I2C bus when Low. Bias current setting. Analog power supply. Sync separation input. Data slicer input. Analog GND. CMOS1 I2C bus clock. CMOS1, 3 I2C bus data. Digital power supply. Oscillator connection. (14.318MHz) Oscillator connection, or clock input. Digital GND. Letter-box bit output when ID detection result is output. Or, general-purpose I/O port by the I2C bus setting. Full-mode bit output when ID detection result is output. Or, general-purpose I/O port by the I2C bus setting. 3 Open drain 4 With pull-up resistor Description
1 Schmitt input
2 With pull-down resistor
Connect SCL (Pin 9) to Vss in no I2C bus mode with MCON (Pin 3) to Low. Connect SDA (Pin 10) to Vss or VDD in no I2C bus mode.
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CXD2085M
Electrical Characteristics DC Characteristics (Logic section) Item Output voltage Symbol VOH VOL VOH VOL VOL VIH VIL Input voltage VIH VIL Input voltage VIH VIL Input voltage Input hysteresis width Input leak current Output leak current Input current Input current Feedback resistance Current consumption VIH VIL Vhys Ii IOZ Ii Ii Rfbk IDD VIN = Vss or VDD VIN = Vss or VDD VIN = VSS VIN = VDD XI (Pin 13) = Vss or VDD Clock frequency: 14.318MHz -10 -40 -40 40 250k -100 100 1M 9 0.6 0.4 +10 +40 -240 240 2.5M 0.8 x VDD 0.2 x VDD 0.7 x VDD 0.3 x VDD 2.2 0.8 Conditions IOH = -2mA IOL = 4mA IOH = -3mA IOL = 3mA IOL = 3mA 2.0 0.8 VDD/2 VDD/2 0.4 Min. VDD - 0.8 0.4 (VDD = 5.0V 5%, VSS = 0V, Ta = 25C) Typ. Max. Unit V V V V V V V V V V V V V V V Remarks Pins 15, 16
Output voltage Output voltage Input voltage
Pin 12 Pin 10 Pins 15, 16
Pins 1, 2
Pins 3, 13
Pins 9, 10 Pins 9, 10 Pin 1
A Pins 3, 9 A Pins 10, 15, 16 A Pin 1 A Pin 2 Between Pins 12 and 13
mA Sum of Pins 5 and 11
AC Characteristics Item Clock frequency Symbol fxi Conditions Min.
(VDD = 5.0V 5%, VSS = 0V, Ta = 25C) Typ. 14.318 Max. Unit Remarks
Pin 13 input, or MHz oscillator between Pins 12 and 13
I/O Pin Capacitance Item Input pin capacitance Output pin capacitance I/O pin capacitance Symbol CIN COUT CI/O Conditions VDD = VI = 0V, f = 1MHz VDD = VI = 0V, f = 1MHz VDD = VI = 0V, f = 1MHz -3- Min. Typ. Max. Unit 9 11 11 pF pF pF Remarks
CXD2085M
Pin and Electrical Characteristics Analog Section Pin No. 5 Symbol Equivalent circuit Not connected to VDD (Pin 11) in the IC. Not connected to Vss (Pin 14) in the IC.
AVDD
(VDD = 5.0V 5%, Vss = 0V, Ta = 25C) Description Analog power supply. Connect a low-noise power supply from the digital system. Analog ground. Connect to the same potential as Vss.
AVDD
8
AVSS
Bias setting. 4 ISET
4
Connect to AVDD (Pin 5) with 33k.
AVSS
AVDD
Sync tip clamp, sync separation input. Input with the capacitance coupled.
6
VSIN
6
AVSS
Clamp voltage 1.5V
AVDD
Pedestal clamp, ID signal data slice input. Input with the capacitance coupled.
7
VDIN
7
AVSS
Clamp voltage 1.5V
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CXD2085M
1. Description of ID-1 (transmission system of additional video information, aspect ratio identification) As shown in the table below, the additional video information consists of 14-bits data, and a 6-bit CRCC is added to the data to form 20-bit data in total. This is carried on lines 20 and 283 in the vertical blanking area of the NTSC video signal. Table 1. Description of ID-1 signal Bit No. 1 2 3 4 5 6 4bits 4bits Description Transmission aspect ratio Screen display format Not defined
"1" Full-mode (16:9) Letter-box --
"0" 4:3 Normal --
A WORD0 B WORD1 WORD2
Identification information relating to the video signals and other signals (audio signals, etc.) transmitted simultaneously with the video signals Identification signal dependent on WORD0 Identification signal and other information dependent on WORD0 (From the Provisional standard of EIAJ, CPX-1204)
In the CXD2085M, the above 14-bit data are obtained in the I2C bus for I2C bus mode. Also, first two bits only can be output to OLBX (Pin 15) and O169 (Pin 16) set as the direct output pins.
2. Difference between ID-1 Data from the I2C Bus and Direct Output Pin
2 ID-1 decoding 14
Direct pin outputs OLBX, O169
Data validity determination
I2C VBVLD
To microcomputer
CXD2085M
As shown in the figure above, the data validity determination which detects that the valid ID signal is exist or not, and the decoded result are obtained independently during ID-1 decoding. These two results are output to the direct output pins after taking their logical AND. Processing inside the microcomputer which has acquired the information from the I2C bus is performed either by simply outputting this data directly to the pins or by taking the logical AND as above. In addition, performing the processing when the data validity determination (VBVLD) is "1" and the decoding results bits 1 and 2 are "0" allows the video to be identified as 4:3 video. 3. General-Purpose I/O Port Function In I2C bus mode, the CXD2085M can use two pins OLBX (Pin 15) and O169 (Pin 16) as the general-purpose I/O ports. The three types of setting are available; both two pins for inputs, for outputs, and one for input and another for output. While resetting by XRST (Pin 1) in I2C bus mode, two pins are set as the general-purpose input ports. Perform the power-on reset by XRST when there is a possibility that the IC external circuit and the OLBX and O169 signals could collide. Be sure to set the OLBX and O169 pins as the output pins when they are not used. -5-
CXD2085M
4. Clock The CXD2085M requires a 4fsc clock (14.318MHz). When using a crystal oscillator, connect it between XI (Pin 13) and XO (Pin 12). When inputting the clock from an external source, input it to XI (Pin 13). 5. Various Settings and Data I/O The various settings and data I/O can be made by using the pin directly or using I2C bus interface. 5-1. I2C bus By setting MCON (Pin 3) to High, the various settings and data extraction can be made with the I2C bus. The CXD2085M supports the I2C bus slave RECEIVER and slave TRANSMITTER modes. The slave address is 40 (H). In addition to standard mode (max. 100K bits/s), this IC also supports high-speed mode (max. 400K bits/s). Even when the power supply falls to 0V, it does not occupy the I2C bus. However, the absolute maximum ratings should not be exceeded. The I2C bus transmission process is shown in the figure below. The number of transmission data is one byte for write (RECEIVER) and two bytes for read (TRANSMITTER). There is no sub-address setting function. Note that the I2C bus transmission cannot be performed during resetting by the XRST pin (Pin 1). Data write (RECEIVER mode) 7654321 Sm SLAm 0 Wm 1 As 76543210 DATAm 1 As P
Data read (TRANSMITTER mode) 7654321 Sm SLAm 0 Rm 1 As 76543210 DATAs 1 Am 76543210 1 P
DATAs XAm
Symbol m s S P SLA DATA W R A XA
Description from Master to Slave from Slave to Master Start Condition Stop Condition Slave Address Data 0: Write 1: Read Master Slave Slave Master
Clock pulse for Acknowledgment (SDA: L) Acknowledgment none (SDA: H) -6-
CXD2085M
Table 2. List of I2C bus controls R/W Bit bit7 MSB bit6 Symbol POLBX PO169 Description Output value when the OLBX pin used as the general-purpose output port. Output value when the O169 pin used as the general-purpose output port. Settings whether the OLBX and O169 pins are used as the direct output pin of decoding result or as the general-purpose I/O port. bit5 PORT2 PORT2 PORT1 OLBX pin function 1st byte WR bit4 PORT1 O169 pin function Direct output 0 0 Direct output 0 1 1 0 1 1
General-purpose I/O port Output Input Input
General-purpose I/O port Output Output Input
bit3 bit2
TST XJGLK
Test signal. Be sure to set to Low. Normally set to Low. When Low, the decoding result is held during the VCR variable-speed playback for home use. When High, it is not held. Normally set to Low. When Low, the ID signal can be detected not only for the line where it should locate but for one line before and after it. When High, decoding is performed only to the line where the ID signal should locate. Normally set to Low. When High, the decoding function is reset. Reset immediately after switching the input signal such as for TV channels. ID decoding result 5th bit. ID decoding result 4th bit. ID decoding result 3rd bit. ID decoding result 1st bit. ID decoding result 2nd bit. High when the valid ID signal is detected. Input value when OLBX is used as the general-purpose input port. Input value when O169 is used as the general-purpose input port. ID decoding result 14th bit when O169 is used as the general-purpose output port or as the direct output. ID decoding result 13th bit. ID decoding result 12th bit. ID decoding result 11th bit. ID decoding result 10th bit. ID decoding result 9th bit. ID decoding result 8th bit. ID decoding result 7th bit. ID decoding result 6th bit. -7-
bit1
LNJ1
bit0 LSB bit7 MSB bit6 bit5 1st byte bit4 bit3 bit2 bit1 bit0 LSB RD bit7 MSB bit6 bit5 2nd byte bit4 bit3 bit2 bit1 bit0 LSB
RES ID5 ID4 ID3 ID1 ID2 VBVLD IOLBX IO169 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6
CXD2085M
5-2. No bus mode No bus mode is established when setting the MCON pin (Pin 3) to Low and then the CXD2085M can be operates without using the I2C bus. In this case, the contents to be set by the I2C bus is fixed as shown below. OLBX and O169 obtain the decoding results as they become the direct output pins. Table 3. Settings in No Bus Mode (Pin 3, MCON = Low) R/W Bit bit7 MSB bit6 bit5 WR 1st byte bit4 bit3 bit2 bit1 bit0 LSB Symbol POLBX PO169 PORT2 PORT1 TST XJGLK LNJ1 RES Contents Fixed to Low. In no I2C bus mode, there is no general-purpose I/O port function and this bit's operation is not affected. PORT1 and PROT2 fixed to Low. The OLBX and O169 pins are the direct output pins of the ID decoding result. SCL (Pin 9) input reflected as it is. Therefore, connect the SCL pin to Vss in no I2C bus mode. SCL (Pin 9) input reflected as it is. Fixed to Low as the SCL pin is surely connected to Vss. Fixed to Low. When resetting is required, use the XRST pin (Pin 1).
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CXD2085M
Application Circuit
For 2Vp-p input amplitude, using the I2C bus
VDD = 5.0V 5% 16mA
5 AVDD 2.2k 8 AVSS
11 VDD XRST MCON 1 3
33k 4 ISET
SDA 10 I2C SCL 9 10k OLBX 15 CXD2085M 10k O169 16 1
2.2k
1
100 1000p
10 6 VSIN TST 2
47 Vin
VSS 14 0.1 100 7 10k 4.7k 470 VDIN 22p XO 12 14.3MHz XI 13 22p
100 IRE 2.0Vp-p 0 IRE -40 IRE
1 When OLBX (Pin 15) and O169 (Pin 16) are not used, connect the pull-down or pull-up resistor to these pins.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXD2085M
Application Circuit
For 1Vp-p input amplitude not using the I2C bus
VDD = 5.0V 5% 16mA
5 AVDD 2.2k 8 AVSS
11 VDD XRST MCON 1 3
33k 4 ISET
SDA 10 SCL 9
OLBX 15 CXD2085M 1 100 1000p TST 2 10 6 47 Vin VSS 14 0.1 100 7 10k 4.7k 470 VDIN VSIN O169 16
Decoding result output
22p XO 12 14.3MHz XI 13 22p
100 IRE 1.0Vp-p 0 IRE -40 IRE
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXD2085M
Package Outline
Unit: mm
16PIN SOP (PLASTIC)
+ 0.4 9.9 - 0.1
+ 0.4 1.85 - 0.15
16
9 0.15 + 0.2 0.1 - 0.05
+ 0.3 5.3 - 0.1
7.9 0.4
0.45 0.1
1.27
+ 0.1 0.2 - 0.05
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PACKAGE MASS SOP-16P-L01 SOP016-P-0300 LEAD MATERIAL COPPER ALLOY 0.2g LEAD TREATMENT EPOXY RESIN SOLDER PLATING
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0.5 0.2
1
8
6.9

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