 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PM6341 Summary Information E1 TRANSCEIVER FEATURES * Monolithic single chip device which integrates a full-featured E1 framer with on-chip analog line interface. * Provides frame synchronization and frame generation for a G.704/G.706 2.048 Mbit/s signal with capability to support the optional signalling and CRC multiframes. * Supports HDB3 or AMI line coding and accepts gapped data streams to support higher rate demultiplexing. * Supports both 75 Ohm and 120 Ohm G.703 line interfaces. * Provides Channel Associated Signalling extraction/insertion, programmable idle code substitution, digital milliwatt code substitution, data inversion and up to 3 multiframes of signalling debounce on a per channel basis. * Optionally extracts/inserts the datalink from/to timeslot 16 to receive/transmit Common Channel Signalling. * Pin compatible with the PM4341A T1XC T1 Transceiver. * Software compatible with the PM6344 EQUAD E1 Framer, and PM6388 EOCTL E1 Framer. * Provides an 8-bit microprocessor bus interface for configuration, control and status monitoring. * Low-power 5V CMOS technology. * Available in a high density 80-pin (14 by 14mm) PQFP or in a 68-pin PLCC package. A(7-0) R DB WRB C SB ALE INTB R STB M P IF MIC ROPRO CESSOR INTERFAC E E1XC RECEIVE SECTION * Provides indications of loss of signal, loss of frame alignment (OOF), loss of signalling multiframe alignment and loss of CRC multiframe alignment. * Declares red and AIS alarms using Q.516 recommended integration periods * Supports line and path performance monitoring according to ITU-T recommendations. Accumulators are provided for CRC-4 errors, Far End Block Errors, Frame sync errors, and Line Code Violations. * Provides an integral HDLC/LAPD interface which may be used for terminating a CCS or National Bits datalink. * Provides a two frame elastic store for jitter and wander attenuation. * Provides programmable trunk conditioning on a per channel basis. TRANSMIT SECTION * Supports transmission of AIS, timeslot 16 AIS, remote alarm signal or remote multiframe alarm signal. * Provides an integral HDLC/LAPD interface which may be used for generating a CCS or National Bits datalink. * Provides an integrated digital phase locked loop for generation of a low jitter transmit clock. * Provides a FIFO buffer for jitter attenuation and rate conversion. * Provides programmable trunk conditioning which forces trouble code substitution and signalling conditioning on a per channel basis. BLOCK DIAGRAM TCLKI B TIF BAC KPLANE TRANSMIT INTERFAC E TRA N TRANSMITTER: FRAME GENERATION, ALARM IN SER TIO N, TRU NK CON D ITION ING LIN E C OD IN G TOPS TIM ING OPTIO NS TR A N S M ITT E R XPLS ANALO G PULSE GEN ER ATOR BTPCM /BTDP BTSIG/BTD N BTFP BTC LK TAP D JA T D IGITAL JITTER ATTEN UATOR TAN PCSC XBOC INTERN AL BUS PER -C H AN C ON TR : SIG NAL, IDLE C ON T BITOR IEN TED C OD E TRANS X FD L H DLC TRANSMITTER TC D TIF D IGITAL TRANSMIT INTERFAC E TCLKO TDP/TD D TDN /TFLG TDLCLK/ TDLUD R TDLSIG/ TDLINT APPLICATIONS * E1 & E3 Multiplexers * Digital Loop Carriers * E1 Frame Relay Interfaces D (7-0) BRC LK * E1 ATM UNI Interfaces * E1 Channel Service Units (CSUs) and Data Service Units (DSUs) * Digital Access and Cross-Connect Systems (DACS) and Electronic Digital Cross-Connect Systems (EDSX) * SDH Add/Drop Multiplexers (ADM) * ISDN Primary Rate Interfaces (PRI) * Digital Private Branch Exchanges (PBX) * E1 & E3 Test Equipment PMC-920109(R6) BRFPI XCLK/VCLK R AS R EF R RC R SLC PMON R E C E IV E R S IG X SIG NALLIN G EXTRACT, TRU NK C ON DITION ANALO G PULSE SLIC ER PER F MONITOR C OU NTER S E LS T ELASTIC STO RE BRPCM /BR DP B R IF BRSIG/BR DN BRFPO R CLKI R DP/R DD / SDP R DN /RLCV/ SDN D R IF D IGITAL R EC EIVE INTERFAC E C DR C C LOCK AN D D ATA R EC OVER Y FRM R FR AMER: FRAME ALIG NM EN T, ALARM D ETEC TION R B OC BIT OR IEN TED C OD E D ETEC TOR BAC KPLANE R EC EIVE INTERFAC E R DPCM/RPCM R CLKO R FP R FD L H DLC R EC EIVER R DLSIG/ R DLINT R DLCLK/ R DLEOM (c) 1998 PMC-Sierra, Inc. March, 1998 PM6341 E1XC Summary Information E1 TRANSCEIVER TYPICAL APPLICATIONS: 1/0 CROSS-CONNECT WITH E1 INTERFACE: STo1 STo2 STo4 STo3 STo5 STo6 STo7 STi7 D ig ital C rosspo int Sw itch STi2 STi3 STi4 STi5 STi6 STi1 STi8 BR SIG BR SIG STo8 BR SIG BR PC M BR PC M BR PC M PM C PM 63 41 E1XC TAN R EF R AS TAP TAP PM C PM 63 41 E 1X C TAN R EF R AS TAP PM C PM 63 41 E1XC R AS R EF TAN TAP PM C PM 63 41 E1 XC TAN R AS R EF Receive E1 Transmit E1 Receive Transmit Receive Transmit FULLY CHANNELIZED QUAD E1 HDLC CARD: E1 PM C PM 6341 E1XC E1 PM C PM 6341 E1XC Transmit Receive E1 E1 E1 E1 E1 E1 Processor PM C PM 7366 FREEDM -8 H DLC Controller E1 PM C PM 6341 E1XC Packet M em o ry E1 PM C PM 6341 E1XC PCI Bus Head Office: PMC-Sierra, Inc. Suite 105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn:Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com BR PC M BTPC M BTPC M BTPC M BTPC M BR SIG BTSIG BTSIG BTSIG BTSIG PMC-920109(R6) (c) 1998 PMC-Sierra, Inc. March, 1998 |
Price & Availability of PM6341
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |