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Philips Semiconductors Linear Products
Product specification
6-Bit A/D converter (parallel outputs)
NE5037
DESCRIPTION
The NE5037 is a low cost, complete successive-approximation analog-to-digital (A/D) converter, fabricated using Bipolar/I2L technology. With an external reference voltage, the NE5037 will accept input voltages between 0V and VREF. An external START pulse of at least 300ns in duration will provide the 6-bit result of the conversion in parallel format. Full conversion with no missing codes occurs in 9s.
PIN CONFIGURATION
N Package
VCC 1 VREF 2 16 B5 (MSB) 15 B4 14 B3 13 B2 12 B1 11 B0
VIN 3 ANALOG GND 4 5
FEATURES
DIGITAL GND
* TTL-compatible inputs and outputs * 3-State output buffer * Easy interface to CMOS microprocessors * Fast conversion--9s * Guaranteed no missing codes over full temp range * Single-supply operation, +5V * Positive true binary outputs * High-impedance analog inputs
APPLICATIONS
CLK 6 START 7
10 EOC 9 TOP VIEW EO
CS 8
* P-based appliances * Light level monitors * Head position sensing * Electronic toys * Joystick interface
* Temperature control
ORDERING INFORMATION
DESCRIPTION 16-Pin Plastic Dual In-Line Package (DIP) TEMPERATURE RANGE 0 to +70C ORDER CODE NE5037N DWG # 0406C
BLOCK DIAGRAM
VCC
1
VREF
2
IIN V/I
1/2 LSB 6-BIT DAC
IO
COM
DB
VIN AGND DGND CLK
16
DB5
3 4
5 6
V/I
CONTROL LOGIC
SAR
11
DB
DBO
EOC
10
EOC
7 START CS
8
9 EOC
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853-0939 13721
Philips Semiconductors Linear Products
Product specification
6-Bit A/D converter (parallel outputs)
NE5037
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VREF VIN(Analog) VIN(Digital) DOUT Power supply voltage Reference voltage Analog input voltage Digital input voltage (CS, OE, START, CLK) Data outputs (DB0 to DB5) 3-state mode Enabled mode (each output) EOC GND TA TSTG TSOLD PD End of conversion Analog GND to digital GND Operating temperature range Storage temperature range Lead soldering temperature (10 seconds) Maximum power dissipation, TA=25C (still-air)1 N package NOTES: 1. Derate above 25C at the following rates: N package=11.6mW/C 1450 mW 7 5 VCC 1 0 to 70 -65 to 150 300 V C C C V mA PARAMETER RATING 7 7 7 7 UNIT V V V V
DC ELECTRICAL CHARACTERISTICS
VCC=5.0V; VREF=2.0V; Clock=1MHz; 0C TA 70C unless otherwise specified. Typical values are specified at 25C SYMBOL Resolution Relative accuracy1,2 VCC FS ZS PSR IIN IREF RIN VIH VIL IIH IIL IOH IOL IOZ ICC PD Positive supply voltage Full-scale gain error2,3,4 Zero-scale offset error2 Power supply rejection, Max change in full-scale2 Analog input bias current Reference bias current Analog input resistance Logic "1' input voltage Logic "0' input voltage Logic "1' input current Logic "0' input current Logic "1' output current5 Logic "0' output current5 3-State leakage current Positive supply current Power dissipation 2.4VVOH VOL0.4V 300 1.6 0.1 18 40 24 132 1 VREF=2.0V, TA=25C VREF=2.0V, TA=25C VREF=2.0V, 4.75VVCC5.5V 0VIN2.5V 0VREF2.5V 3 2.0 0.8 10 10 +4.75 PARAMETER TEST CONDITIONS LIMITS Min 6 Typ 6 1/4 +5.0 1 1/2 1/2 1 1 30 Max 6 1/2 +5.50 2 -1/2, +2 1 10 10 UNIT Bits LSB V LSB LSB LSB A A M V V A A A mA A mA mW
NOTES: 1. Relative accuracy is defined as the deviation of the code transition points from the ideal code transition points on a straight line drawn from zero-scale to full-scale of the device. 2. Specifications given in LSBs refer to the weight of the least significant bit at the 6-bit level which is 1.56% of the full-scale voltage. 3. Full-scale gain error is the deviation of the full-scale code transition point (111110 to 111111) from its ideal value. 4. The analog input voltage (VIN) range is 0V to VREF nominally, with the output remaining at 111111 even though the input may increase from VREF to VCC. (For optimum performance, VREF can be any value from 1.5V to 2.5V.) 5. The data outputs have active pull-ups. The EOC line is open-collector with a nominal 5k internal pull-up resistor.
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Philips Semiconductors Linear Products
Product specification
6-Bit A/D converter (parallel outputs)
NE5037
AC ELECTRICAL CHARACTERISTICS
VCC=5.0V; VREF=2.0V; Clock=1MHz; 0C TA 70C unless otherwise specified. Typical values are specified at 25C (Refer to AC test figures.) SYMBOL fMAX tW PARAMETER Maximum clock frequency Start pulse width Minimum positive/negative clock pulse width tCONV tP (OUT DATA) tP (OUT EOC) tP (3-STATE) Conversion time Propagation delay1 Data out EOC 3-State Data OE Clock OE TA=25C tR=tF20ns TA=25C tR=tF20ns TA=25C tR=tF20ns Propagation delay2 Propagation delay, 3-State TO FROM TEST CONDITIONS LIMITS Min 1 300 300 9 500 800 500 Typ Max UNIT MHz ns ns Clock cycles ns ns ns
NOTES: 1. Propagation delay of data outputs is defined as the delay in the data outputs reading their final value after the low going edge of OE. 2. Propagation delay of EOC is defined as the delay in EOC going low, following the low going edge of the 9th clock pulse after the start pulse.
CIRCUIT DESCRIPTION
NE5037 is a complete 6-bit, parallel output, microprocessor compatible, A/D converter which incorporates the successive-approximation method. The chip includes the internal control logic, the successive-approximation register (SAR), 6-bit DAC, comparator and output buffers. An externally-generated clock source (max frequency=1MHz) must be provided to Pin 6. An external reference voltage supplied to Pin 2 sets the full-scale range of the A/D converter. The CS pin must be at a low level prior to the start of the conversion process. Upon receipt of a START pulse, the internal control logic resets the SAR. On the first low-going edge of the clock pulse, successive approximation conversion commences. Successive bits beginning with the MSB (D5) are supplied to the input of the internal 6-bit current output DAC by the I2L successive approximation register.
CS
The comparator determines whether the output current of the DAC is greater or less than the input current, which is converted from the unknown analog input voltage through the V/I converter. If the DAC output is greater, that bit of the DAC is set to "0' and the corresponding output buffer goes to "0' simultaneously. If it is less, it stays at `1' and the output buffer also stays at `1'. On successive clock pulses, successive bits of the DAC are tried and the corresponding output buffer represents the bits of the DAC. On the eighth low-going edge of the clock pulse (after the receipt of the start pulse), the EOC pin goes low, thereby indicating that the conversion is complete. The output data is now valid. In order to access the result of the conversion, the OE pin must be set to a low level. EOC is reset to a high state when OE is low. When OE is in a "1' state, the output buffers are in a high impedance state.
DON'T CARE
START
CLK
OE
EOC HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE
DATA OUTPUTS
DATA READY HIGH AVAILABLE HIGH AVAILABLE
Figure 1. Timing Diagram
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EE EE EE EE
EEE EEE EEE EEE
Refer to Figure 1 for the timing diagram.
EEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEEEEEE
Philips Semiconductors Linear Products
Product specification
6-Bit A/D converter (parallel outputs)
NE5037
TRANSFER CHARACTERISTICS
The ideal transfer characteristic of the NE5037 is shown in Figure 2. The NE5037 is designed to have a nominal LSB offset so that the code transition points are located LSB on either side of the exact analog inputs for a given code. Thus the first transition (000000 to 000001) will occur at an input of LSB (15.63mV with a VREF of 2.0V). Subsequent transitions will occur at nominal increments of 1 LSB. The last transition (to full-scale--111111) will occur at 62.5 LSB (1.953V at VREF of 2.0V).
The reference input and the analog voltage input must both remain stable during conversion to insure accuracy and proper operation. This can be done by adequately bypassing these inputs and/or keeping the impedance of these inputs at or below 2k.
111111 1DIGITAL OUTPUT CODE 111110 111101 111100 LSB + 000011 000010 000001 000000 121/2 LSB 123/2 LSB 125/2 LSB 119/2 LSB 1/2 LSB 3/2 LSB 5/2 LSB 7/2 LSB V REF 64
LAYOUT PRECAUTIONS
Analog ground (Pin 4) and digital ground (Pin 5) are not connected internally and should be connected together as close to the device as possible for optimum performance. The circuit will operate with as much as 200mV between the two grounds but some degradation will occur. The leads to the analog inputs should be kept as short as possible to minimize noise pick-up. Input bypass capacitors from the analog inputs to ground will eliminate noise pick-up. Power supplies should be decoupled with at least 1F located close to the device to minimize the effects of noise spikes.
FOR 111111 OUTPUT VIN = VREF -- LSB -- 1/2 LSB BUILT-IN OFFSET + 62.5LSB + 62.5 V 64 REF
ANALOG INPUT
Figure 2. Ideal Transfer Characteristics
August 31, 1994
585
Philips Semiconductors Linear Products
Product specification
6-Bit A/D converter (parallel outputs)
NE5037
TYPICAL PERFORMANCE CHARACTERISTICS
Zero-Scale Offset Error vs Temp
+1 Z-F OFFSET ERROR (LSB's) Z-F OFFSET ERROR (LSB's)
Zero-Scale Offset Error vs vcc
+1 Z-F OFFSET ERROR (LSB's)
Zero-Scale Offset Error vs vREF
+1
+3/4
VCC = 5.0V VREF = 2.0V
+3/4
VREF = 2.0V TA = 25oC
+3/4
VCC = 5.0V TA = 25oC
+31/2
+31/2
+31/2
+1/4
+1/4
+1/4
0 0 25 50 TA (oC) 75
0 4.75
0 5.0 5.25 5.5 1.5 2.0 2.5 VCC (VOLTS DC) VREF (VOLTS DC)
Full-Scale GAIN Error vs Temp
+2 Z-F GAIN ERROR (LSB's) Z-F GAIN ERROR (LSB's) +2
Full-Scale Gain Error vs vcc
+2 Z-F GAIN ERROR (LSB's)
Full-Scale Gain Error vs vREF
VCC = 5.0V TA = 25oC +1 1/2
+1 1/2
VCC = 5.0V VREF = 2.0V
+1 1/2
VREF = 2.0V TA = 25oC
+1
+1
+1
+1/2
+1/2
+1/2
0
0
25
50 TA (oC)
75
0 4.75
0 5.0 5.25 5.5 VCC (VOLTS DC)
1.5
2.0
2.5
VREF (VOLTS DC)
IOL vs Temp (Data Output)
4 4
IOL vs Temp (EOC)
10.0 VCC = 5.0V VCC = 4.75V 2
IOH vs Temp (Data Output)
VCC = 5.0V 9.0 I OH(mA)
3 I OL(mA)
VCC = 5.0V I OL(mA)
3
2
VCC = 4.75V
8.0
VCC = 4.75V
1 IOL @ VOL = 0.4VDC 0 0 25 TA 50 (oC) 75
1 IOL @ VOL = 0.4VDC 0 0 25 50 TA (oC) 75
7.0 IOL @ VOL = 2.4VDC 6.0 0 25 50 TA (oC) 75
ICC vs Temp (EOC)
17 VREF = 2.0V 0.4 I OH(mA) VCC = 5.5V 15 VCC = 4.75V 14 0.5
IOH vs Temp (EOC)
VCC = 5.0V
16 I CC(mA)
VCC = 4.75V 0.3
0.2 IOH @ VOH = 2.4VDC
13 0 25 50 TA (oC) 75
0.1 0 25 50 TA (oC) 75
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Philips Semiconductors Linear Products
Product specification
6-Bit A/D converter (parallel outputs)
NE5037
AC TEST CIRCUITS AND WAVEFORMS
VCC = 5V VREF = 2V VIN = 2.1V NE5037 1MHz CLK (TTL) START PULSE (TTL LEVEL) 15pF 10k 1R = tF = 20ns 90% 50% 10% tF 50% 90% 50% 10%
tp (DATA) DATA OUTPUT OE
EO (TTL LEVEL)
tR 10%
DB (0 TO 5)
tp (3-STATE) tp (DATA)
Propagation Delay Time tP (DATA) and TP (3-state)
1R = tF = 20ns VCC = +5V VCC = 5V VREF = 2V VIN = 0.1V NE5037 1MHz CLK (TTL) START PULSE (TTL LEVEL) EO (TTL LEVEL) 10K DATA OUTPUT 15pF VCC tF tR VCC 50% GND tp (DATA) tp (3-STATE) VCC OE 50% GND 90% 50% 10%
DB (0 TO 5)
10%
Data Output High
90% VCC = +5V VREF = +2V NE5037 1MHz TTL (CLOCK) START PULSE (TTL LEVEL) VCC CLK 1 10k EOC START EO = VCC tW EOC tR 10%
90% 10% 2 tF 50% 9
50% tp (EOC)
Propagation Delay Time EOC tP(EOC)
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Philips Semiconductors Linear Products
Product specification
6-Bit A/D converter (parallel outputs)
NE5037
+5V LM334 0.1F 220 0.1F 160 1000pF RANGE 100 3 5.76K (F) 3.2 K (C) 1/2 NE5512 10K 6 1/2 NE5512 7 4 5+ 11-16 6 6-BIT DATA BUS 4 5 NE5037 A/D 2 7 STRT 8 CS 9 OE 10 EOC CONTROLLER 330 0.1F 1
1K BIAS ADJ. 1K
2 - 3 +
8
-
820
0.1F
910 DISPLAY READING
oF oC
VOLTAGE TP1 1.5895 0.8742
TP1*
-3V
TP2
TP3
CLK
a. Temperature Sensor +5V 20 LM334 0.1F 220 0.1F 160 1000pF RANGE 100 3 5.76K (F) 3.2 K (C) 1/2 NE5512 10K 6 1/2 NE5512 7 4 5+ 6 7 9 4 5 NE5037 A/D 2 330 0.1F 1 16 14 15 3 14 4 13 13 12 6 11 11 10 9 8 N74LS174 6-BIT LATCH 19 18 17 15 16 2 5 12 7 10 5 4 3 2 1 10 15 Q1 2N3906 820 0.1F 910 N82S147 PROM (DECODER/ DRIVER) 14 13 12 11 9 8 7 6 DIS 1 10's OPEN 0.22F
1K BIAS ADJ. 1K
2 - 3 +
8
-
CLK DIS 2 10's TP1* -3V TP2 TP3 CLK
DISPLAY READING
oF oC
U7 PIN 18 GND HIGH
VOLTAGE TP1 1.5895 0.8742
Q2 2N3986
b. Digital Thermometer
Figure 3. August 31, 1994 588
Philips Semiconductors Linear Products
Product specification
6-Bit A/D converter (parallel outputs)
NE5037
APPLICATION
* 0 to 63C Temperature Sensor
CIRCUIT DESCRIPTION
The temperature sensor of Figure 3 provides an input to Pin 3 of the NE5037 of 32mV/C. This 32mV is the value of one LSB for the NE5037. The LM334 is a three-terminal temperature sensor and provides a current of 1A for each Kelvin. The first section of the dual op amp is connected as a trans-impedance amplifier to convert the current from the LM334 to a voltage, which is amplified and inverted by the section amplifier. Note that the first amplifier requires different values of feedback resistance for C and F. The NE5512 was chosen for its low temperature coefficient of input bias current as excessive IOS tempco would degrade temperature tracking. To read temperature, conversion is started by sending a momentary low signal to Pin 7 of the NE5037. When Pin 10 of the NE5037 goes low, conversion is complete and a low is applied to Pin 9 of the NE5037 to read data on Pins 11 through 16. Note that this temperature data is in straight binary format. The controller can be a microprocessor in a temperature control application, or discrete circuitry in a simple temperature reporting application. A temperature reporting (digital thermometer) circuit is shown in Figure 3b. The NE5037 A/D converter is connected in a continuous conversion mode by connecting together Pins 7, 9, and 10. Should this pin be momentarily shorted to any relatively low impedance point, conversion will stop. Conversion will resume upon interruption and restoration of the power. These pins are also
connected to the latch enable of a 6-bit latch because the data at the converter output is available for only a short time when the converter is in the continuous conversion mode. The (P)ROM) must have the correct code for converting the data from the NE5037 (used as address for the (P)ROMs) to the appropriate segment drive codes. Note that the circuit of Figure 3b shows a circuit which can be used to display either Fahrenheit or Centigrade temperatures. The displayed output could easily be converted to degrees Fahrenheit (F) by the controller of Figure 3a or through the (P)ROMs of Figure 3b. When doing this, a third (hundreds) digit (P)ROM and display will be needed for displaying temperatures above 99F. An inexpensive clock can be made from NAND gates or inverters, as shown in Figure 3c.
CIRCUIT ADJUSTMENT
The circuit should be at a known ambient temperature for a few minutes before making adjustments. 14.Adjust bias adjust potentiometer for the voltage indicated in the chart in Figure 3b. 15.With the circuit (or sensor U3, if it is remotely located) at a known temperature for 2 to 3 minutes, adjust range control for a correct reading on the displays. This should provide an accuracy of 3 counts (3 F or C). Higher accuracy may require NE5037 reference voltage regulation.
August 31, 1994
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