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DS2196 T1 Dual Framer LIU
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2196 T1 dual framer LIU is designed for T1 transmission equipment. The DS2196 combines dual optimized framers together with a LIU. This combination allows the users to extract and insert facility data-link (FDL) messages in the receive and transmit paths, collect line performance data, and perform basic channel conditioning and maintenance. The DS2196 contains all of the necessary functions for connection to T1 lines whether they are DS1 long haul or DSX-1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0ft to over 6000ft in length. The device can generate both DSX-1 line buildouts as well as CSU line buildouts of -7.5dB, -15dB, and -22.5dB. The on-board jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. The device contains a set of internal registers that the user can access and use to control the unit's operation of the unit. Quick access through the parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the latest T1 specifications.
FEATURES

Two full-featured framers and a short/long-haul line interface unit (LIU) in one small package Based on Dallas Semiconductor's single -chip transceiver (SCT) family Two HDLC controllers with 64-byte buffers that can be used for the FDL or DS0 channels Supports NPRMs and SPRMs as per ANSI T1.403-1998 Can be combined with a short/long-haul LIU or a HDSL modem chipset to create a low-cost office repeater/NIU/CSU, or a HDSL1/HDSL2 terminal unit with enhanced monitoring and data link control Supports fractional T1 Can convert from D4 to ESF framing and ESF to D4 framing 32-bit or 128-bit crystal-less jitter attenuator Can generate and detect repeating in-band patterns from 1 to 8 bits or 16 bits in length Detects and generates RAI-CI and AIS-CI Generates DS1 idle codes On-chip programmable BERT generator and detector All key signals are routed to pins to support numerous hardware configurations Supports both NRZ and bipolar interfaces Can create errors in the F-bit position and BERT interface data paths 8-bit parallel control port that can be used directly on either multiplexed or nonmultiplexed buses (Intel or Motorola) IEEE 1149.1 JTAG Boundary Scan 3.3V supply with 5V tolerant inputs and outputs 100-pin LQFP (14 mm x 14 mm) package

PACKAGE OUTLINE
DS2196

100 1
ORDERING INFORMATION
PART DS2196L DS2196LN TEMP RANGE 0C to +70C -40C to +85C PIN-PACKAGE 100 LQFP 100 LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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TABLE OF CONTENTS
1 INTRODUCTION................................................................................................................................ 6 1.1 FEATURE HIGHLIGHTS.................................................................................................................. 6 1.2 TYPICAL APPLICATIONS............................................................................................................. 10 1.3 FUNCTIONAL DESCRIPTION....................................................................................................... 10 2 3 4 5 6 7 8 9 10 PIN DESCRIPTION .......................................................................................................................... 10 PIN FUNCTION DESCRIPTION.................................................................................................... 13 REGISTER MAP............................................................................................................................... 21 PARALLEL PORT............................................................................................................................ 27 CONTROL, ID, AND TEST REGISTERS ..................................................................................... 27 STATUS AND INFORMATION REGISTERS ............................................................................ 51 ERROR COUNT REGISTERS....................................................................................................... 64 SIGNALING OPERATION.............................................................................................................. 68 DS0 MONITORING FUNCTION .................................................................................................. 70
11 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK ..................................... 72 11.1 TRANSMIT SIDE CODE GENERATION .................................................................................. 72 11.2 RECEIVE SIDE CODE GENERATION...................................................................................... 73 12 13 14 15 16 17 18 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION ......................... 74 CLOCK BLOCKING REGISTERS.............................................................................................. 83 TRANSMIT TRANSPARENCY.................................................................................................... 85 BERT FUNCTION .......................................................................................................................... 86 ERROR INSERTION FUNCTION ............................................................................................... 96 HDLC CONTROLLER .................................................................................................................. 99 FDL/FS EXTRACTION AND INSERTION .............................................................................. 101
15.1 BERT REGISTER DESCRIPTION.............................................................................................. 88
17.1 HDLC FOR DS0S ......................................................................................................................... 100 18.1 HDLC AND BOC CONTROLLER FOR THE FDL.................................................................. 101 18.1.1 General Overview ................................................................................................................. 101 18.1.2 Status Register for the HDLC............................................................................................... 103 18.1.3 Basic Operation Details ........................................................................................................ 103 18.1.4 HDLC/BOC Register Description ........................................................................................ 105
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18.2 LEGACY FDL SUPPORT.......................................................................................................... 115 18.2.1 Overview............................................................................................................................... 115 18.2.2 Receive Section..................................................................................................................... 115 18.2.3 Transmit Section................................................................................................................... 116 18.3 D4/SLC-96 OPERATION .......................................................................................................... 117 19 LINE INTERFACE FUNCTION................................................................................................ 118 19.1 RECEIVE CLOCK AND DATA RECOVERY ......................................................................... 118 19.2 TRANSMIT WAVESHAPING AND LINE DRIVING............................................................. 119 19.3 JITTER ATTENUATOR .......................................................................................................... 120 20 JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................... 124 20.1 DESCRIPTION................................................................................................................................ 124 20.2 TAP CONTROLLER STATE MACHINE............................................................................................ 125 20.3 INSTRUCTION REGISTER AND INSTRUCTIONS................................................................................ 127 21 22 23 TIMING DIAGRAMS.................................................................................................................. 133 OPERATING PARAMETERS ................................................................................................... 141 100-PIN LQFP PACKAGE SPECIFICATIONS ...................................................................... 157
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LIST OF FIGURES
Figure 1-1: T1 Dual Framer LIU .............................................................................................................. 9 Figure 15-1: BERT Mux Diagram .......................................................................................................... 87 Figure 19-1: External Analog Connections .......................................................................................... 121 Figure 19-2: Jitter Tolerance ................................................................................................................. 122 Figure 19-3: Transmit Waveform Template ........................................................................................ 122 Figure 19-4: Jitter Attenuation.............................................................................................................. 123 Figure 20-1: Boundary Scan Architecture ........................................................................................... 124 Figure 20-2: TAP Controller State Machine........................................................................................ 127 Figure 21-1: Receive Side D4 Timing.................................................................................................... 133 Figure 21-2: Receive Side ESF Timing ................................................................................................. 134 Figure 21-3: Receive Side Boundary Timing ....................................................................................... 135 Figure 21-4: Transmit Side D4 Timing................................................................................................. 136 Figure 21-5: Transmit Side ESF Timing .............................................................................................. 137 Figure 21-6: Transmit Side Boundary Timing .................................................................................... 138 Figure 21-7: Transmit Data Flow.......................................................................................................... 139 Figure 21-8: Receive Data Flow............................................................................................................. 140 Figure 22-1: Intel Bus Read AC Timing (BTS=0 / MUX = 1) ............................................................ 146 Figure 22-2: Intel Bus Write Timing (BTS=0 / MUX=1) .................................................................... 147 Figure 22-3: Motorola Bus AC Timing (BTS = 1 / MUX = 1) ............................................................ 148 Figure 22-4: Intel Bus Read AC Timing (BTS=0 / MUX=0) .............................................................. 149 Figure 22-5: Intel Bus Write AC Timing (BTS=0 / MUX=0) ............................................................. 150 Figure 22-6: Motorola Bus Read AC Timing (BTS=1 / MUX=0) ...................................................... 151 Figure 22-7: Motorola Bus Write AC Timing (BTS=1 / MUX=0) ..................................................... 152 Figure 22-8: Receive Side AC Timing................................................................................................... 153 Figure 22-9: Receive Line Interface AC Timing.................................................................................. 154 Figure 22-10: Transmit Side AC Timing.............................................................................................. 155 Figure 22-11: Transmit Line Interface Side AC Timing..................................................................... 156
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LIST OF TABLES
Table 2-1: Pin Description Sorted by Pin Number................................................................................ 10 Table 4-1: Register Map Sorted by Address .......................................................................................... 21 Table 6-1: Output Pin Test Modes .......................................................................................................... 36 Table 6-2: Receive Data Source Mux Modes......................................................................................... 37 Table 6-3: TPOSB/TNEGB Data Source Select..................................................................................... 38 Table 7-1: Receive T1 Level Indication .................................................................................................. 57 Table 7-2: Alarm Criteria ........................................................................................................................ 59 Table 8-1: Line Code Violation Counting Arrangements..................................................................... 66 Table 8-2: Path Code Violation Counting Arrangements..................................................................... 67 Table 8-3: Multiframes Out Of Sync Counting Arrangements............................................................ 67 Table 12-1: Transmit Code Length......................................................................................................... 75 Table 12-2: Receive Code Length ........................................................................................................... 75 Table 15-1: Bert Pattern Select Options ................................................................................................. 89 Table 15-2: Repetitive Pattern Length Options ..................................................................................... 90 Table 15-3: Bert Rate Insertion Select.................................................................................................... 91 Table 16-1: Error Rate Options .............................................................................................................. 98 Table 16-2: Error Insertion examples..................................................................................................... 99 Table 17-1: Transmit HDLC Configuration .......................................................................................... 99 Table 18-1: HDLC/BOC Controller Register List............................................................................... 102 Table 19-1: Line Build Out Select In LICR ......................................................................................... 119 Table 19-2: Transformer Specifications ............................................................................................... 120 Table 20-1: Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture ............................ 128 Table 20-2: ID Code Structure .............................................................................................................. 128 Table 20-3: Device ID Codes.................................................................................................................. 129 Table 20-4: Boundary Scan Register Description................................................................................ 130
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1. INTRODUCTION
The DS2196 is a derivative of the DS21352 T1 SCT. The feature set has been optimized for transport applications commonly found in T1 transmission equipment. The DS2196 register map and register bit definitions are compatible with the DS21352/DS21552, allowing for easy migration to the DS2196. Interface designs requiring per-channel code insertion, elastic stores, and ANSI 1's density monitoring should use the DS21352 or DS21552.
1.1 Feature Highlights
Main features - Two full-featured independent framers - Short/long haul LIU - 100-pin LQFP small package - 3.3V operation with 5V tolerant I/O 8-bit parallel control port - Multiplexed or nonmultiplexed buses - Intel or Motorola formats - Polled or interrupt environments HDLC Support - Two independent HDLC controllers - 64-byte Rx and Tx buffers - Access FDL or single/multiple DS0 channels ANSI T1.403-1998 support - NPRMs - SPRMs - RAI-CI detection and generation - AIS-CI detection and generation Format Conversion - D4 to ESF framing - ESF to D4 framing LIU - Long and short-haul support - Receive sensitivity: 0dB to -36dB - 32-bit or 128-bit crystal-less jitter attenuator - DSX-1 and CSU line buildout options - Provisions for custom waveform generation DS1 Idle Code Generation - User-defined - Fixed 7F Hex - Digital milliwatt In-band repeating pattern generator and detector - Programmable pattern generator - Three programmable pattern detectors Patterns from 1 to 8 bits or 16 bits in length Programmable on-chip bit error-rate testing - Pseudorandom patterns including QRSS - User-defined repetitive patterns - Daly pattern - Error insertion - Bit and error counts Payload Error Insertion - Error insertion in the payload portion of the T1 frame in the transmit path - Errors can be inserted over the entire frame or selected channels - Insertion options include continuous and absolute number with selectable insertion rates Function Isolation - All key signals are routed to pins - LIU, Framer A, and Framer B can be disconnected from each other Supports both NRZ and bipolar interfaces F-bit corruption for line testing Programmable output clocks for Fractional T1 Fully independent transmit and receive functionality in each framer Large path and line error counters including BPV, CV, CRC6, and framing bit errors Ability to calculate and check CRC6 according to the Japanese standard Ability to generate Yellow Alarm according to the Japanese standard Per channel loopback RCL, RLOS, RRA, and RAIS alarms interrupt on change of state Hardware pins to indicate receive loss-ofsync and receive bipolar violations IEEE 1149.1 JTAG Boundary Scan -

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1.2 Typical Applications
1.544 MHz
OFFICE REPEATER/NIU
DS2196
1.544 MHz
T3/SONET/OPTICAL MULTIPLEXER APPLICATION
DS2196
T1 Interface A
Long / Short Haul Line Interface Unit (LIU)
Rx Framer A Rx HDLC Tx HDLC Tx Formatter A
Tx Formatter B Tx HDLC Rx HDLC Rx Framer B
Long / Short Haul Line Interface Unit (LIU)
T1 Interface B
T1 Network Interface
Long / Short Haul Line Interface Unit (LIU)
Rx Framer A Rx HDLC Tx HDLC Tx Formatter A
Tx Formatter B Tx HDLC Rx HDLC Rx Framer B
T3 / SONET / Optical Mux
Microcontroller
Microcontroller
NRZ Interface
1.544 MHz
CSU APPLICATION
DS2196
1.544 MHz
HDSL1/HDSL2 APPLICATION
DS2196
Telco T1 Interface
Long / Short Haul Line Interface Unit (LIU)
Rx Framer A Rx HDLC Tx HDLC Tx Formatter A
Tx Formatter B Tx HDLC Rx HDLC Rx Framer B
Short Haul Line Interface Unit (LIU)
CPE T1 Interface
T1 Interface (Remote or CO Located)
Long / Short Haul Line Interface Unit (LIU)
Rx Framer A Rx HDLC
Tx Formatter B Tx HDLC Rx HDLC Rx Framer B
Tx
Tx Formatter A
HDSL1 / HDSL2 Modem
One or Two Sets of Twisted Pair
Microcontroller
Microcontroller
NRZ Interface
1.3 Functional Description
The analog AMI/B8ZS waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of the DS2196. The device recovers clock and data from the analog signal and passes it through the optional jitter attenuator to the receive side framer where the digital serial stream is analyzed to locate the framing/multiframe pattern. The DS2196 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of 0 dB to -36 dB, which allows the device to operate on cables up to 6000 feet in length. The receive side framer locates D4 (SLC-96) or ESF multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, blue (AIS) and yellow alarms. The transmit side of the DS2196 is totally independent from the receive side in both the clock requirements and characteristics. The transmit formatter will provide the necessary frame/multiframe data overhead for T1 transmission. Once the data stream has been prepared for transmission, it is sent via the optional jitter attenuator to the wave shaping and line driver functions. The DS2196 will drive the T1 line from the TTIP and TRING pins via a coupling transformer. The line driver can handle both long haul (CSU) and short haul (DSX-1) lines.
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Reader's Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125ms frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of 8 bits that are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. The following abbreviations are used throughout this data sheet:
BERT D4 SLC-96 ESF B8ZS CRC Ft Fs FPS MF BOC HDLC FDL Bit Error Rate Tester Superframe (12 frames per multiframe) Multiframe Structure Subscriber Loop Carrier-96 Channels Extended Superframe (24 frames per multiframe) Multiframe Structure Bipolar with Eight Zero Substitution Cyclical Redundancy Check Terminal Framing Pattern in D4 Signaling Framing Pattern in D4 Framing Pattern in ESF Multiframe Bit-Oriented Code High-Level Data-Link Control Facility Data Link
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Figure 1-1. T1 Dual Framer LIU
TNEGOB/ TFSYNCB TPOSOB/ TNRZB DVDD(3) TCLKOB DVSS(3) RVSS(2) RNEGIB RCLKIB RPOSIB Back End Loopback User Output Port (4 pins) From BERT Mux POWER
RVDD
TVDD
UOP0 UOP1 UOP2 UOP3
TVSS
FLB B Mux
Clock Gen
TCHBLKB/ TLINKB TCHCLKB TLCLKB BERT sync clock data clock data 4 4 5 2 from Receive Framer B (only in FT1 application) RMSYNCB FLB B
Framer Loopback B AIS & AIS-CI Generation Transmit Side Formatter B B8ZS Encode Corrupt F-Bit / Payload Insert Data From BERT Yellow Alarm Generation BOM Generation CRC Generation F-Bit Insertion Loop Code Generation Clear Channel Signaling Insertion clock msync fsync
data
RCHBLKB/ RLINKB B8ZS Decoder BPV Counter Synchronizer Alarm Detection Clock Gen RCHCLKB/ RLCLKB RLOSB / LOTCB FDL Extraction BOM Detection 64-Byte Buffer RBPVB
BERT Mux
4
64-Byte Buffer
FDL Insertion
Receive Side Framer B
Loop Code Detector CRC/Frame Error Count Signaling Extraction Channel Marking
RXA
RXB
RCLKB
TXA
To BERT Mux
Per-Channel Loopback
RSERB RCLKB RFSYNCB
1.544MHz
msync
From MCLK
LOTC Mux
RMSYNCB data TSYNC Control fsync msync clock Payload Loopback B TSYNC Control TSYNCA TSERA TCLKA
SSER SYSCLK SFSYNC DS2175 (optional)
TSERB TCLKB TSYNCB
mux (controlled via CCR4B.2)
fsync
msync
clock
BOM Detection
FDL Extraction
RSERA To BERT Mux
64-Byte Buffer
Channel Marking Signaling Extraction Receive Side Framer A CRC/Frame Error Count Loop Code Detector Alarm Detection Synchronizer BPV Counter B8ZS Decoder Framer Loopback A Transmit Side Formatter A
Clear Channel Loop Code Generation F-Bit Insertion CRC Generation Yellow Alarm Generation Insert Data From BERT Corrupt F-Bit / Payload B8ZS Encode AIS & AIS-CI Generation
BOM Generation
64-Byte Buffer
FDL Insertion
RMSYNC RCLK RSER
clock
data
RFSYNCA RCLKA
fsync
msync
Per-Channel Loopback Signaling Insertion
RBPVA RLOSA / LOTCA RCHCLKA/ RLCLKA RCHBLKA/ RLINKA
Clock Gen
To / From BERT Mux
4
From MCLK
RMSYNCA
data
Payload Loopback A
LOTC Mux
mux (controlled via CCR4B.2)
Clock Gen
TCHBLKA/ TLINKA TCHCLKA/ TLCLKA
mux (controlled via CCR4A.2)
RPOSIA RCLKIA RNEGIA RNEGLO RCLKLO RPOSLO
Remote Loopback
TPOSOA/ TNRZA TCLKOA TNEGOA/ TFSYNCA mux (controlled via CCR4A.2) TNEGLI TCLKLI TPOSLI D0 to D7 / AD0 to AD7 INT* MUX Parallel Control Port (routed to all blocks)
Data Source MUX Control (controlled via CCR1A.2/3/4)
WPS
VCO / PLL
8
Jitter Attenuation (can be placed in either transmit or receive path)
Local Loopback WORKING PROTECT LIU AIS
A0 to A6 7 ALE(AS) / A7 RD*(DS*) WR*(R/W*) BTS CS* JTCLK JTDI JTRST* JTMS JTDO
LIU AIS Generation RCL 1.544 MHz Clock / Data Recovery Wave Shaping Peak Detect TNEG or TFSYNC
TPOS or TNRZ
CSU Filters
LNRZ AIS Generation
Filter
LFSYNC
RRING
WCLK
WNRZ
RTIP
TRING
TTIP
TCLK
Line Drivers
MCLK
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LNRZ
LCLK
PCLK
PNRZ
JTAG
DS2196
2. PIN DESCRIPTION Table 2-1. Pin Description Sorted by Pin Number
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 SYMBOL PCLK PNRZ WCLK WNRZ JTMS JTCLK JTRST* JTDI JTDO RCL LNRZ LCLK LFSYNC RPOSLO RNEGLO RCLKLO BTS RTIP RRING RVDD RVSS INT* RVSS MCLK UOP3 UOP2 UOP1 UOP0 TTIP TVSS TVDD TRING TPOSLI TNEGLI TCLKLI TCHBLKB/ TLINKB TCHCLKB/ TLCLKB TSYNCB TCLKB TSERB TPOSOB/ TNRZB TNEGOB / TFSYNCB TYPE I I I I I I I I O O O O O O O O I I I - - O - I O O O O O - - O I I I I/O O I/O I I O O FUNCTION Protect Clock Input. Protect NRZ Data Input. Working Clock Input. Working NRZ Data Input. IEEE 1149.1 Test Mode Select. IEEE 1149.1 Test Clock Signal. IEEE 1149.1 Test Reset. IEEE 1149.1 Test Data Input. IEEE 1149.1 Test Data Output. Receive LIU Carrier Loss. LIU NRZ & Positive Data Output. LIU Clock Output. LIU Frame Sync Pulse & Negative Data Output. Receive Positive & NRZ Data Output from the LIU. Receive Negative & NRZ Data Output from the LIU. Receive Clock Output from the LIU. Bus Type Select. 0 = Intel / 1 = Motorola. Receive Analog Tip Input. Receive Analog Ring Input. Receive Analog Positive Supply. 3.3V (5%). Receive Analog Signal Ground. Interrupt. Open Drain. Active Low Signal. Receive Analog Signal Ground. Master Clock Input. 1.544 MHz (50 ppm). User Defined Output Port Bit 3. User Defined Output Port Bit 2. User Defined Output Port Bit 1. User Defined Output Port Bit 0. Transmit Analog Tip Output. Transmit Analog Signal Ground. Transmit Analog Positive Supply. 3.3V (5%). Transmit Analog Ring Output. Transmit Positive & NRZ Data for the LIU. Transmit Negative & NRZ Data for the LIU. Transmit Clock Input for the LIU. Transmit Channel Blocking Clock Output from Formatter B / Transmit FDL Link Data Input for Formatter B. Transmit DS0 Channel Clock Output from Formatter B / Transmit FDL Link Clock Output from Formatter B. Transmit Frame & Multiframe Pulse for/from Formatter B. Transmit Clock Input for Formatter B. Transmit Serial Data Input for Formatter B. Transmit Positive Data Output from Formatter B / Transmit NRZ Data Output from Formatter B. Transmit Negative Data Output from Formatter B / Transmit Frame Sync Pulse Output from Formatter B.
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PIN 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
SYMBOL TCLKOB DVSS DVDD TCLKOA TNEGOA / TFSYNCA TPOSOA / TNRZA TSERA TCLKA TSYNCA TCHCLKA / TLCLKA TCHBLKA / TLINKA MUX D0 / AD0 D1 / AD1 D2 / AD2 D3 / AD3 D4 / AD4 D5 / AD5 D6 / AD6 D7 / AD7 DVSS DVDD A0 A1 A2 A3 A4 A5 A6 A7 / ALE(AS) RD*(DS*) CS* WR*(R/W*) RCHBLKA / RLINKA RCHCLKA / RLCLKA RCLKIA RPOSIA RNEGIA RCLKA RSERA RMSYNCA RFSYNCA RLOSA/ LOTCA
TYPE O - - O O O I I I/O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O - - I I I I I I I I I I I O O I I I O O O O O
FUNCTION Transmit Clock Output from Formatter B. Digital Signal Ground. Digital Positive Supply. 3.3V (5%). Transmit Clock Output from Formatter A. Transmit Negative Data Output from Formatter A / Transmit Frame Sync Pulse Output from Formatter A. Transmit Positive Data Output / Transmit NRZ Data Output from Formatter A. Transmit Serial Data Input for Formatter A. Transmit Clock Input for Formatter A. Transmit Frame & Multiframe Pulse for/from Formatter A. Transmit DS0 Channel Clock Output from Formatter A / Transmit FDL Link Clock Output from Formatter A. Transmit Channel Blocking Clock Output from Formatter A / Transmit FDL Link Data Input for Formatter A. Bus Operation. 0 = Non-Mux Bus / 1 = Mux Bus Operation. Data Bus Bit 0 / Address/Data Bus Bit 0. LSB. Data Bus Bit 1 / Address/Data Bus Bit 1. Data Bus Bit 2 / Address/Data Bus Bit 2. Data Bus Bit 3 / Address/Data Bus Bit 3. Data Bus Bit 4 / Address/Data Bus Bit 4. Data Bus Bit 5 / Address/Data Bus Bit 5. Data Bus Bit 6 / Address/Data Bus Bit 6. Data Bus Bit 7 / Address/Data Bus Bit 7. MSB. I/O Digital Signal Ground. I/O Digital Positive Supply. 3.3V (5%). Address Bus Bit 0. LSB. Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Bus Bit 7 / Address Latch Enable (Address Strobe). MSB. Read Input (Data Strobe). Chip Select. Active Low Signal. Write Input (Read/Write). Receive Channel Blocking Clock Output from Framer A / Receive FDL Link Data Output from Framer A. Receive DS0 Channel Clock Output from Framer A / Receive FDL Link Clock Output from Framer A. Receive Clock Input for Framer A. Receive Positive & NRZ Data Input for Framer A. Receive Negative & NRZ Data Input for Framer A. Receive Clock Output from Framer A. Receive Serial Data Output from Framer A. Receive Multiframe Pulse from Framer A. Receive Frame Pulse from Framer A. Receive Loss Of Synchronization from Framer A / Loss of Transmit Clock Framer A.
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PIN 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
SYMBOL RBPVA DVSS DVDD RBPVB RLOSB/ LOTCB RFSYNCB RMSYNCB RSERB RCLKB RNEGIB RPOSIB RCLKIB RCHCLKB / RLCLKB RCHBLKB / RLINKB WPS
TYPE O - - O O O O O O I I I O O I
FUNCTION Receive bipolar Violation (BPV) from Framer A. Digital Signal Ground. Digital Positive Supply. 3.3V (5%). Receive bipolar Violation (BPV) from Framer B. Receive Loss Of Synchronization from Framer B / Loss of Transmit Clock Framer B. Receive Frame Pulse from Framer B. Receive Multiframe Pulse from Framer B. Receive Serial Data Output from Framer B. Receive Clock Output from Framer B. Receive Negative & NRZ Data Input for Framer B. Receive Positive & NRZ Data Input for Framer B. Receive Clock Input for Framer B. Receive DS0 Channel Clock Output from Framer B / Receive FDL Link Clock Output from Framer B. Receive Channel Blocking Clock Output from Framer B / Receive FDL Link Data Output from Framer B. Working/Protect Select.
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3. PIN FUNCTION DESCRIPTION Transmit Side Pins
Signal Name: TCLKA/B Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz primary clock is applied here. Used to clock data through the transmit side formatters. TCLKA/B can be internally connected to RCLKB/A via the CCR4B.2 control bit. Signal Name: TSERA/B Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLKA or TCLKB. TSERA/B can be internally connected to RSERB/A via the CCR4B.2 control bit. Signal Name: TSYNCA/B Signal Description: Transmit Sync Signal Type: Input / Output When programmed as an input, a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR2A.2 and TCR2B.2, the DS2196 can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2A.4 and TCR2B.4 to output double-wide pulses at signaling frames. See Section 21 for details. TSYNCA/B can be internally connected to RMSYNCB/A via the CCR4B.2 control bit. Signal Name: TCHCLKA/B / TLCLKA/B Signal Description: Transmit Channel Clock / Transmit Link Clock Signal Type: Output A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If TCHCLK is selected, a 192-kHz clock, which pulses high during the LSB of each channel, will be output. If TLCLK is selected, either a 4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK data is output. This output signal is always synchronous with TCLKA or TCLKB. See Section 21 for details. Signal Name: TCHBLKA/B / TLINKA/B Signal Description: Transmit Channel Block / Transmit Link Data Signal Type: Input / Output A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If TCHBLK is selected, a user programmable output that can be forced high or low during any of the 24 T1 channels is output. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional T1, 384 kbps service, 768 kbps, or ISDN-PRI. Also useful for locating individual channels in drop- and-insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 21 for details. If TLINK is selected, this pin will be sampled on the falling edge of TCLKA or TCLKB for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4) or the Z-bit position (ZBTSI). See Section 21 for details. This signal is always synchronous with TCLKA or TCLKB. Signal Name: TPOSOA/B / TNRZA/B Signal Description: Transmit Positive & NRZ Data Output Signal Type: Output Updated on the rising edge of TCLKOA and rising or falling edge of TCLKOB with either bipolar data or NRZ data out of the transmit side formatter. This pin can be programmed to source NRZ data via the Output Data Format (CCR1A.6 and CCR1B.6) control bits.
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Signal Name: TNEGA/B / TFSYNCA/B Signal Description: Transmit Negative Data & Frame Sync Pulse Output Signal Type: Output Updated on the rising edge of TCLKA or TCLKB with either bipolar data or a frame sync pulse out of the transmit side formatter. This pin can be programmed to source the frame sync pulse via the Output Data Format (CCR1A.6 and CCR1B.6) control bits.
Receive Framer Pins
Signal Name: RCHCLKA/B / RLCLKA/B Signal Description: Receive Channel Clock / Receive Link Clock Signal Type: Output A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If RCHCLK is selected, a 192-kHz clock, which pulses high during the LSB of each channel, will be output. If RLCLK is selected, either a 4 kHz or 2 kHz (ZBTSI) clock for the RLINK data is output. This output signal is always synchronous with RCLKA or RCLKB. Signal Name: RCHBLKA/B / RLINKA/B Signal Description: Receive Channel Block / Receive Link Data Signal Type: Output A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If RCHBLK is selected, a user programmable output that can be forced high or low during any of the 24 T1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional T1, 384 kbps service, 768 kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 21 for details. If RLINK is selected, then either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLKA before the start of a frame are output. See Section 21 for details. This signal is always synchronous with RCLKA or RCLKB. Signal Name: RSERA/B Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLKA or RCLKB. Signal Name: RFSYNCA/B Signal Description: Receive Frame Sync Signal Type: Output An extracted pulse, one RCLKA or RCLKB wide, is output at this pin which identifies frame boundaries. Via RCR2A.5 and RCR2B.5, RFSYNC can also be set to output double-wide pulses on signaling frames. This signal is always synchronous with RCLKA or RCLKB.
Signal Name:
RMSYNCA/B Signal Description: Receive Multiframe Sync Signal Type: Output An extracted pulse, one RCLKA or RCLKB wide, is output at this pin which identifies multiframe boundaries. This signal is always synchronous with RCLKA or RCLKB.
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Signal Name: RLOSA/B / LOTCA/B Signal Description: Receive Loss of Sync / Loss of Transmit Clock Signal Type: Output A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5 msec. Signal Name: RBPVA/B Signal Description: Receive BPV Signal Type: Output This pin will toggle high for one RCLKA or RCLKB clock cycle for each bipolar Violation (BPV) detected by the framer. Signal Name: RPOSIA/B Signal Description: Receive Positive Data Input Signal Type: Input Sampled on the falling edge of RCLKIA and either rising or falling edge of RCLKIB for data to be clocked through the receive side framer. RPOSIA/B and RNEGIA/B can be tied together for a NRZ interface. RPOSIA be internally connected to RPOSLO via the CCR4A.2 control bit. Signal Name: RNEGIA/B Signal Description: Receive Negative Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSIA/B and RNEGIA/B can be tied together for a NRZ interface. RNEGIA be internally connected to RNEGLO via the CCR4A.2 control bit. Signal Name: RCLKIA/B Signal Description: Receive Clock Input Signal Type: Input Signal used to clock data through the receive side framers. RCLKIA can be internally connected to RCLKLO via the CCR4A.2 control bit.
User Port Pins
Signal Name: UOP0/1/2/3 Signal Description: User Output Port Signal Type: Output These output port pins can be set low or high via the CCR7B.0 to CCR7B.3 control bits. The pins are forced low on power-up.
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Parallel Control Port Pins
Signal Name: INT* Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and change of states as defined in the Status Registers. Active low, open drain output. Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select non-multiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: D0 to D7 / AD0 to AD7 Signal Description: Data Bus or Address/Data Bus Signal Type: Input / Output In non-multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as a 8-bit multiplexed address / data bus. Signal Name: A0 to A6 Signal Description: Address Bus Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low. Signal Name: BTS Signal Description: Bus Type Select Signal Type: Input Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*), ALE (AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis (). Signal Name: RD* (DS*) Signal Description: Read Input (Data Strobe) Signal Type: Input RD* is an active low signal. DS* polarity is determined by the MUX pin setting. Refer to section 21 for details. Signal Name: CS* Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS* is an active low signal. Signal Name: ALE(AS) / A7 Signal Description: A7 or Address Latch Enable (Address Strobe) Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus on a positive-going edge. Signal Name: WR*( R/W*) Signal Description: Write Input (Read/Write) Signal Type: Input WR* is an active low signal.
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Signal Name: JTCLK Signal Description: JTAG IEEE 1149.1 Test Serial Clock Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, this pin should be pulled high. Signal Name: JTDI Signal Description: JTAG IEEE 1149.1 Test Serial Data Input Signal Type: Input Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this pin should be pulled high. This pin has an internal pull-up. Signal Name: JTDO Signal Description: JTAG IEEE 1149.1 Test Serial Data Output Signal Type: Output Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this pin should be left open circuited. Signal Name: JTRST* Signal Description: JTAG IEEE 1149.1 Test Reset Signal Type: Input This signal is used to synchronously reset the test access port controller. At power up, JTRST must be set low and then high. This action will set the device into the boundary scan bypass mode allowing normal device operation. If boundary scan is not used, this pin should be held low. This pin has an internal pull-up. Signal Name: JTMS Signal Description: JTAG IEEE 1149.1 Test Mode Select Signal Type: Input This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE 1149.1 states. If not used, this pin should be pulled high. This signal has an internal pull-up.
Line Interface Pins
Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 1.544 MHz (50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. This clock is also used to source AIS within the LIU. Signal Name: RTIP & RRING Signal Description: Receive Tip and Ring Signal Type: Input Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 19 for details. Signal Name: TTIP & TRING Signal Description: Transmit Tip and Ring Signal Type: Output Analog line driver outputs. These pins connect via a 1:2 step-up transformer to the T1 line. See Section 19 for details. Signal Name: Signal Description: LFSYNC LIU Frame Sync
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Signal Type: Output This digital output will provide either a frame synchronization pulse or the negative half of a bipolar data stream. The signal is based on what is provided at the TNEGLI input. Signal Name: LNRZ Signal Description: LIU NRZ Data Signal Type: Output This digital output will provide either a NRZ data stream or the positive half of a bipolar data stream. The signal is based on what is provided at the TPOSLI input. Signal Name: LCLK Signal Description: LIU Clock Signal Type: Output This digital output provides the 1.544 MHz transmit LIU clock. The signal is based on what is provided at the TCLKLI input. Signal Name: TNEGLI Signal Description: Transmit Negative Data for the LIU Signal Type: Input This digital input is used to pass either the negative half of a bipolar data stream or a frame synchronization pulse via the jitter attenuator block to the transmit line driver block and the LFSYNC output pin. Data input to this pin is sampled on the falling edge of TCLKLI. TNEGLI can be internally connected to TNEGOA/TFSYNCA via the CCR4A.2 control bit. Signal Name: TPOSLI Signal Description: Transmit Positive Data for the LIU Signal Type: Input This digital input is used to pass either the positive half of a bipolar data stream or a NRZ data stream via the jitter attenuator block to the transmit line driver block and the LNRZ output pin. Data input to this pin is sampled on the falling edge of TCLKLI. TPOSLI can be internally connected to TPOSOA/TNRZA via the CCR4A.2 control bit. Signal Name: TCLKLI Signal Description: Transmit Clock for the LIU Signal Type: Input This digital input is used to pass a 1.544 MHz clock via the jitter attenuator block to the transmit line driver block and the LCLK output pin. TCLKLI can be internally connected to TCLKOA via the CCR4A.2 control bit. Signal Name: WNRZ Signal Description: Working NRZ Data Signal Type: Input This digital input is used to pass a NRZ data stream via the Data Source Selection MUX and the jitter attenuator block to the RPOSLO and RNEGLO output pins. Data input to this pin is sampled on the falling or rising edge of WCLK. Signal Name: WCLK Signal Description: Working Clock Signal Type: Input This digital input is used to pass a 1.544 MHz clock via the Data Source Selection MUX and the jitter attenuator block to the RCLKLO output pin.
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Signal Name: PNRZ Signal Description: Protect NRZ Data Signal Type: Input This digital input is used to pass a NRZ data stream via the Data Source Selection MUX and the jitter attenuator block to the RPOSLO and RNEGLO output pins. Data input to this pin is sampled on the falling or rising edge of PCLK. Signal Name: PCLK Signal Description: Protect Clock Signal Type: Input This digital input is used to pass a 1.544 MHz clock via the Data Source Selection MUX and the jitter attenuator block to the RCLKLO output pin. Signal Name: RCL Signal Description: Receive Carrier Loss Signal Type: Output Set high when the line interface (LIU) detects a carrier loss. Signal Name: RPOSLO Signal Description: Receive Positive Data Output from the LIU Signal Type: Output Updated on the rising edge of RCLKLO with either bipolar data out of the LIU or NRZ data from the WNRZ or PNRZ inputs. Signal Name: RNEGLO Signal Description: Receive Negative Data Output from the LIU Signal Type: Output Updated on the rising edge of RCLKLO with either bipolar data out of the LIU or NRZ data from the WNRZ or PNRZ inputs. Signal Name: RCLKO Signal Description: Receive Clock Output Signal Type: Output Either a buffered recovered clock from the T1 line or the clock provided at the WCLK or PCLK inputs. Signal Name: WPS Signal Description: Working or Protect Select Signal Type: Input This digital input can be used to select between the WNRZ/WCLK (working) or PNRZ/PCLK (protect) data inputs. For this pin to be active the Data Source MUX must be properly configured via the CCR1A.2, CCR1A.3, and CCR1A.4 control bits.
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Supply Pins
Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3 volts 5%. Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3 volts 5%. Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 3.3 volts 5%. Should be tied to the RVDD and DVDD pins. Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0.0 volts. Should be tied to the DVSS and TVSS pins. Signal Name: TVSS Signal Description: Transmit Analog Ground Signal Type: Supply 0.0 volts. Should be tied to the DVSS and TVSS pins.
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4. REGISTER MAP Table 4-1. Register Map Sorted By Address
ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B R/W R/W R/W R/W R/W R/W R R/W R/W W R/W R/W -- -- -- R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/w R/W R R/W R/W R/W R R R R R R R/W R/W R/W REGISTER NAME HDLC Control for Framer A HDLC Status from Framer A HDLC Interrupt Mask for Framer A Receive HDLC Information for Framer A Receive Bit Oriented Code for Framer A Receive HDLC FIFO from Framer A Transmit HDLC Information for Formatter A Transmit Bit Oriented Code for Formatter A Transmit HDLC FIFO for Formatter A Test 2 for Framer A (Set to 00h on power-up) Common Control 7 for Framer A Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Interrupt Status Register Device ID Receive Information 3 from Framer A Common Control 4 for Framer A In-Band Code Control for Framer A Transmit Code Definition 1 for Framer A Receive Up Code Definition 1 for Framer A Receive Down Code Definition 1 for Framer A Transmit Code Definition 2 for Framer A Receive Up Code Definition 2 for Framer A Receive Down Code Definition 2 for Framer A Common Control 5 for Framer A Transmit DS0 Monitor for Framer A Receive Spare Code Definition 1 for Framer A Receive Spare Code Definition 2 for Framer A Receive Spare Code Control for Framer A Common Control 6 for Framer A Receive DS0 Monitor from Framer A Status 1 from Framer A Status 2 from Framer A Receive Information 1 from Framer A Line Code Violation Count 1 from Framer A Line Code Violation Count 2 from Framer A Path Code Violation Count 1 from Framer A Multiframe Out of Sync Count 1 from Framer A Path Code violation Count 2 from Framer A Multiframe Out of Sync Count 2 from Framer A Receive FDL Register from Framer A Receive FDL Match 1 for Framer A Receive FDL Match 2 for Framer A Receive Control 1 for Framer A
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REGISTER ABBREVIATION HCRA HSRA HIMRA RHIRA RBOCA RHFA THIRA TBOCA THFA -- CCR7A -- -- -- ISR IDR RIR3A CCR4A IBCCA TCD1A RUPCD1A RDNCD1A TCD2A RUPCD2A RDNCD2A CCR5A TDS0MA RSCD1A RSCD2A RSCCA CCR6A RDS0MA SR1A SR2A RIR1A LCVCR1A LCVCR2A PCVCR1A MOSCR1A PCVCR2A MOSCR2A RFDLA RMTCH1A RMTCH2A RCR1A
DS2196
ADDRESS 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R R R R R R R/W -- -- -- -- -- -- -- -- -- -- -- --
REGISTER NAME Receive Control 2 for Framer A Receive Mark 1 for Framer A Receive Mark 2 for Framer A Receive Mark 3 for Framer A Common Control 3 for Framer A Receive Information 2 for Framer A Transmit Channel Blocking 1 for Formatter A Transmit Channel blocking 2 for Formatter A Transmit Channel Blocking 3 for Formatter A Transmit Control 1 for Formatter A Transmit Control 2 for Formatter A Common Control 1 for Framer A Common Control 2 for Framer A Transmit Transparency 1 for Formatter A Transmit Transparency 2 for Formatter A Transmit Transparency 3 for Formatter A Transmit Idle 1 for Formatter A Transmit Idle 2 for Formatter A Transmit Idle 3 for Formatter A Transmit Idle Definition for Formatter A BERT Control Register 0 BERT Control Register 1 BERT Control Register 2 BERT Information Register BERT Alternating Word Count BERT Repetitive Pattern Set Register 0 BERT Repetitive Pattern Set Register 1 BERT Repetitive Pattern Set Register 2 BERT Repetitive Pattern Set Register 3 BERT Bit Count Register 0 BERT Bit Count Register 1 BERT Bit Count Register 2 BERT Bit Count Register 3 BERT Bit Error Count Register 0 BERT Bit Error Count Register 1 BERT Bit Error Count Register 2 BERT Interface Control Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up)
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REGISTER ABBREVIATION RCR2A RMR1A RMR2A RMR3A CCR3A RIR2A TCBR1A TCBR2A TCBR3A TCR1A TCR2A CCR1A CCR2A TTR1A TTR2A TTR3A TIR1A TIR2A TIR3A TIDRA BC0 BC1 BC2 BIR BAWC BRP0 BRP1 BRP2 BRP3 BBC0 BBC1 BBC2 BBC3 BEC0 BEC1 BEC2 BIC -- -- -- -- -- -- -- -- -- -- -- --
DS2196
ADDRESS 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D
R/W -- R/W R/W R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W R R R/W W W R R -- -- -- --
REGISTER NAME Reserved (Set to 00h on power-up) LIU Test Register 1 (Set to 00h on power-up) LIU Test Register 2 (Set to 00h on power-up) Receive Signaling 1 from Framer A Receive Signaling 2 from Framer A Receive Signaling 3 from Framer A Receive Signaling 4 from Framer A Receive Signaling 5 from Framer A Receive Signaling 6 from Framer A Receive Signaling 7 from Framer A Receive Signaling 8 from Framer A Receive Signaling 9 from Framer A Receive Signaling 10 from Framer A Receive Signaling 11 from Framer A Receive Signaling 12A from Framer A Receive Channel Blocking 1 for Framer A Receive Channel Blocking 2 for Framer A Receive Channel Blocking 3 for Framer A Interrupt Mask 2 for Framer A. Transmit Signaling 1 for Formatter A Transmit Signaling 2 for Formatter A Transmit Signaling 3 for Formatter A Transmit Signaling 4 for Formatter A Transmit Signaling 5 for Formatter A Transmit Signaling 6 for Formatter A Transmit Signaling 7 for Formatter A Transmit Signaling 8 for Formatter A Transmit Signaling 9 for Formatter A Transmit Signaling 10 for Formatter A Transmit Signaling 11 for Formatter A Transmit Signaling 12 for Formatter A Line Interface Control Test 1 for Framer A (Set to 00h on power-up) Transmit FDL Register for Formatter A Interrupt Mask Register 1 for Framer A Error Rate Control for Framer A Number of Errors 1 for Framer A Number of Errors 2 for Framer A Number of Errors Left 1 for Framer A Number of Errors Left 2 for Framer A Error Rate Control for Framer B Number of Errors 1 for Framer B Number of Errors 2 for Framer B Number of Errors Left 1 for Framer B Number of Errors Left 2 for Framer B Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up)
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REGISTER ABBREVIATION -- -- -- RS1A RS2A RS3A RS4A RS5A RS6A RS7A RS8A RS9A RS10A RS11A RS12A RCBR1A RCBR2A RCBR3A IMR2A TS1A TS2A TS3A TS4A TS5A TS6A TS7A TS8A TS9A TS10A TS11A TS12A LICR -- TFDLA IMR1A ERCA NOE1A NOE2A NOEL1A NOEL2A ERCB NOE1B NOE2B NOEL1B NOEL2B -- -- -- --
DS2196
ADDRESS 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8
R/W -- -- R/W R/W R/W R/W R/W R/W R/W R/W -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R R/W R/W W R/W R/W -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Receive HDLC DS0 Control Register 1 for Framer A Receive HDLC DS0 Control Register 2 for Framer A Transmit HDLC DS0 Control Register 1 for Formatter A Transmit HDLC DS0 Control Register 2 for Formatter A Receive HDLC DS0 Control Register 1 for Framer B Receive HDLC DS0 Control Register 2 for Framer B Transmit HDLC DS0 Control Register 1 for Formatter B Transmit HDLC DS0 Control Register 2 for Formatter B Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) HDLC Control for Framer B HDLC Status from Framer B HDLC Interrupt Mask for Framer B Receive HDLC Information for Framer B Receive Bit Oriented Code for Framer B Receive HDLC FIFO from Framer B Transmit HDLC Information for Formatter B Transmit Bit Oriented Code for Formatter B Transmit HDLC FIFO for Formatter B Test 2 for Framer B (Set to 00h on power-up) Common Control 7 for Framer B Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Reserved (Set to 00h on power-up) Receive Information 3 from Framer B Common Control 4 for Framer B In-Band Code Control for Framer B Transmit Code Definition 1 for Framer B Receive Up Code Definition 1 for Framer B Receive Down Code Definition 1 for Framer B Transmit Code Definition 2 for Framer B Receive Up Code Definition 2 for Framer B Receive Down Code Definition 2 for Framer B
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REGISTER ABBREVIATION -- -- RDC1A RDC2A TDC1A TDC2A RDC1B RDC2B TDC1B TDC2B -- -- -- -- -- -- -- HCRB HSRB HIMRB RHIRB RBOCB RHFB THIRB TBOCB THFB -- CCR7B -- -- -- -- -- RIR3B CCR4B IBCCB TCD1B RUPCD1B RDNCD1B TCD2B RUPCD2B RDNCD2B
DS2196
ADDRESS B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8
R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R
REGISTER NAME Common Control 5 for Framer B Transmit DS0 Monitor from Formatter B Receive Spare Code Definition 1 for Framer B Receive Spare Code Definition 2 for Framer B Receive Spare Code Control for Framer B Common Control 6 for Framer B Receive DS0 Monitor from Framer B Status 1 from Framer B Status 2 from Framer B Receive Information 1 from Framer B Line Code Violation Count 1 from Framer B Line Code Violation Count 2 from Framer B Path Code Violation Count 1 from Framer B Multiframe Out of Sync Count 1 from Framer B Path Code violation Count 2 from Framer B Multiframe Out of Sync Count 2 from Framer B Receive FDL Register from Framer B Receive FDL Match 1 for Framer B Receive FDL Match 2 for Framer B Receive Control 1 for Framer B Receive Control 2 for Framer B Receive Mark 1 for Framer B Receive Mark 2 for Framer B Receive Mark 3 for Framer B Common Control 3 for Framer B Receive Information 2 from Framer B Transmit Channel Blocking 1 for Formatter B Transmit Channel blocking 2 for Formatter B Transmit Channel Blocking 3 for Formatter B Transmit Control 1 for Framer B Transmit Control 2 for Framer B Common Control 1 for Framer B Common Control 2 for Framer B Transmit Transparency 1 for Formatter B Transmit Transparency 2 for Formatter B Transmit Transparency 3 for Formatter B Transmit Idle 1 for Formatter B Transmit Idle 2 for Formatter B Transmit Idle 3 for Formatter B Transmit Idle Definition for Formatter B Receive Signaling 1 from Framer B Receive Signaling 2 from Framer B Receive Signaling 3 from Framer B Receive Signaling 4 from Framer B Receive Signaling 5 from Framer B Receive Signaling 6 from Framer B Receive Signaling 7 from Framer B Receive Signaling 8 from Framer B Receive Signaling 9 from Framer B
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REGISTER ABBREVIATION CCR5B TDS0MB RSCD1B RSCD2B RSCCB CCR6B RDS0MB SR1B SR2B RIR1B LCVCR1B LCVCR2B PCVCR1B MOSCR1B PCVCR2B MOSCR2B RFDLB RMTCH1B RMTCH2B RCR1B RCR2B RMR1B RMR2B RMR3B CCR3B RIR2B TCBR1B TCBR2B TCBR3B TCR1B TCR2B CCR1B CCR2B TTR1B TTR2B TTR3B TIR1B TIR2B TIR3B TIDRB RS1B RS2B RS3B RS4B RS5B RS6B RS7B RS8B RS9B
DS2196
ADDRESS E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W
REGISTER NAME Receive Signaling 10 from Framer B Receive Signaling 11 from Framer B Receive Signaling 12 from Framer B Receive Channel Blocking 1 for Framer B Receive Channel Blocking 2 for Framer B Receive Channel Blocking 3 for Framer B Interrupt Mask 2 for Framer B Transmit Signaling 1 for Formatter B Transmit Signaling 2 for Formatter B Transmit Signaling 3 for Formatter B Transmit Signaling 4 for Formatter B Transmit Signaling 5 for Formatter B Transmit Signaling 6 for Formatter B Transmit Signaling 7 for Formatter B Transmit Signaling 8 for Formatter B Transmit Signaling 9 for Formatter B Transmit Signaling 10 for Formatter B Transmit Signaling 11 for Formatter B Transmit Signaling 12 for Formatter B Reserved (Set to 00h on power-up) Test 1 for Framer B (Set to 00h on power-up) Transmit FDL Register for Framer B Interrupt Mask Register 1 for Framer B
REGISTER ABBREVIATION RS10B RS11B RS12B RCBR1B RCBR2B RCBR3B IMR2B TS1B TS2B TS3B TS4B TS5B TS6B TS7B TS8B TS9B TS10B TS11B TS12B -- -- TFDLB IMR1B
Note: Framer A and B Test and Reserved registers are used only by the factory; these registers must be cleared (set to all 0's) on power-up initialization to ensure proper operation.
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5. PARALLEL PORT
The DS2196 is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS2196 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the AC Electrical Characteristics in Section 22 for more details.
6. CONTROL, ID, AND TEST REGISTERS
Each framer in the DS2196 is configured via a set of eleven control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2196 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and seven Common Control Registers (CCR1 to CCR7). Each of the eleven registers are described in this section. There is a device Identification Register (IDR) at address 0Fh. The MSB of this read-only register is fixed to a 0 indicating that a T1 device is present. The next 3 MSBs are used to indicate which T1 device is present. The lower 4 bits of the IDR are used to display the die revision of the chip.
Power-Up Sequence
The DS2196 does not automatically clear its register space on power-up. After the supplies are stable, the register space should be configured for operation by writing to all of the internal registers. This includes setting the Test and all unused registers to 00Hex. This can be accomplished using a two-pass approach. 1. Clear DS2196 register space by writing 00h to the addresses 00h through 0FFh. 2. Program required registers to achieve desired operating mode.
IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex)
(MSB) 0 SYMBOL 0 0 1 1 ID3 ID2 ID1 ID0 0 1 POSITION IDR.7 IDR.6 IDR.5 IDR.4 IDR.3 IDR.1 IDR.2 IDR.0 1 ID3 ID2 ID1 (LSB) ID0
NAME AND DESCRIPTION Chip ID Bit 3. MSB of DS2196 identification code. Set to 0. Chip ID Bit 2. DS2196 identification code. Set to 0. Chip ID Bit 1. DS2196 identification code. Set to 1. Chip ID Bit 0. LSB of DS2196 identification code. Set to 1. Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. Chip Revision Bit 2. Chip Revision Bit 1. Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
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The factory in testing the DS2196 uses the two Test Registers at addresses 09 and 7D hex. On power-up, the Test Registers should be set to 00 hex in order for the DS2196 to operate properly.
RCR1A: RECEIVE CONTROL REGISTER 1 FRAMER A (Address = 2B Hex)
(MSB) LCVCRF SYMBOL LCVCRF ARC OOF1 OOF2 SYNCC ARC OOF1 POSITION RCR1A.7 RCR1A.6 RCR1A.5 RCR1A.4 RCR1A.3 OOF2 SYNCC SYNCT SYNCE (LSB) RESYNC
NAME AND DESCRIPTION Line Code Violation Count Register Function Select. 0 = do not count excessive 0's 1 = count excessive 0's Auto Resync Criteria. 0 = Resync on OOF or RCL event 1 = Resync on OOF only Out Of Frame Select 1. 0 = 2/4 frame bits in error 1 = 2/5 frame bits in error Out Of Frame Select 2. 0 = follow RCR1.5 1 = 2/6 frame bits in error Sync Criteria. In D4 Framing Mode. 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode. 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 Sync Time. 0 = qualify 10 bits 1 = qualify 24 bits Sync Enable. 0 = auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync.
SYNCT SYNCE RESYNC
RCR1A.2 RCR1A.1 RCR1A.0
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RCR1B: RECEIVE CONTROL REGISTER 1 FRAMER B (Address = CB Hex)
(MSB) LCVCRF SYMBOL LCVCRF ARC OOF1 OOF2 SYNCC ARC OOF1 POSITION RCR1B.7 RCR1B.6 RCR1B.5 RCR1B.4 RCR1B.3 OOF2 SYNCC SYNCT SYNCE (LSB) RESYNC
NAME AND DESCRIPTION Line Code Violation Count Register Function Select. 0 = do not count excessive 0's 1 = count excessive 0's Auto Resync Criteria. 0 = Resync on OOF or RCL event 1 = Resync on OOF only Out Of Frame Select 1. 0 = 2/4 frame bits in error 1 = 2/5 frame bits in error Out Of Frame Select 2. 0 = follow RCR1.5 1 = 2/6 frame bits in error Sync Criteria. In D4 Framing Mode. 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode. 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 Sync Time. 0 = qualify 10 bits 1 = qualify 24 bits Sync Enable. 0 = auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync.
SYNCT SYNCE RESYNC
RCR1B.2 RCR1B.1 RCR1B.0
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RCR2A: RECEIVE CONTROL REGISTER 2 FRAMER A (Address = 2C Hex)
(MSB) RCS SYMBOL RCS - - - - RD4YM FSBE - - POSITION RCR2A.7 RCR2A.6 RCR2A.5 RCR2A.4 RCR2A.3 RCR2A.2 RCR2A.1 - - RD4YM FSBE (LSB) MOSCRF
NAME AND DESCRIPTION Receive Code Select. See Section 11 for more details. 0 = idle code (7F Hex) 1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex) Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Receive Side D4 Yellow Alarm Select. 0 = 0s in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 PCVCR Fs-Bit Error Report Enable. 0 = do not report bit errors in Fs-bit position; only Ft bit position 1 = report bit errors in Fs-bit position as well as Ft bit position Multiframe Out of Sync Count Register Function Select. 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync
MOSCRF
RCR2A.0
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RCR2B: RECEIVE CONTROL REGISTER 2 FRAMER B (Address = CC Hex)
(MSB) RCS SYMBOL RCS - - - - RD4YM FSBE - - POSITION RCR2B.7 RCR2B.6 RCR2B.5 RCR2B.4 RCR2B.3 RCR2B.2 RCR2B.1 - - RD4YM FSBE (LSB) MOSCRF
NAME AND DESCRIPTION Receive Code Select. See Section 11 for more details. 0 = idle code (7F Hex) 1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex) Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Receive Side D4 Yellow Alarm Select. 0 = 0's in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 PCVCR Fs-Bit Error Report Enable. 0 = do not report bit errors in Fs-bit position; only Ft bit position 1 = report bit errors in Fs-bit position as well as Ft bit position Multiframe Out of Sync Count Register Function Select. 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync
MOSCRF
RCR2B.0
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TCR1A: TRANSMIT CONTROL REGISTER 1 FRAMER A (Address = 35 Hex)
(MSB) LOTCMC SYMBOL LOTCMC TFPT TCPT POSITION TCR1A.7 RBSE GB7S TFDLS TBL (LSB) TYEL
NAME AND DESCRIPTION Loss Of Transmit Clock Mux Control. Determines whether the transmit side of Formatter A should switch to MCLK if the TCLK input should fail to transition (see Figure 1.1 for details). 0 = do not switch to MCLK if TCLKA stops 1 = switch to MCLK if TCLKA stops Transmit F-Bit Pass Through. (see note below) 0 = F bits sourced internally 1 = F bits sampled at TSERA Transmit CRC Pass Through. (see note below) 0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSERA during F-bit time Robbed Bit Signaling Enable. (see note below) 0 = no signaling is inserted in any channel 1 = signaling is inserted in all channels (the TTR registers can be used to block insertion on a channel by channel basis) Global Bit 7 Stuffing. (see note below) 0 = allow the TTR registers to determine which channels containing all 0's are to be Bit 7 stuffed 1 = force Bit 7 stuffing in all zero byte channels regardless of how the TTR registers are programmed TFDL Register Select. (see note below) 0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode) 1 = source FDL or Fs bits from the internal HDLC/BOC controller or the TLINKA pin Transmit Blue Alarm. (see note below) 0 = transmit data normally 1 = transmit an unframed all 1's code at TPOSOA and TNEGOA Transmit Yellow Alarm. (see note below) 0 = do not transmit yellow alarm 1 = transmit yellow alarm
TFPT TCPT RBSE
TCR1A.6 TCR1A.5 TCR1A.4
GB7S
TCR1A.3
TFDLS
TCR1A.2
TBL
TCR1A.1
TYEL
TCR1A.0
NOTE:
For a description of how the bits in TCR1A affect the transmit side formatter, see Figure 21-7.
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TCR1B: TRANSMIT CONTROL REGISTER 1 FRAMER B (Address = D5 Hex)
(MSB) LOTCMC SYMBOL LOTCMC TFPT TCPT POSITION TCR1B.7 RBSE GB7S TFDLS TBL (LSB) TYEL
NAME AND DESCRIPTION Loss Of Transmit Clock Mux Control. Determines whether the transmit side of Formatter B should switch to MCLK if the TCLK input should fail to transition (see Figure 1.1 for details). 0 = do not switch to MCLK if TCLKB stops 1 = switch to MCLK if TCLKB stops Transmit F-Bit Pass Through. (see note below) 0 = F bits sourced internally 1 = F bits sampled at TSERB Transmit CRC Pass Through. (see note below) 0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSERB during F-bit time Robbed Bit Signaling Enable. (see note below) 0 = no signaling is inserted in any channel 1 = signaling is inserted in all channels (the TTR registers can be used to block insertion on a channel by channel basis) Global Bit 7 Stuffing. (see note below) 0 = allow the TTR registers to determine which channels containing all 0's are to be Bit 7 stuffed 1 = force Bit 7 stuffing in all zero byte channels regardless of how the TTR registers are programmed TFDL Register Select. (see note below) 0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode) 1 = source FDL or Fs bits from the internal HDLC/BOC controller or the TLINKB pin Transmit Blue Alarm. (see note below) 0 = transmit data normally 1 = transmit an unframed all 1's code at TPOSOB and TNEGOB Transmit Yellow Alarm. (see note below) 0 = do not transmit yellow alarm 1 = transmit yellow alarm
TFPT TCPT RBSE
TCR1B.6 TCR1B.5 TCR1B.4
GB7S
TCR1B.3
TFDLS
TCR1B.2
TBL
TCR1B.1
TYEL
TCR1B.0
NOTE:
For a description of how the bits in TCR1B affect the transmit side formatter, see Figure 21-7.
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TCR2A: TRANSMIT CONTROL REGISTER 2 FRAMER A (Address = 36 Hex)
(MSB) TEST1 SYMBOL TEST1 TEST0 TAISM TSDW TEST0 TAISM POSITION TCR2A.7 TCR2A.6 TCR2A.5 TCR2A.4 TSDW TSM TSIO TD4YM (LSB) TB7ZS
NAME AND DESCRIPTION Test Mode Bit 1 for Output Pins. See Table 6-1. Test Mode Bit 0 for Output Pins. See Table 6-1. Transmit AIS Mode. 0 = normal AIS 1 = AIS-CI TSYNCA Double-Wide. (note: this bit must be set to 0 when TCR2.3=1 or when TCR2.2=0) 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames TSYNCA Mode Select. 0 = frame mode (see the timing in Section 21) 1 = multiframe mode (see the timing in Section 21) TSYNCA I/O Select. 0 = TSYNCA is an input 1 = TSYNCA is an output Transmit Side D4 Yellow Alarm Select. 0 = 0's in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 Transmit Side Bit 7 Zero Suppression Enable. 0 = no stuffing occurs 1 = Bit 7 force to a 1 in channels with all 0's
TSM TSIO TD4YM TB7ZS
TCR2A.3 TCR2A.2 TCR2A.1 TCR2A.0
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TCR2B: TRANSMIT CONTROL REGISTER 2 FRAMER B (Address = D6 Hex)
(MSB) - SYMBOL - - TAISM TSDW - TAISM POSITION TCR2B.7 TCR2B.6 TCR2A.5 TCR2B.4 TSDW TSM TSIO TD4YM (LSB) TB7ZS
NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Transmit AIS Mode. 0 = normal AIS 1 = AIS-CI TSYNCB Double-Wide. (note: this bit must be set to 0 when TCR2.3=1 or when TCR2.2=0) 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames TSYNCB Mode Select. 0 = frame mode (see the timing in Section 21) 1 = multiframe mode (see the timing in Section 21) TSYNCB I/O Select. 0 = TSYNCB is an input 1 = TSYNCB is an output Transmit Side D4 Yellow Alarm Select. 0 = zeros in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 Transmit Side Bit 7 Zero Suppression Enable. 0 = no stuffing occurs 1 = Bit 7 force to a 1 in channels with all 0's
TSM TSIO TD4YM TB7ZS
TCR2B.3 TCR2B.2 TCR2B.1 TCR2B.0
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Table 6-1: OUTPUT PIN TEST MODES
TEST 1 0 0 1 1 TEST 0 0 1 0 1 EFFECT ON OUTPUT PINS operate normally force all output pins into 3-state (including all I/O pins and parallel port pins) force all output pins low (including all I/O pins except parallel port pins) force all output pins high (including all I/O pins except parallel port pins)
CCR1A: COMMON CONTROL REGISTER 1 FRAMER A (Address = 37 Hex)
(MSB) TRAIM SYMBOL TRAIM ODF ODF RSAO POSITION CCR1A.7 CCR1A.6 RDS2 RDS1 RDS0 PLB (LSB) FLB
NAME AND DESCRIPTION Transmit RAI Mode. Only used in ESF framing mode. 0 = normal RAI 1 = RAI-CI Output Data Format. 0 = bipolar data at TPOSOA and TNEGOA 1 = NRZ data at TPOSOA; TNEGOA = TSYNCA delayed by 10 TCLKAs Receive Signaling All 1's. 0 = allow robbed signaling bits to appear at RSERA 1 = force all robbed signaling bits at RSERA to 1 Receive Data Source Bit 2 See Table 6-2. Receive Data Source Bit 1 See Table 6-2. Receive Data Source Bit 0 See Table 6-2. Payload Loopback. 0 = loopback disabled 1 = loopback enabled Framer Loopback. 0 = loopback disabled 1 = loopback enabled
RSAO RDS2 RDS1 RDS0 PLB FLB
CCR1A.5 CCR1A.4 CCR1A.3 CCR1A.2 CCR1A.1 CCR1A.0
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Table 6-2: Receive Data Source Mux Modes
RDS2 0 0 0 0 1 RDS1 0 0 1 1 X RDS0 0 1 0 1 X Data Source AIS Generator Line Interface Unit PNRZ and PCLK WNRZ and WCLK WPS pin selects source 0 = source from PNRZ/PCLK pins 1 = source from WNRZ/WCLK pins
CCR1B: COMMON CONTROL REGISTER 1 FRAMER B (Address = D7 Hex)
(MSB) TRAIM SYMBOL TRAIM ODF ODF RSAO POSITION CCR1B.7 CCR1B.6 - TDSS1 TDSS0 PLB (LSB) FLB
NAME AND DESCRIPTION Transmit RAI Mode. Only used in ESF framing mode. 0 = normal RAI 1 = RAI-CI Output Data Format. 0 = bipolar data at TPOSOB and TNEGOB 1 = TX NRZ data at TPOSOB; TNEGOB =TFSYNCB= TSYNCB delayed by 10 TCLKBs Receive Signaling All 1's. 0 = allow robbed signaling bits to appear at RSERB 1 = force all robbed signaling bits at RSERB to 1 Not Assigned. Should be set to 0 when written to. TPOS/TNEG Data Source Select 1. Used to select the data source for the TPOSOB & TNEGOB pins when Framer Loopback is active. See table 6-3. TPOS/TNEG Data Source Select 0. Used to select the data source for the TPOSOB & TNEGOB pins when Framer Loopback is active. See table 6-3. Payload Loopback. 0 = loopback disabled 1 = loopback enabled Framer Loopback. 0 = loopback disabled 1 = loopback enabled
RSAO - TDSS1 TDSS0 PLB FLB
CCR1B.5 CCR1B.4 CCR1B.3 CCR1B.2 CCR1B.1 CCR1B.0
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Table 6-3: TPOSB/TNEGB Data Source Select
TTDSS1 TTDSS0 Data Source 0 0 Pass tpos/tclk/tneg from the framer through to the TPOSOB/TCLKOB/TNEGOB pins. 0 1 Force TPOSOB to source data from the BERT circuit. TNEGOB is the frame sync pulse. 1 0 Force TPOSOB high. TNEGOB is the frame sync pulse. 1 1 Force TPOSOB and TNEGOB high.
Payload Loopback A
Payload Loopback When CCR1A.1 is set to a 1, the Framer/Formatter A will be forced into Payload Loopback (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications. In a PLB situation, the DS2196 will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS2196. When PLB is enabled, the following will occur: 1. The TCLKOA signal will become synchronous with RCLKA instead of TCLKA. 2. Data will be transmitted from the TRING and TTIP pins synchronous with RCLKA instead of TCLKA. 3. All of the receive side signals will continue to operate normally. 4. The TCHCLKA and TCHBLKA signals are forced low. 5. TX serial data into Formatter A is ignored.
Payload Loopback B
When CCR1B.1 is set to a 1, the Framer/Formatter B will be forced into Payload Loopback (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications. In a PLB situation, the DS2196 will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS2196. When PLB is enabled, the following will occur: 1. The TCLKOB signal will become synchronous with RCLKIB instead of TCLKB. 2. Data will be transmitted from the TPOSOB and TNEGOB pins synchronous with RCLKIB instead of TCLKB. 3. All of the receive side signals will continue to operate normally. 4. The TCHCLKB and TCHBLKB signals are forced low. 5. TX serial data into Formatter B is ignored.
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Framer Loopback A
When CCR1A.0 is set to a 1, the A Framer/Formatter will enter a Framer Loopback (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS2196 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1. An unframed all 1's code will be transmitted at TPOSOA and TNEGOA outputs 2. Data at RPOSIA and RNEGIA will be ignored 3. All receive side signals will take on timing synchronous with TCLKOA instead of RCLKIA.
NOTE:
The signals RCLKA and TCLKA cannot be the same clock during this loopback because this will cause an unstable condition.
Framer Loopback B
When CCR1B.0 is set to a 1, the B Framer/Formatter will enter a Framer Loopback (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS2196 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1. An unframed all 1's code will be transmitted at TPOSOB and TNEGOB outputs 2. Data at RPOSIB and RNEGIB will be ignored 3. All receive side signals will take on timing synchronous with TCLKOB instead of RCLKIB.
NOTE:
The signals RCLKB and TCLKB cannot be the same clock during this loopback because this will cause an unstable condition.
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CCR2A: COMMON CONTROL REGISTER 2 FRAMER A (Address = 38 Hex)
(MSB) TFM SYMBOL TFM TB8ZS TSLC96 TB8ZS TSLC96 POSITION CCR2A.7 CCR2A.6 CCR2A.5 TZSE RFM RB8ZS RSLC96 (LSB) RFDL
NAME AND DESCRIPTION Transmit Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode Transmit B8ZS Enable. 0 = B8ZS disabled 1 = B8ZS enabled Transmit SLC-96 / Fs-Bit Insertion Enable. Only set this bit to a 1 in D4 framing applications. Must be set to 1 to source the Fs pattern. See Section 18 for details. 0 = SLC-96/Fs-bit insertion disabled 1 = SLC-96/Fs-bit insertion enabled Transmit FDL Zero Stuffer Enable. Set this bit to 0 if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 18 for details. 0 = zero stuffer disabled 1 = zero stuffer enabled Receive Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode Receive B8ZS Enable. 0 = B8ZS disabled 1 = B8ZS enabled Receive SLC-96 Enable. Only set this bit to a 1 in D4/SLC- 96 framing applications. See Section 18 for details. 0 = SLC-96 disabled 1 = SLC-96 enabled Receive FDL Zero Destuffer Enable. Set this bit to 0 if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 18 for details. 0 = zero destuffer disabled 1 = zero destuffer enabled
TZSE
CCR2A.4
RFM RB8ZS RSLC96
CCR2A.3 CCR2A.2 CCR2A.1
RFDL
CCR2A.0
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CCR2B: COMMON CONTROL REGISTER 2 FRAMER B (Address = D8 Hex)
(MSB) TFM SYMBOL TFM TB8ZS TSLC96 TB8ZS TSLC96 POSITION CCR2B.7 CCR2B.6 CCR2B.5 TZSE RFM RB8ZS RSLC96 (LSB) RFDL
NAME AND DESCRIPTION Transmit Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode Transmit B8ZS Enable. 0 = B8ZS disabled 1 = B8ZS enabled Transmit SLC-96 / Fs-Bit Insertion Enable. Only set this bit to a 1 in D4 framing applications. Must be set to 1 to source the Fs pattern. See Section 18 for details. 0 = SLC-96/Fs-bit insertion disabled 1 = SLC-96/Fs-bit insertion enabled Transmit FDL Zero Stuffer Enable. Set this bit to 0 if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 18 for details. 0 = zero stuffer disabled 1 = zero stuffer enabled Receive Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode Receive B8ZS Enable. 0 = B8ZS disabled 1 = B8ZS enabled Receive SLC-96 Enable. Only set this bit to a 1 in D4/SLC- 96 framing applications. See Section 18 for details. 0 = SLC-96 disabled 1 = SLC-96 enabled Receive FDL Zero Destuffer Enable. Set this bit to 0 if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 18 for details. 0 = zero destuffer disabled 1 = zero destuffer enabled
TZSE
CCR2B.4
RFM RB8ZS RSLC96
CCR2B.3 CCR2B.2 CCR2B.1
RFDL
CCR2B.0
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CCR3A: COMMON CONTROL REGISTER 3 FRAMER A (Address = 30 Hex)
(MSB) LIDST TCLKSRC RLOS RSMS FBCT2 ECUS TLOOP (LSB) FBCT1
SYMBOL LIDST
POSITION CCR3A.7
NAME AND DESCRIPTION Line Interface TX Digital Signal Tri-state. Tri-state control for the LIU pins LFSYNC, LCLK and LNRZ. 0 = pins not tri-stated 1 = pins tri-stated Transmit Clock Source Select. This function allows the user to internally select MCLK as the clock source for the transmit side formatter. 0 = TCLK supplied by LOTC mux (see TCR1A.7) 1 = use MCLK for TCLK Function of the RLOSA/LOTCA Output. 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC) RMSYNCA Multiframe Skip Control. Useful in framing format conversions from D4 to ESF. 0 = RMSYNCA will output a pulse at every multiframe 1 = RMSYNCA will output a pulse at every other multiframe F Bit Corruption Type 2. Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set. Error Counter Update Select. Selects the update rate of the error counters and the period of the One Second Timer (SR2A.5). See Sections 7 & 8 for details. 0 = update error counters once a second 1 = update error counters every 42 ms (333 frames) Transmit Loop Code Enable. See Section 12 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in TCD register F Bit Corruption Type 1. A low to high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization.
TCLKSRC
CCR3A.6
RLOSF RSMS
CCR3A.5 CCR3A.4
FBCT2
CCR3A.3
ECUS
CCR3A.2
TLOOP
CCR3A.1
FBCT1
CCR3A.0
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CCR3B: COMMON CONTROL REGISTER 3 FRAMER B (Address = D0 Hex)
(MSB) - TCLKSRC RLOS RSMS FBCT2 ECUS TLOOP (LSB) FBCT1
SYMBOL - TCLKSRC
POSITION CCR3B.7 CCR3B.6
NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Transmit Clock Source Select. This function allows the user to internally select MCLK as the clock source for the transmit side formatter. 0 = TCLK supplied by LOTC mux (see TCR1B.7) 1 = use MCLK for TCLK Function of the RLOSB/LOTCB Output. 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC) RMSYNC Multiframe Skip Control. Useful in framing format conversions from D4 to ESF. 0 = RMSYNCB will output a pulse at every multiframe 1 = RMSYNCB will output a pulse at every other multiframe F Bit Corruption Type 2. Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set. Error Counter Update Select. Selects the update rate of the error counters and the period of the One Second Timer (SR2B.5). See Sections 7 & 8 for details. 0 = update error counters once a second 1 = update error counters every 42 ms (333 frames) Transmit Loop Code Enable. See Section 12 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in TCD register F Bit Corruption Type 1. A low to high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization.
RLOSF RSMS
CCR3B.5 CCR3B.4
FBCT2
CCR3B.3
ECUS
CCR3B.2
TLOOP
CCR3B.1
FBCT1
CCR3B.0
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CCR4A: COMMON CONTROL REGISTER 4 FRAMER A (Address = 11 Hex)
(MSB) LCLKPOL SYMBOL LCLKPOL PWCLKPOL BERTMEN LNRZAIS - LFAMC RTDLPM PWCLKPOL BERTMEN LNRZAIS - LFAMC RTDLPM (LSB) TIRFS
POSITION CCR4A.7 CCR4A.6 CCR4A.5 CCR4A.4 CCR4A.3 CCR4A.2 CCR4A.1
NAME AND DESCRIPTION LCLK Polarity Select. 0 = data updated on rising edge. 1 = data updated on falling edge. PCLK/WCLK Polarity Select. 0 = data sampled on falling edge. 1 = data sampled on rising edge. Transmit BERT Mux Enable. 0 = BERT mux disabled. 1 = BERT mux enabled. LNRZ AIS Enable. 0 = LNRZ and LFSYNC operate normally. 1 = LNRZ =1, LFSYNC = 0. Not Assigned. Must be set to 0 when written. LIU to Framer A Mux Control. 0 = LIU connected on-chip to Framer/Formatter A. 1 = LIU disconnected from Framer/Formatter A. RX/TX Data Link Pin Mode. Determines the function of the RCHCLKA/RLCLKA, RCHBLKA/RLINKA, TCHCLKA/TLCLKA and TCHBLKA/TLINKA pins. 0 = RCHCLKA, RCHBLKA, TCHCLKA, TCHBLKA. 1 = RLCLKA, RLINKA, TLCLKA, TLINKA. Transmit Idle Registers (TIR) Function Select. See Section 11 for timing details. 0 = TIRs define in which channels to insert idle code 1 = TIRs define in which channels to insert data from RSERA (i.e., Per Channel Loopback function)
TIRFS
CCR4A.0
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CCR4B: COMMON CONTROL REGISTER 4 FRAMER B (Address = B1 Hex)
(MSB) RCLKIPOL SYMBOL RCLKIPOL TCLKOPOL BERTMEN - - FAFBMC TCLKOPOL BERTMEN - - FAFBMC RTDLPM (LSB) TIRFS
POSITION CCR4B.7 CCR4B.6 CCR4B.5 CCR4B.4 CCR4B.3 CCR4B.2
NAME AND DESCRIPTION RCLKIB Polarity Select. 0 = no inversion. 1 = invert. TCLKOB Polarity Select. 0 = no inversion. 1 = invert. Transmit BERT Mux Enable. 0 = BERT mux disabled. 1 = BERT mux enabled. Not Assigned. Must be set to 0 when written. Not Assigned. Must be set to 0 when written. Framer/Formatter A to Framer/Formatter B Mux Control. 0 = Framer/Formatter A connected on-chip to Framer/Formatter B 1 = Framer/Formatter A disconnected from Framer/Formatter B RX/TX Data Link Pin Mode. Determines the function of the RCHCLKB/RLCLKB, RCHBLKB/RLINKB, TCHCLKB/TLCLKB and TCHBLKB/TLINKB pins. 0 = RCHCLKB, RCHBLKB, TCHCLKB, TCHBLKB 1 = RLCLKB, RLINKB, TLCLKB, TLINKB Transmit Idle Registers (TIR) Function Select. See Section 11 for timing details. 0 = TIRs define in which channels to insert idle code 1 = TIRs define in which channels to insert data from RSERB (i.e., Per = Channel Loopback function)
RTDLPM
CCR4B.1
TIRFS
CCR4B.0
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CCR5A: COMMON CONTROL REGISTER 5 FRAMER A (Address = 19 Hex)
(MSB) TJC SYMBOL TJC LLB LIAIS LLB LIAIS POSITION CCR5A.7 CCR5A.6 CCR5A.5 TCM4 TCM3 TCM2 TCM1 (LSB) TCM0
NAME AND DESCRIPTION Transmit Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Local Loopback. 0 = loopback disabled 1 = loopback enabled Line Interface AIS Generation Enable. See Figure 1-1 for details. AIS generation is based on MCLK. 0 = allow normal data from TPOSIA/TNEGIA to be transmitted at TTIP and TRING 1 = force unframed all 1's to be transmitted at TTIP and TRING Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 10 for details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
TCM4 TCM3 TCM2 TCM1 TCM0
CCR5A.4 CCR5A.3 CCR5A.2 CCR5A.1 CCR5A.0
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CCR5B: COMMON CONTROL REGISTER 5 FRAMER B (Address = B9 Hex)
(MSB) TJC SYMBOL TJC - - TCM4 TCM3 TCM2 TCM1 TCM0 - - POSITION CCR5B.7 CCR5B.6 CCR5B.5 CCR5B.4 CCR5B.3 CCR5B.2 CCR5B.1 CCR5B.0 TCM4 TCM3 TCM2 TCM1 (LSB) TCM0
NAME AND DESCRIPTION Transmit Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Not Assigned. Must be set to 0 when written. Not Assigned. Must be set to 0 when written. Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 10 for details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
CCR6A: COMMON CONTROL REGISTER 6 FRAMER A (Address = 1E Hex)
(MSB) RJC SYMBOL RJC EAMS MECU EAMS MECU POSITION CCR6A.7 CCR6A.6 CCR6A.5 RCM4 RCM3 RCM2 RCM1 (LSB) RCM0
NAME AND DESCRIPTION Receive Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Error Accumulation Mode Select. 0 = CCR3A.2 determines accumulation time 1 = CCR6A.5 determines accumulation time Manual Error Counter Update. When enabled by CCR6A.6, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 972 ns (1.5 clock periods) before reading the error count registers to allow for proper update. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 10 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode.
RCM4 RCM3 RCM2 RCM1 RCM0
CCR6A.4 CCR6A.3 CCR6A.2 CCR6A.1 CCR6A.0
CCR6B: COMMON CONTROL REGISTER 6 FRAMER B (Address = BE Hex)
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(MSB) RJC SYMBOL RJC EAMS MECU
EAMS
MECU POSITION CCR6B.7 CCR6B.6 CCR6B.5
RCM4
RCM3
RCM2
RCM1
(LSB) RCM0
NAME AND DESCRIPTION Receive Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Error Accumulation Mode Select. 0 = CCR3B.2 determines accumulation time 1 = CCR6B.5 determines accumulation time Manual Error Counter Update. When enabled by CCR6B.6, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 972 ns (1.5 clock periods) before reading the error count registers to allow for proper update. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 10 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode.
RCM4 RCM3 RCM2 RCM1 RCM0
CCR6B.4 CCR6B.3 CCR6B.2 CCR6B.1 CCR6B.0
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CCR7A: COMMON CONTROL REGISTER 7 FRAMER A (Address = 0A Hex)
(MSB) LIRST SYMBOL LIRST RLB AIS13-24 POSITION CCR7A.7 AIS1-12 DISRCL - - (LSB) LBOS3
NAME AND DESCRIPTION Line Interface reset. Setting this bit from a 0 to a 1 will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Remote Loopback. 0 = loopback disabled 1 = loopback enabled Channels 13 - 24 AIS Enable 0 = do not transmit AIS in channels 13 - 24 1 = transmit AIS in channels 13 - 24 Channels 1 - 12 AIS Enable 0 = do not transmit AIS in channels 1 - 12 1 = transmit AIS in channels 1 - 12 LIU Receive Carrier Loss (RCL) pin Disable. 0 = Normal operation. 1 = Disable the LIU RCL pin. Pin will always output a "0". The LRCL status bit in RIR3A.3 continues to report correct LRCL status. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Line Build Out Select Bit 3. Sets the transmitter build out; see the Table 19-1
RLB AIS13-24 AIS1-12 DISRCL
CCR7A.6 CCR7A.5 CCR7A.4 CCR7A.3
- - LBOS3
CCR7A.2 CCR7A.1 CCR7A.0
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CCR7B: COMMON CONTROL REGISTER 7 FRAMER B (Address = AA Hex)
(MSB) - SYMBOL - BELB AIS13-24 AIS1-12 UOP3 UOP2 UOP1 UOP0 BELB AIS13-24 POSITION CCR7B.7 CCR7B.6 CCR7B.5 CCR7B.4 CCR7B.3 CCR7B.2 CCR7B.1 CCR7B.0 AIS1-12 UOP3 UOP2 UOP1 (LSB) UOP0
NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Back End Loopback. 0 = loopback disabled 1 = loopback enabled Channels 13 - 24 AIS Enable 0 = do not transmit AIS in channels 13 - 24 1 = transmit AIS in channels 13 - 24 Channels 1 - 12 AIS Enable 0 = do not transmit AIS in channels 1 - 12 1 = transmit AIS in channels 1 - 12 User Defined Output Pin 3. 0 = logic 0 level at pin 1 = logic 1 level at pin User Defined Output Pin 2. 0 = logic 0 level at pin 1 = logic 1 level at pin User Defined Output Pin 1. 0 = logic 0 level at pin 1 = logic 1 level at pin User Defined Output Pin 0. 0 = logic 0 level at pin 1 = logic 1 level at pin
Remote Loopback
When CCR7A.6 is set to a 1, the 2196 will be forced into Remote Loopback (RLB). In this loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data will continue to pass through the receive side of Framer A as it would normally and the data from the transmit side of Formatter A will be ignored. Please see Figure 1-1 for more details.
Back End Loopback
When CCR7B.6 is set to a 1, the 2196 will be forced into Back End Loopback (BELB). In this loopback, data input via the RPOSIB and RNEGIB pins will be transmitted back to the TPOSOB and TNEGOB pins. Data will continue to pass through the receive side of Framer B as it would normally and the data from the transmit side of Formatter B will be ignored. Please see Figure 1-1 for more details.
Power-Up Sequence
On power-up, after the supplies are stable, the DS2196 should be configured for operation by writing to all of the internal registers (this includes setting the Test Registers to 00Hex) since the contents of the internal registers cannot be predicted on power-up.
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7. STATUS AND INFORMATION REGISTERS
Found in each Framer/Formatter is a set of nine registers that contain information on the current real time status of the DS2196, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers 1 to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller for the FDL. BERT generator and receiver status is contained in the BERT Information Register (BIR). The specific details on the registers pertaining to the BERT and FDL functions are covered in Section 15 and 18 but they operate the same as the other status registers in the DS2196 and this operation is described below. When a particular event has occurred (or is occurring), the appropriate bit in 1 of these nine registers will be set to a 1. All of the bits in SR1, SR2, RIR1, RIR2, and RIR3 registers operate in a latched fashion. This means that if an event or an alarm occurs and a bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the RBL, RYEL, LRCL or FRCL, and RLOS alarms, the bit will remain set if the alarm is still present). There are bits in the four FDL status registers that are not latched and these bits are listed in Section 18. The user will always precede a read of any of the nine registers with a write. The byte written to the register will inform the DS2196 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register will be updated with the latest information. When a 0 is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read- write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2196 with higher-order software languages. The SR1, SR2, HSR and BIR registers have the unique ability to initiate a hardware interrupt via the INT output pin. Each of the alarms and events in the SR1, SR2, HSR and BIR can be either masked or unmasked from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), HDLC Interrupt Mask Register (HIMR) and BERT Control Register (BC1) respectively. The BC1 register is covered in Section 15. The HIMR register is covered in Section 18. The interrupts caused by alarms in SR1 (namely RYEL, LRCL or RCL, RBL, and RLOS) act differently than the interrupts caused by events in SR1 and SR2 (namely LUP, LDN, LSPARE, LOTC, RMF, TMF, SEC, RFDL, TFDL, RMTCH, RAF, and LORC) and FIMR. The alarm caused interrupts will force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 7-2). The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. The event caused interrupts will force the INT pin low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
ISR: INTERRUPT STATUS REGISTER (Address = 0E Hex)
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(MSB) - SYMBOL - BIRQ FDLSB SR2B SR1B FDLSA SR2A SR1A
BIRQ
FDLSB POSITION ISR.7 ISR.6 ISR.5 ISR.4 ISR.3 ISR.2 ISR.1 ISR.0
SR2B
SR1B
FDLSA
SR2A
(LSB) SR1A
NAME AND DESCRIPTION Not Assigned. Could be any value when read. BERT INTERRUPT REQUEST. 0 = No interrupt request pending. 1 = Interrupt request pending. FRAMER B FDLS INTERRUPT REQUEST. 0 = No interrupt request pending. 1 = Interrupt request pending. FRAMER B SR2 INTERRUPT REQUEST. 0 = No interrupt request pending. 1 = Interrupt request pending. FRAMER B SR1 INTERRUPT REQUEST. 0 = No interrupt request pending. 1 = Interrupt request pending. FRAMER A FDLS INTERRUPT REQUEST. 0 = No interrupt request pending. 1 = Interrupt request pending. FRAMER A SR2 INTERRUPT REQUEST. 0 = No interrupt request pending. 1 = Interrupt request pending. FRAMER A SR1 INTERRUPT REQUEST. 0 = No interrupt request pending. 1 = Interrupt request pending.
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RIR1A: RECEIVE INFORMATION REGISTER 1 FRAMER A (Address = 22 Hex)
(MSB) COFA SYMBOL COFA 8ZD 16ZD - - SEFE B8ZS 8ZD 16ZD POSITION RIR1A.7 RIR1A.6 RIR1A.5 RIR1A.4 RIR1A.3 RIR1A.2 RIR1A.1 - - SEFE B8ZS (LSB) FBE
NAME AND DESCRIPTION Change of Frame Alignment. Set when the last resync resulted in a change of frame or multiframe alignment. Eight Zero Detect. Set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at RPOSIA and RNEGIA. Sixteen Zero Detect. Set when a string of at least sixteen consecutive zeros (regardless of the length of the string) have been received at RPOSIA and RNEGIA. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Severely Errored Framing Event. Set when 2 out of 6 framing bits (Ft or FPS) are received in error. B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOSIA and RNEGIA independent of whether the B8ZS mode is selected or not via CCR2.6. Useful for automatically setting the line coding. Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
FBE
RIR1A.0
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RIR1B: RECEIVE INFORMATION REGISTER 1 FRAMER B (Address = C2 Hex)
(MSB) COFA SYMBOL COFA 8ZD 16ZD - - SEFE B8ZS 8ZD 16ZD POSITION RIR1B.7 RIR1B.6 RIR1B.5 RIR1B.4 RIR1B.3 RIR1B.2 RIR1B.1 - - SEFE B8ZS (LSB) FBE
NAME AND DESCRIPTION Change of Frame Alignment. Set when the last resync resulted in a change of frame or multiframe alignment. Eight Zero Detect. Set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at RPOSIB and RNEGIB. Sixteen Zero Detect. Set when a string of at least sixteen consecutive zeros (regardless of the length of the string) have been received at RPOSIB and RNEGIB. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Severely Errored Framing Event. Set when 2 out of 6 framing bits (Ft or FPS) are received in error. B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOSIB and RNEGIB independent of whether the B8ZS mode is selected or not via CCR2.6. Useful for automatically setting the line coding. Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
FBE
RIR1B.0
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RIR2A: RECEIVE INFORMATION REGISTER 2 FRAMER A (Address = 31 Hex)
(MSB) RLOSC SYMBOL RLOSC LRCLC FRCLC - - RBLC - - LRCLC FRCLC POSITION RIR2A.7 RIR2A.6 RIR2A.5 RIR2A.4 RIR2A.3 RIR2A.2 RIR2A.1 RIR2A.0 - - RBLC - (LSB) -
NAME AND DESCRIPTION Receive Loss of Sync Clear. Set when the framer achieves synchronization; will remain set until read. Line Interface Receive Carrier Loss Clear. Set when the carrier signal is restored; will remain set until read. See Table 7-2. Framer Receive Carrier Loss Clear. Set when the carrier signal is restored; will remain set until read. See Table 7-2. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no longer detected; will remain set until read. See Table 7-2. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read.
RIR2B: RECEIVE INFORMATION REGISTER 2 FRAMER B (Address = D1 Hex)
(MSB) RLOSC SYMBOL RLOSC - FRCLC - - RBLC - - FRCLC - POSITION RIR2B.7 RIR2B.6 RIR2B.5 RIR2B.4 RIR2B.3 RIR2B.2 RIR2B.1 RIR2B.0 - - RBLC - (LSB) -
NAME AND DESCRIPTION Receive Loss of Sync Clear. Set when the framer achieves synchronization; will remain set until read. Not Assigned. Could be any value when read. Framer Receive Carrier Loss Clear. Set when the carrier signal is restored; will remain set until read. See Table 7-2. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no longer detected; will remain set until read. See Table 7-2. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read.
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RIR3A: RECEIVE INFORMATION REGISTER 3 FRAMER A (Address = 10 Hex)
(MSB) RL1 SYMBOL RL1 RL0 JALT LORC LRCL RL0 JALT POSITION RIR3A.7 RIR3A.6 RIR3A.5 RIR3A.4 RIR3A.3 LORC LRCL - - (LSB) RAIS-CI
NAME AND DESCRIPTION Receive Level Bit 1. See Table 7-1. Receive Level Bit 0. See Table 7-1. Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4 bits of its limit; useful for debugging jitter attenuation operation. Loss of Receive Clock. Set when the RCLKIA pin has not transitioned for at least 2 ms (3 ms 1ms). Line Interface Receive Carrier Loss. Set when 192 consecutive zeros have been received at the RRING and RTIP pins; allowed to be cleared when 14 or more 1's out of 112 possible bit positions are received. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Receive AIS-CI Detect. Set when the AIS-CI pattern is detected. (see note below)
- - RAIS-CI
RIR3A.2 RIR3A.1 RIR3A.0
RIR3B: RECEIVE INFORMATION REGISTER 3 FRAMER B (Address = B0 Hex)
(MSB) - SYMBOL - - - LORC - - - RAIS-CI - - POSITION RIR3B.7 RIR3B.6 RIR3B.5 RIR3B.4 RIR3B.3 RIR3B.2 RIR3B.1 RIR3A.0 LORC - - - (LSB) RAIS-CI
NAME AND DESCRIPTION Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Loss of Receive Clock. Set when the RCLKIB pin has not transitioned for at least 2 ms(3ms 1ms). Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Receive AIS-CI Detect. Set when the AIS-CI pattern is detected. (see note below)
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Table 7-1: RECEIVE T1 LEVEL INDICATION
RL1 0 0 1 1 RL0 0 1 0 1 TYPICAL LEVEL RECEIVED +2 dB to -7.5 dB -7.5 dB to -15 dB -15 dB to -22.5 dB less than -22.5 dB
NOTE:
The RAIS-CI bit is qualified with the RBL status bit (SR1A.3 and SR1B.3). Hence the RAIS-CI status bit will not be set unless the RBL status bit is set. If the RBL bit is set and the RAIS-CI bit has transitioned from a 1 to a 0 (i.e., it has cleared), it is recommended that the software wait at lest 1.5 seconds and then read the RAIS-CI bit again to make sure that the alarm has indeed cleared.
SR1A: STATUS REGISTER 1 FRAMER A (Address = 20 Hex)
(MSB) LUP SYMBOL LUP LDN LOTC LDN LOTC POSITION SR1A.7 SR1A.6 SR1A.5 LSPARE RBL RYEL FRCL (LSB) RLOS
NAME AND DESCRIPTION Loop Up Code Detected. Set when the loop up code as defined in the RUPCD register is being received. See Section 12 for details. Loop Down Code Detected. Set when the loop down code as defined in the RDNCD register is being received. See Section 12 for details. Loss of Transmit Clock. Set when the TCLKA pin has not transitioned for one channel time (or 5.2 ms). Will force the RLOSA/LOTCA pin high if enabled via CCR1A.6. Also will force transmit side formatter to switch to MCLK if so enabled via TCR1A.7. Spare Code Detected. Set when the spare code as defined in the RSPARE register is being received. See Section 12 for details. Receive Blue Alarm. Set when an unframed all 1's code is received at RPOSIA and RNEGIA. Receive Yellow Alarm. Set when a yellow alarm is received at RPOSIA and RNEGIA. Framer Receive Carrier Loss. Set when a red alarm is received at RPOSIA and RNEGIA. Receive Loss of Sync. Set when the device is not synchronized to the receive T1 stream.
LSPARE RBL RYEL FRCL RLOS
SR1A.4 SR1A.3 SR1A.2 SR1A.1 SR1A.0
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SR1B: STATUS REGISTER 1 FRAMER B (Address = C0 Hex)
(MSB) LUP SYMBOL LUP LDN LOTC LDN LOTC POSITION SR1B.7 SR1B.6 SR1B.5 LSPARE RBL RYEL FRCL (LSB) RLOS
NAME AND DESCRIPTION Loop Up Code Detected. Set when the loop up code as defined in the RUPCD register is being received. See Section 12 for details. Loop Down Code Detected. Set when the loop down code as defined in the RDNCD register is being received. See Section 12 for details. Loss of Transmit Clock. Set when the TCLKB pin has not transitioned for one channel time (or 5.2 ms). Will force the RLOSB/LOTCB pin high if enabled via CCR1B.6. Also will force transmit side formatter to switch to MCLK if so enabled via TCR1B.7. Spare Code Detected. Set when the spare code as defined in the RSPARE register is being received. See Section 12 for details. Receive Blue Alarm. Set when an unframed all 1's code is received at RPOSIB and RNEGIB. Receive Yellow Alarm. Set when a yellow alarm is received at RPOSIB and RNEGIB. Framer Receive Carrier Loss. Set when a red alarm is received at RPOSIB and RNEGIB. Receive Loss of Sync. Set when the device is not synchronized to the receive T1 stream.
LSPARE RBL RYEL FRCL RLOS
SR1B.4 SR1B.3 SR1B.2 SR1B.1 SR1B.0
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Table 7-2: ALARM CRITERIA
ALARM Blue Alarm (AIS) (see note 1 below) Yellow Alarm (RAI) 1. D4 bit 2 mode(RCR2.2=0) SET CRITERIA when over a 3 ms window, 5 or less zeros are received when bit 2 of 256 consecutive channels is set to 0 for at least 254 occurrences when the 12th framing bit is set to "1" for two consecutive occurrences when 16 consecutive patterns of 00FF appear in the FDL when 192 consecutive 0's are received CLEAR CRITERIA when over a 3 ms window, 6 or more zeros are received when bit 2 of 256 consecutive channels is set to 0 for less than 254 occurrences when the 12th framing bit is set to 0 for two consecutive occurrences when 14 or less patterns of 00FF hex out of 16 possible appear in the FDL when 14 or more 1's out of 112 possible bit positions are received starting with the first 1 received
2. D4 12th F-bit mode (RCR2.2=1; this mode is also referred to as the "Japanese Yellow Alarm") 3. ESF mode Red Alarm (LRCL or RCL) (this alarm is also referred to as Loss Of Signal)
NOTES:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all 1'ss signal. Blue alarm detectors should be able to operate properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all 1'ss signal. The blue alarm criteria in the DS2196 have been set to achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit. 2. ANSI specifications use a different nomenclature than the DS2196 does; the following terms are equivalent: RBL = AIS LRCL = LOS RLOS = LOF RYEL = RAI
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SR2A: STATUS REGISTER 2 FRAMER A (Address = 21 Hex)
(MSB) RMF SYMBOL RMF TMF SEC TMF SEC POSITION SR2A.7 SR2A.6 SR2A.5 RFDL TFDL RMTCH RAF (LSB) -
NAME AND DESCRIPTION Receive Multiframe. Set on receive multiframe boundaries. Transmit Multiframe. Set on transmit multiframe boundaries. One Second Timer. Set on increments of one second based on RCLK; will be set in increments of 999 ms, 999 ms, and 1002 ms every 3 seconds. Set on increments of 42 ms (333 frames) if CCR3A.2 = 1. Receive FDL Buffer Full. Set when the receive FDL buffer (RFDL) fills to capacity (8 bits). Transmit FDL Buffer Empty. Set when the transmit FDL buffer (TFDL) empties. Receive FDL Match Occurrence. Set when the RFDL matches either RMTCH1A or RMTCH2A. Receive FDL Abort. Set when eight consecutive 1's's are received in the FDL. Not Assigned. Could be any value when read.
RFDL TFDL RMTCH RAF -
SR2A.4 SR2A.3 SR2A.2 SR2A.1 SR2A.0
SR2B: STATUS REGISTER 2 FRAMER B (Address = C1 Hex)
(MSB) RMF SYMBOL RMF TMF SEC TMF SEC POSITION SR2B.7 SR2B.6 SR2B.5 RFDL TFDL RMTCH RAF (LSB) -
NAME AND DESCRIPTION Receive Multiframe. Set on receive multiframe boundaries. Transmit Multiframe. Set on transmit multiframe boundaries. One Second Timer. Set on increments of one second based on RCLK; will be set in increments of 999 ms, 999 ms, and 1002 ms every 3 seconds. Set on increments of 42 ms (333 frames) if CCR3B.2 = 1. Receive FDL Buffer Full. Set when the receive FDL buffer (RFDL) fills to capacity (8 bits). Transmit FDL Buffer Empty. Set when the transmit FDL buffer (TFDL) empties. Receive FDL Match Occurrence. Set when the RFDL matches either RMTCH1B or RMTCH2B. Receive FDL Abort. Set when eight consecutive 1's's are received in the FDL. Not Assigned. Could be any value when read.
RFDL TFDL RMTCH RAF -
SR2B.4 SR2B.3 SR2B.2 SR2B.1 SR2B.0
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IMR1A: INTERRUPT MASK REGISTER 1 FRAMER A (Address = 7F Hex)
(MSB) LUP SYMBOL LUP LDN LOTC LSPARE RBL RYE FRCL RLOS LDN LOTC POSITION IMR1A.7 IMR1A.6 IMR1A.5 IMR1A.4 IMR1A.3 IMR1A.2 IMR1A.1 IMR1A.0 LSPARE RBL RYEL FRCL (LSB) RLOS
NAME AND DESCRIPTION Loop Up Code Detected. 0 = interrupt masked 1 = interrupt enabled Loop Down Code Detected. 0 = interrupt masked 1 = interrupt enabled Loss of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled Spare Code Detected. 0 = interrupt masked 1 = interrupt enabled Receive Blue Alarm. 0 = interrupt masked 1 = interrupt enabled Receive Yellow Alarm. 0 = interrupt masked 1 = interrupt enabled Framer Receive Carrier Loss. 0 = interrupt masked 1 = interrupt enabled Receive Loss of Sync. 0 = interrupt masked 1 = interrupt enabled
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IMR1B: INTERRUPT MASK REGISTER 1 FRAMER B (Address = FF Hex)
(MSB) LUP SYMBOL LUP LDN LOTC LSPARE RBL RYE FRCL RLOS LDN LOTC POSITION IMR1B.7 IMR1B.6 IMR1B.5 IMR1A.4 IMR1B.3 IMR1B.2 IMR1B.1 IMR1B.0 LSPARE RBL RYEL FRCL (LSB) RLOS
NAME AND DESCRIPTION Loop Up Code Detected. 0 = interrupt masked 1 = interrupt enabled Loop Down Code Detected. 0 = interrupt masked 1 = interrupt enabled Loss of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled Spare Code Detected. 0 = interrupt masked 1 = interrupt enabled Receive Blue Alarm. 0 = interrupt masked 1 = interrupt enabled Receive Yellow Alarm. 0 = interrupt masked 1 = interrupt enabled Framer Receive Carrier Loss. 0 = interrupt masked 1 = interrupt enabled Receive Loss of Sync. 0 = interrupt masked 1 = interrupt enabled
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IMR2A: INTERRUPT MASK REGISTER 2 FRAMER A (Address = 6F Hex)
(MSB) RMF SYMBOL RMF TMF SEC RFDL TFDL RMTCH RAF - TMF SEC POSITION IMR2A.7 IMR2A.6 IMR2A.5 IMR2A.4 IMR2A.3 IMR2A.2 IMR2A.1 IMR2A.0 RFDL TFDL RMTCH RAF (LSB) -
NAME AND DESCRIPTION Receive Multiframe. 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe. 0 = interrupt masked 1 = interrupt enabled One Second Timer. 0 = interrupt masked 1 = interrupt enabled Receive FDL Buffer Full. 0 = interrupt masked 1 = interrupt enabled Transmit FDL Buffer Empty. 0 = interrupt masked 1 = interrupt enabled Receive FDL Match Occurrence. 0 = interrupt masked 1 = interrupt enabled Receive FDL Abort. 0 = interrupt masked 1 = interrupt enabled Not Assigned. Should be set to 0 when written to.
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IMR2B: INTERRUPT MASK REGISTER 2 FRAMER B (Address = EF Hex)
(MSB) RMF SYMBOL RMF TMF SEC RFDL TFDL RMTCH RAF - TMF SEC POSITION IMR2B.7 IMR2B.6 IMR2B.5 IMR2B.4 IMR2B.3 IMR2B.2 IMR2B.1 IMR2B.0 RFDL TFDL RMTCH RAF (LSB) -
NAME AND DESCRIPTION Receive Multiframe. 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe. 0 = interrupt masked 1 = interrupt enabled One Second Timer. 0 = interrupt masked 1 = interrupt enabled Receive FDL Buffer Full. 0 = interrupt masked 1 = interrupt enabled Transmit FDL Buffer Empty. 0 = interrupt masked 1 = interrupt enabled Receive FDL Match Occurrence. 0 = interrupt masked 1 = interrupt enabled Receive FDL Abort. 0 = interrupt masked 1 = interrupt enabled Not Assigned. Should be set to 0 when written to.
8. ERROR COUNT REGISTERS
There is a set of three counters per framer that record bipolar violations, excessive zeros, errors in the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive synchronization. Each of these three counters can be automatically updated on either one second boundaries (CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5) or manually (CCR6.6=1 and triggering with CCR6.5). When updated automatically, the user can use the interrupt from the one-second timer to determine when to read these registers. The user has a full second (or 42 ms) to read the counters before the data is lost. All three counters will saturate at their respective maximum counts and they will not rollover (note: only the Line Code Violation Count Register has the potential to over-flow but the bit error would have to exceed 10E-2 before this would occur).
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Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least significant word of a 16-bit counter that records code violations (CVs). CVs are defined as Bipolar Violations (BPVs) or excessive zeros. See Table 8-1 for details of exactly what the LCVCRs count. If the B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This counter is always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1A: LINE CODE VIOLATION COUNT REGISTER 1 FRAMER A (Address = 23 Hex) LCVCR2A: LINE CODE VIOLATION COUNT REGISTER 2 FRAMER A (Address = 24 Hex) LCVCR1B: LINE CODE VIOLATION COUNT REGISTER 1 FRAMER B (Address = C3 Hex) LCVCR2B: LINE CODE VIOLATION COUNT REGISTER 2 FRAMER B (Address = C4 Hex)
(MSB) LCV15 LCV7 LCV14 LCV6 LCV13 LCV5 POSITION LCVCR1.7 LCVCR2.0 LCV12 LCV4 LCV11 LCV3 LCV10 LCV2 LCV9 LCV1 (LSB) LCV8 LCV0 LCVCR1 LCVCR2
SYMBOL LCV15 LCV0
NAME AND DESCRIPTION MSB of the 16-bit code violation count LSB of the 16-bit code violation count
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Table 8-1: LINE CODE VIOLATION COUNTING ARRANGEMENTS
COUNT EXCESSIVE ZEROS (RCR1.7) no yes no yes B8ZS ENABLED (CCR2.2) no no yes yes WHAT IS COUNTED IN THE LCVCRs BPVs BPVs + 16 consecutive zeros BPVs (B8ZS code words not counted) BPV's + 8 consecutive zeros
Path Code Violation Count Register (PCVCR) When the receive side of a framer is set to operate in the ESF framing mode (CCR2.3=1), PCVCR will automatically be set as a 12-bit counter that will record errors in the CRC6 code words. When set to operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing bit position. Via the RCR2.1 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1) conditions. See Table 8-2 for a detailed description of exactly what errors the PCVCR counts. PCVCR1A: PATH VIOLATION COUNT REGISTER 1 FRAMER A (Address = 25 Hex) PCVCR2A: PATH VIOLATION COUNT REGISTER 2 FRAMER A (Address = 26 Hex) PCVCR1B: PATH VIOLATION COUNT REGISTER 1 FRAMER B (Address = C5 Hex) PCVCR2B: PATH VIOLATION COUNT REGISTER 2 FRAMER B (Address = C6 Hex) (MSB) (note 1) CRC/ FB7 SYMBOL CRC/FB11 CRC/FB0 (note 1) CRC/ FB6 (note 1) CRC/ FB5 POSITION PCVCR1.3 PCVCR2.0 (note 1) CRC/ FB4 CRC/ FB11 CRC/ FB3 CRC/ FB10 CRC/ FB2 CRC/ FB9 CRC/ FB1 (LSB) CRC/ FB8 CRC/ FB0 PCVCR1 PCVCR2
NAME AND DESCRIPTION MSB of the 12-Bit CRC6 Error or Frame Bit Error Count (note #2) LSB of the 12-Bit CRC6 Error or Frame Bit Error Count (note #2)
NOTES:
1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register 2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in the framing bit position (in the D4 framing mode; CCR2.3=0).
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Table 8-2: PATH CODE VIOLATION COUNTING ARRANGEMENTS
FRAMING MODE (CCR2.3) D4 D4 ESF COUNT Fs ERRORS? (RCR2.1) no yes don't care WHAT IS COUNTED IN THE PCVCRs errors in the Ft pattern errors in both the Ft & Fs patterns errors in the CRC6 code words
MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1) conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1) conditions. See Table 8-3 for a detailed description of what the MOSCR is capable of counting.
MOSCR1A: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 FRAMER A (Address = 25 Hex) MOSCR2A: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 FRAMER A (Address = 27 Hex) MOSCR1B: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 FRAMER B (Address = C5 Hex) MOSCR2B: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 FRAMER B (Address = C7 Hex)
(MSB) MOS/ FB11 MOS/ FB7 MOS/ FB10 MOS/ FB6 MOS/ FB9 MOS/ FB5 POSITION MOSCR1.7 MOSCR2.0 MOS/ FB8 MOS/ FB4 (note 1) MOS/ FB3 (note 1) MOS/ FB2 (note 1) MOS/ FB1 (LSB) (note 1) MOS/ FB0 MOSCR1 MOSCR2
SYMBOL MOS/FB11 MOS/FB0
NAME AND DESCRIPTION MSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count (note #2) LSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count (note #2)
NOTES:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register 2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of sync (RCR2.0=1)
Table 8-3: MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS
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FRAMING MODE (CCR2.3) D4 D4 ESF ESF
COUNT MOS OR F-BIT ERRORS (RCR2.0) MOS F-Bit MOS F-Bit
WHAT IS COUNTED IN THE MOSCRs number of multiframes out of sync errors in the Ft pattern number of multiframes out of sync errors in the FPS pattern
9. SIGNALING OPERATION
The robbed-bit signaling bits embedded in the T1 stream can be extracted from the receive stream and inserted into the transmit stream by each framer. There is a set of 12 registers for the receive side (RS1 to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below. The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to 0, then the robbed signaling bits will appear at the RSER pin in their proper position as they are received. If CCR1.5 is set to a 1, then the robbed signaling bit positions will be forced to a 1 at RSER.
RS1A TO RS12A: RECEIVE SIGNALING REGISTERS FRAMER A (Address = 60 to 6B Hex) RS1B TO RS12B: RECEIVE SIGNALING REGISTERS FRAMER B (Address = E0 to EB Hex)
(MSB) A(8) A(16) A(24) B(8) B(16) B(24) A/C(8) A/C(16) A/C(24) B/D(8) B/D(16) B/D(24) A(7) A(15) A(23) B(7) B(15) B(23) A/C(7) A/C(15) A/C(23) B/D(7) B/D(15) B/D(23) A(6) A(14) A(22) B(6) B(14) B(22) A/C(6) A/C(14) A/C(22) B/D(6) B/D(14) B/D(22) A(5) A(13) A(21) B(5) B(13) B(21) A/C(5) A/C(13) A/C(21) B/D(5) B/D(13) B/D(21) A(4) A(12) A(20) B(4) B(12) B(20) A/C(4) A/C(12) A/C(20) B/D(4) B/D(12) B/D(20) A(3) A(11) A(19) B(3) B(11) B(19) A/C(3) A/C(11) A/C(19) B/D(3) B/D(11) B/D(19) A(2) A(10) A(18) B(2) B(10) B(18) A/C(2) A/C(10) A/C(18) B/D(2) B/D(10) B/D(18) (LSB) A(1) A(9) A(17) B(1) B(9) B(17) A/C(1) A/C(9) A/C(17) B/D(1) B/D(9) B/D(17) RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12
SYMBOL D(24) A(1)
POSITION RS12.7 RS1.0
NAME AND DESCRIPTION Signaling Bit D in Channel 24 Signaling Bit A in Channel 1
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Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only two framing bits per channel (A and B). In the D4 framing mode, the framer will replace the C and D signaling bit positions with the A and B signaling bits from the previous multiframe. Hence, whether the framer is operated in either framing mode, the user needs only to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent signaling information before the "OOF" occurred. The signaling data reported in RS1 to RS12 is also available at the RSER pin.
TS1A TO TS12A: TRANSMIT SIGNALING REGISTERS FRAMER A (Address = 70 to 7B Hex) TS1B TO TS12B: TRANSMIT SIGNALING REGISTERS FRAMER B (Address = F0 to FB Hex)
(MSB) A(8) A(16) A(24) B(8) B(16) B(24) A/C(8) A/C(16) A/C(24) B/D(8) B/D(16) B/D(24) A(7) A(15) A(23) B(7) B(15) B(23) A/C(7) A/C(15) A/C(23) B/D(7) B/D(15) B/D(23) A(6) A(14) A(22) B(6) B(14) B(22) A/C(6) A/C(14) A/C(22) B/D(6) B/D(14) B/D(22) A(5) A(13) A(21) B(5) B(13) B(21) A/C(5) A/C(13) A/C(21) B/D(5) B/D(13) B/D(21) A(4) A(12) A(20) B(4) B(12) B(20) A/C(4) A/C(12) A/C(20) B/D(4) B/D(12) B/D(20) A(3) A(11) A(19) B(3) B(11) B(19) A/C(3) A/C(11) A/C(19) B/D(3) B/D(11) B/D(19) A(2) A(10) A(18) B(2) B(10) B(18) A/C(2) A/C(10) A/C(18) B/D(2) B/D(10) B/D(18) (LSB) A(1) A(9) A(17) B(1) B(9) B(17) A/C(1) A/C(9) A/C(17) B/D(1) B/D(9) B/D(17) TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12
SYMBOL D(24) A(1)
POSITION TS12.7 TS1.0
NAME AND DESCRIPTION Signaling Bit D in Channel 24 Signaling Bit A in Channel 1
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0 channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe boundaries, the framer will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing mode, the interrupt will come every 3 ms and the user has a full 3ms to update the TSRs. In the D4 framing mode, there are only two framing bits per channel (A and B). However in the D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. The framer will load the values in the TSRs into the outgoing shift register every other D4 multiframe.
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10.
DS0 MONITORING FUNCTION
Each framer in the DS2196 has the ability to monitor one DS0 64 kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR5A & CCR5B registers. In the receive direction, the RCM0 to RCM4 bits in the CCR6A & CCR6B registers need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1 channel. Channels 1 through 24 map to register values 0 through 23. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into CCR5 and CCR6: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1 RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0
CCR5A: COMMON CONTROL REGISTER 5 FRAMER A (Address = 19 Hex) CCR5B: COMMON CONTROL REGISTER 5 FRAMER B (Address = B9 Hex)
[Repeated here from section 6 for convenience with only the TX monitor function present] (MSB) TCM4 SYMBOL TCM4 TCM3 TCM2 TCM1 TCM0 POSITION CCR5.4 CCR5.3 CCR5.2 CCR5.1 CCR5.0 TCM3 TCM2 TCM1 (LSB) TCM0
NAME AND DESCRIPTION Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
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TDS0MA: TRANSMIT DS0 MONITOR REGISTER FRAMER A (Address = 1A Hex) TDS0MB: TRANSMIT DS0 MONITOR REGISTER FRAMER B (Address = BA Hex)
(MSB) B1 SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 B2 B3 POSITION TDS0M.7 TDS0M.6 TDS0M.5 TDS0M.4 TDS0M.3 TDS0M.2 TDS0M.1 TDS0M.0 B4 B5 B6 B7 (LSB) B8
NAME AND DESCRIPTION Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2. Transmit DS0 Channel Bit 3. Transmit DS0 Channel Bit 4. Transmit DS0 Channel Bit 5. Transmit DS0 Channel Bit 6. Transmit DS0 Channel Bit 7. Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted).
CCR6A: COMMON CONTROL REGISTER 6 FRAMER A (Address = 1E Hex) CCR6B: COMMON CONTROL REGISTER 6 FRAMER B (Address = BE Hex)
[Repeated here from section 6 for convenience with only the RX monitor function present] (MSB) RCM4 SYMBOL RCM4 RCM3 RCM2 RCM1 RCM0 POSITION CCR5.4 CCR5.3 CCR5.2 CCR5.1 CCR5.0 RCM3 RCM2 RCM1 (LSB) RCM0
NAME AND DESCRIPTION Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive DS0 channel data will appear in the RDS0M register. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode that determines which receive DS0 channel data will appear in the RDS0M register.
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RDS0MA: RECEIVE DS0 MONITOR REGISTER FRAMER A (Address = 1F Hex) RDS0MB: RECEIVE DS0 MONITOR REGISTER FRAMER B (Address = BF Hex)
(MSB) B1 SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 B2 B3 POSITION RDS0M.7 RDS0M.6 RDS0M.5 RDS0M.4 RDS0M.3 RDS0M.2 RDS0M.1 RDS0M.0 B4 B5 B6 B7 (LSB) B8
NAME AND DESCRIPTION Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be received). Receive DS0 Channel Bit 2. Receive DS0 Channel Bit 3. Receive DS0 Channel Bit 4. Receive DS0 Channel Bit 5. Receive DS0 Channel Bit 6. Receive DS0 Channel Bit 7. Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be received).
11.
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
The DS2196 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the T1 line and is covered in Section 11.1. The receive direction is from the T1 line to the backplane and is covered in Section 11.2.
11.1 TRANSMIT SIDE CODE GENERATION
The Transmit Idle Registers (TIR1/2/3) are used to determine which of the 24 T1 channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allows the same 8-bit code to be placed into any of the 24 T1 channels. If this method is used, then the CCR4.0 control bit must be set to 0. Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR). Bit 7 stuffing will occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers. The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per-Channel Loopback (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RSYNC to TSYNC.
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TIR1A/TIR2A/TIR3A: TRANSMIT IDLE REGISTERS FRAMER A (Address = 3C to 3E Hex) TIR1B/TIR2B/TIR3B: TRANSMIT IDLE REGISTERS FRAMER B (Address = DC to DE Hex)
[Also used for Per-Channel Loopback] (MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITIONS TIR1.0-3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TIR1 TIR2 TIR3
SYMBOLS CH1-24
NAME AND DESCRIPTION Transmit Idle Code Insertion Control Bits. 0 = do not insert the Idle Code in the TIDR into this channel 1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR4.0=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel Loopback; see Figure 1-1).
TIDRA: TRANSMIT IDLE DEFINITION REGISTER FRAMER A (Address = 3F Hex) TIDRB: TRANSMIT IDLE DEFINITION REGISTER FRAMER B (Address = DF Hex)
(MSB) TIDR7 SYMBOL TIDR7 TIDR0 TIDR6 TIDR5 POSITION TIDR.7 TIDR.0 TIDR4 TIDR3 TIDR2 TIDR1 (LSB) TIDR0
NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last)
11.2 RECEIVE SIDE CODE GENERATION
The Receive Mark Registers (RMR1/2/3) are used to determine which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a digital milliwatt pattern. The RCR2.7 bit will determine which code is used. The digital milliwatt code is an eight-byte repeating pattern that represents a 1 kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs, represents a particular channel. If a bit is set to a 1, then the receive data in that channel will be replaced with one of the two codes. If a bit is set to 0, no replacement occurs.
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RMR1A/RMR2A/RMR3A: RECEIVE MARK REGISTERS FRAMER A (Address = 2D to 2F Hex) RMR1B/RMR2B/RMR3B: RECEIVE MARK REGISTERS FRAMER B (Address = CD to CF Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITIONS RMR1.0-3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 RMR1 RMR2 RMR3
SYMBOLS CH1-24
NAME AND DESCRIPTION Receive Channel Mark Control Bits 0 =do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with either the idle code or the digital milliwatt code (depends on the RCR2.7 bit)
12.
PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION
Each framer in the DS2196 has the ability to generate and detect a repeating bit pattern that is from one to 8 bits and 16 bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD1&TCD2) registers and select the proper length of the pattern by setting the TC0 and TC1 bits in the In-Band Code Control (IBCC) register. When generating a 1, 2, 4, 8 or 16 bit pattern both transmit code definition registers (TCD1&TCD2) must be filled with the proper code. Generation of a 3, 5, 6 and 7 bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (CCR3.1) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the framer will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent. See Figure 21-7 for more details. As an example, if the user wished to transmit the standard "loop up" code for Channel Service Units which is a repeating pattern of ...10000100001... then 80h would be loaded into TCD1 and the length would set to 5 bits. Each framer can detect three separate repeating patterns. Typically, two of the detectors are used for "loop up" and "loop down" code detection. The user will program the codes to be detected in the Receive Up Code Definition (RUPCD1 & RUPCD2) registers and the Receive Down Code Definition (RDNCD1 & RDNCD2) registers and the length of each pattern will be selected via the IBCC register. There is a third detector (Spare) and it is defined and controlled via the RSCD1/RSCD2 and RSCC registers. When detecting an 8 or 16 bit pattern both receive code definition registers must be filled with the proper code. For 8 bit patterns both receive code definition registers will be filled with the same value. Detection of a 1, 2, 3, 4, 5, 6 and 7 bit pattern only requires the first receive code definition register to be filled. A third or spare detector is available for user definition. The framer will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10E-2. The detectors are capable of handling both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of receive code definition register resets the integration period for that detector. The code detector has a nominal integration period of 30 ms. Hence, after about 30 ms of receiving a valid code, the proper status bit (LUP at SR1A/B.7 , LDN at SR1A/B.6 and LSPARE at SR1A/B.4 ) will be set to a 1. Normally codes are sent for a period of 5 seconds. It is recommend that the software poll the framer every 50 ms to 1000 ms until 5 seconds has elapsed to insure that the code is continuously present.
IBCCA: IN-BAND CODE CONTROL REGISTER FRAMER A (Address = 12 Hex)
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IBCCB: IN-BAND CODE CONTROL REGISTER FRAMER B (Address = B2 Hex)
(MSB) TC1 SYMBOL TC1 TC0 RUP2 RUP1 RUP0 RDN2 RDN1 RDN0 TC0 RUP2 POSITION IBCC.7 IBCC.6 IBCC.5 IBCC.4 IBCC.3 IBCC.2 IBCC.1 IBCC.0 RUP1 RUP0 RDN2 RDN1 (LSB) RDN0
NAME AND DESCRIPTION Transmit Code Length Definition Bit 1. See Table 12-1 Transmit Code Length Definition Bit 0. See Table 12-1 Receive Up Code Length Definition Bit 2. See Table 12-2 Receive Up Code Length Definition Bit 1. See Table 12-2 Receive Up Code Length Definition Bit 0. See Table 12-2 Receive Down Code Length Definition Bit 2. See Table 12-2 Receive Down Code Length Definition Bit 1. See Table 12-2 Receive Down Code Length Definition Bit 0. See Table 12-2
Table 12-1: TRANSMIT CODE LENGTH
TC1 0 0 1 1 TC0 0 1 0 1 LENGTH SELECTED 5 bits 6 bits / 3 bits 7 bits 16 bits / 8 bits / 4 bits / 2 bits / 1 bit
Table 12-2: RECEIVE CODE LENGTH
RUP2/ RDN2/RSC2 0 0 0 0 1 1 1 1 RUP1/ RDN1/RSC1 0 0 1 1 0 0 1 1 RUP0/ RDN0/RSC0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 / 16 bits
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TCD1A: TRANSMIT CODE DEFINITION REGISTER 1 FRAMER A (Address = 13 Hex) TCD1B: TRANSMIT CODE DEFINITION REGISTER 1 FRAMER B (Address = B3 Hex)
(MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 POSITION TCD1.7 TCD1.6 TCD1.5 TCD1.4 TCD1.3 TCD1.2 TCD1.1 TCD1.0 C5 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Transmit Code Definition Bit 7. Transmit Code Definition Bit 6. Transmit Code Definition Bit 5. Transmit Code Definition Bit 4. Transmit Code Definition Bit 3. Transmit Code Definition Bit 2. Transmit Code Definition Bit 1. selected. Transmit Code Definition Bit 0. selected.
First bit of the repeating pattern.
A Don't Care if a 5-bit length is selected. A Don't Care if a 5 or 6 bit length is A Don't Care if a 5, 6 or 7 bit length is
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TCD2A: TRANSMIT CODE DEFINITION REGISTER 2 FRAMER A (Address = 16 Hex) TCD2B: TRANSMIT CODE DEFINITION REGISTER 2 FRAMER B (Address = B6 Hex)
Least significant byte of 16 bit codes (MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION TCD2.7 TCD2.6 TCD2.5 TCD2.4 TCD2.3 TCD2.2 TCD2.1 TCD2.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Transmit Code Definition Bit 7. 7 bit length is selected. Transmit Code Definition Bit 6. 7 bit length is selected. Transmit Code Definition Bit 5. 7 bit length is selected. Transmit Code Definition Bit 4. 7 bit length is selected. Transmit Code Definition Bit 3. 7 bit length is selected. Transmit Code Definition Bit 2. 7 bit length is selected. Transmit Code Definition Bit 1. 7 bit length is selected. Transmit Code Definition Bit 0. 7 bit length is selected.
A Don't Care if a 5, 6 or A Don't Care if a 5, 6 or A Don't Care if a 5, 6 or A Don't Care if a 5, 6 or A Don't Care if a 5, 6 or A Don't Care if a 5, 6 or A Don't Care if a 5, 6 or A Don't Care if a 5, 6 or
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RUPCD1A: RECEIVE UP CODE DEFINITION REGISTER 1 FRAMER A (Address = 14 Hex) RUPCD1B: RECEIVE UP CODE DEFINITION REGISTER 1 FRAMER B (Address = B4 Hex) NOTE:
Writing this register resets the detector's integration period. (MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION RUPCD1.7 RUPCD1.6 RUPCD1.5 RUPCD1.4 RUPCD1.3 RUPCD1.2 RUPCD1.1 RUPCD1.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Receive Up Code Definition Bit 7. pattern. Receive Up Code Definition Bit 6. length is selected. Receive Up Code Definition Bit 5. length is selected. Receive Up Code Definition Bit 4. length is selected. Receive Up Code Definition Bit 3. length is selected. Receive Up Code Definition Bit 2. length is selected. Receive Up Code Definition Bit 1. length is selected. Receive Up Code Definition Bit 0. length is selected.
First bit of the repeating A Don't Care if a 1 bit A Don't Care if a 1 or 2 bit A Don't Care if a 1 to 3 bit A Don't Care if a 1 to 4 bit A Don't Care if a 1 to 5 bit A Don't Care if a 1 to 6 bit A Don't Care if a 1 to 7 bit
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RUPCD2A: RECEIVE UP CODE DEFINITION REGISTER 2 FRAMER A (Address = 17 Hex) RUPCD2B: RECEIVE UP CODE DEFINITION REGISTER 2 FRAMER B (Address = B7 Hex)
(MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION RUPCD2.7 RUPCD2.6 RUPCD2.5 RUPCD2.4 RUPCD2.3 RUPCD2.2 RUPCD2.1 RUPCD2.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Receive Up Code Definition Bit 7. length is selected. Receive Up Code Definition Bit 6. length is selected. Receive Up Code Definition Bit 5. length is selected. Receive Up Code Definition Bit 4. length is selected. Receive Up Code Definition Bit 3. length is selected. Receive Up Code Definition Bit 2. length is selected. Receive Up Code Definition Bit 1. length is selected. Receive Up Code Definition Bit 0. length is selected.
A Don't Care if a 1 to 7 bit A Don't Care if a 1 to 7 bit A Don't Care if a 1 to 7 bit A Don't Care if a 1 to 7 bit A Don't Care if a 1 to 7 bit A Don't Care if a 1 to 7 bit A Don't Care if a 1 to 7 bit A Don't Care if a 1 to 7 bit
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RDNCD1A: RECEIVE DOWN CODE DEFINITION REGISTER 1 FRAMER A (Address = 15 Hex) RDNCD1B: RECEIVE DOWN CODE DEFINITION REGISTER 1 FRAMER B (Address = B5 Hex) NOTE:
Writing this register resets the detector's integration period. (MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION RDNCD1.7 RDNCD1.6 RDNCD1.5 RDNCD1.4 RDNCD1.3 RDNCD1.2 RDNCD1.1 RDNCD1.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Receive Down Code Definition Bit 7. pattern. Receive Down Code Definition Bit 6. length is selected. Receive Down Code Definition Bit 5. 2 bit length is selected. Receive Down Code Definition Bit 4. 3 bit length is selected. Receive Down Code Definition Bit 3. 4 bit length is selected. Receive Down Code Definition Bit 2. 5 bit length is selected. Receive Down Code Definition Bit 1. 6 bit length is selected. Receive Down Code Definition Bit 0. 7 bit length is selected.
First bit of the repeating A Don't Care if a 1 bit A Don't Care if a 1 or A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to
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RDNCD2A: RECEIVE DOWN CODE DEFINITION REGISTER 2 FRAMER A (Address = 18 Hex) RDNCD2B: RECEIVE DOWN CODE DEFINITION REGISTER 2 FRAMER B (Address = B8 Hex)
(MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION RDNCD2.7 RDNCD2.6 RDNCD2.5 RDNCD2.4 RDNCD2.3 RDNCD2.2 RDNCD2.1 RDNCD2.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Receive Down Code Definition Bit 7. 7 bit length is selected. Receive Down Code Definition Bit 6. 7 bit length is selected. Receive Down Code Definition Bit 5. 7 bit length is selected. Receive Down Code Definition Bit 4. 7 bit length is selected. Receive Down Code Definition Bit 3. 7 bit length is selected. Receive Down Code Definition Bit 2. 7 bit length is selected. Receive Down Code Definition Bit 1. 7 bit length is selected. Receive Down Code Definition Bit 0. 7 bit length is selected.
A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to
RSCCA: IN-BAND RECEIVE SPARE CONTROL REGISTER FRAMER A (Address = 1D Hex) RSCCB: IN-BAND RECEIVE SPARE CONTROL REGISTER FRAMER B (Address = BD Hex)
(MSB) - SYMBOL - - - - - RSC2 RSC1 RSC0 - - POSITION RSCC.7 RSCC.6 RSCC.5 RSCC.4 RSCC.3 RSCC.2 RSCC.1 RSCC.0 - - RSC2 RSC1 (LSB) RSC0
NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Receive Spare Code Length Definition Bit 2. See Table 12-2 Receive Spare Code Length Definition Bit 1. See Table 12-2 Receive Spare Code Length Definition Bit 0. See Table 12-2
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RSCD1A: RECEIVE SPARE CODE DEFINITION REGISTER 1 FRAMER A (Address = 1B Hex) RSCD1B: RECEIVE SPARE CODE DEFINITION REGISTER 1 FRAMER B (Address = BB Hex) NOTE:
Writing this register resets the detector's integration period. (MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION RSCD1.7 RSCD1.6 RSCD1.5 RSCD1.4 RSCD1.3 RSCD1.2 RSCD1.1 RSCD1.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Receive Spare Code Definition Bit 7. pattern. Receive Spare Code Definition Bit 6. length is selected. Receive Spare Code Definition Bit 5. 2 bit length is selected. Receive Spare Code Definition Bit 4. 3 bit length is selected. Receive Spare Code Definition Bit 3. 4 bit length is selected. Receive Spare Code Definition Bit 2. 5 bit length is selected. Receive Spare Code Definition Bit 1. 6 bit length is selected. Receive Spare Code Definition Bit 0. 7 bit length is selected.
First bit of the repeating A Don't Care if a 1-bit A Don't Care if a 1 or A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to
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RSCD2A: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER A (Address = 1C Hex) RSCD2B: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER B (Address = BC Hex)
(MSB) C7 SYMBOL C7 C6 C5 C4 C3 C2 C1 C0 C6 C5 POSITION RSCD2.7 RSCD2.6 RSCD2.5 RSCD2.4 RSCD2.3 RSCD2.2 RSCD2.1 RSCD2.0 C4 C3 C2 C1 (LSB) C0
NAME AND DESCRIPTION Receive Spare Code Definition Bit 7. 7 bit length is selected. Receive Spare Code Definition Bit 6. 7 bit length is selected. Receive Spare Code Definition Bit 5. 7 bit length is selected. Receive Spare Code Definition Bit 4. 7 bit length is selected. Receive Spare Code Definition Bit 3. 7 bit length is selected. Receive Spare Code Definition Bit 2. 7 bit length is selected. Receive Spare Code Definition Bit 1. 7 bit length is selected. Receive Spare Code Definition Bit 0. 7 bit length is selected.
A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to A Don't Care if a 1 to
13.
CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a UART or LAPD controller in Fractional T1 or ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and TCHBLK pins will be held high during the entire corresponding channel time. See the timing in Section 21 for an example.
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RCBR1A/RCBR2A/RCBR3A: RECEIVE CHANNEL BLOCKING REGISTERS FRAMER A (Address = 6C to 6E Hex) RCBR1B/RCBR2B/RCBR3B: RECEIVE CHANNEL BLOCKING REGISTERS FRAMER B (Address = EC to EE Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITIONS RCBR1.0-3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 RCBR1 RCBR2 RCBR3
SYMBOLS CH1-24
NAME AND DESCRIPTION Receive Channel Blocking Control Bits. 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time
TCBR1A/TCBR2A/TCBR3A: TRANSMIT CHANNEL BLOCKING REGISTERS FRAMER A (Address = 32 to 34 Hex) TCBR1B/TCBR2B/TCBR3B: TRANSMIT CHANNEL BLOCKING REGISTERS FRAMER B (Address = D2 to D4 Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITIONS TCBR1.0-3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TCBR1 TCBR2 TCBR3
SYMBOLS CH1-24
NAME AND DESCRIPTION Transmit Channel Blocking Control Bits. 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time
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14.
TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or in other words, can be forced to stop Bit 7 Stuffing from overwriting the data in the channels. Transparency can be invoked on a channel by channel basis by properly setting the TTR1, TTR2, and TTR3 registers. Each of the bit position in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represent a DS0 channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or clear). If a DS0 is programmed to be clear, no Bit 7 stuffing will be performed. However, in the D4 framing mode, bit 2 will be overwritten by a zero when a Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from determining which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all 24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are programmed. Please see Figure 21-7 for more details.
TTR1A/TTR2A/TTR3A: TRANSMIT TRANSPARENCY REGISTER FRAMER A (Address = 39 to 3B Hex) TTR1B/TTR2B/TTR3B: TRANSMIT TRANSPARENCY REGISTER FRAMER B (Address = D9 to DB Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITIONS TTR1.0-3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TTR1 TTR2 TTR3
SYMBOLS CH1-24
NAME AND DESCRIPTION Transmit Transparency Registers. 0 = this DS0 channel is not transparent 1 = this DS0 channel is transparent
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15.
BERT FUNCTION
The BERT Block can generate and detect both pseudorandom and repeating bit patterns and it is used to test and stress data communication links. The BERT Block is capable of generating and detected the following patterns: * * * * The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS A repetitive pattern from 1 to 32 bits in length Alternating (16-bit) words which flip every 1 to 256 words Daly pattern
The BERT receiver has a 32-bit Bit Counter and a 24-bit Error Counter. The BERT receiver will report three events, a change in receive synchronizer status, a bit error being detected, and if either the Bit Counter or the Error Counter overflows. Each of these events can be masked within the BERT function via the BERT Control Register 1 (BC1). If the software detects that the BERT has reported an event has occurred, then the software must read the BERT Information Register (BIR) to determine which event(s) has occurred. To activate the BERT Block, the Host must configure the BERT mux via the BIC register (see Figure 15-1). The BERT INTERRUPT REQUEST (BIRQ) status bit located at ISR.6 will be set to a 1 if there is a major change of state in the BERT receiver. A major change of state is defined as either a change in the receive synchronization (i.e. the BERT has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the Bit Counter or the Error Counter. The Host must read the status bits of the BERT in the BERT Information Register (BIR) to determine the change of state. The BIRQ bit will be cleared when read and will not be set again until the BERT has experienced another change of state.
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Figure 15-1: BERT Mux Diagram
BERT
clock
clock
transmit load
data
data
RECEIVE SIDE
TRANSMIT SIDE
Transmit Load Signal Generation
Frame Sync Align Toggle (BIC.3)
Formatter / FLB B Select Mux Note 2 Note 2
FLB B BERT Select (decoded from CCR1B.2 & CCR1B.3)
Framed / Unframed Select (BIC.6) Note 1 Note 1
Framed / Unframed Select (BIC.2)
Use RCHBLK Select (BIC.5)
Use TCHBLK Select (BIC.1) fsync
tchblk
clock
clock
data
rchblk clock
fsync
data
Framer A/B Select (BIC.4)
Framer A/B Select mux
Formatter A/B Select mux
Formatter A/B Select (BIC.0) fsync tchblk
fsync
tchblk
clock clock
clock
data
Note 1: Always includes a clock pulse for the F-bit position Note 2: F-bit clock is blocked in the framed mode enable (CCR4B.5) normal transmit data mux
fsync rchblk clock Framer A
fsync rchblk clock
data
data enable (CCR4A.5) normal transmit data
CCR1B.2 / CCR1B.3 Formatter A Formatter B tpos/tnrz tclk clock data mux tneg/ tfsync thru mode FLB B Mux
Framer B
Transmit Formatter A
BERT tpos/tnrz mode tclk AIS with Sync AIS w/o Sync tneg/ tfsync
bert_mux
Transmit Formatter B
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15.1 BERT REGISTER DESCRIPTION BC0: BERT CONTROL REGISTER 0 (Address = 40 Hex)
(MSB) - SYMBOL - TINV RINV PS2 PS1 PS0 LC TINV RINV POSITION BC0.7 BC0.6 BC0.5 BC0.4 BC0.3 BC0.2 BC0.1 PS2 PS1 PS0 LC (LSB) RESYNC
RESYNC
BC0.0
NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Transmit Invert Data Enable (TINV). 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream Receive Invert Data Enable (RINV). 0 = do not invert the incoming data stream 1 = invert the incoming data stream Pattern Select Bit 2. Refer to Table 15-1 for details. Pattern Select Bit 1. Refer to Table 15-1 for details. Pattern Select Bit 0. Refer to Table 15-1 for details. Load Bit and Error Counters (LC). A low to high transition latches the current bit and error counts into the host accessible registers BBC0/BBC1/BBC2/BBC3 and BEC0/BEC1/BEC2 and clears the internal count. This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a subsequent loads. Force Resynchronization (RESYNC). A low to high transition will force the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
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Table 15-1: BERT PATTERN SELECT OPTIONS
PS2 0 0 0 0 1 1 1 PS1 0 0 1 1 0 0 1 PS0 0 1 0 1 0 1 0 Pattern Definition Pseudorandom 2E7 - 1 Pseudorandom 2E11 - 1 Pseudorandom 2E15 - 1 Pseudorandom Pattern QRSS. A 220 - 1 pattern with 14 consecutive zero restriction. Repetitive Pattern Alternating Word Pattern Modified 55 Octet (Daly) Pattern The Daly pattern is a repeating 55 octet pattern that is byte aligned into the active DS0 timeslots. The pattern is defined in a ATIS (Alliance for Telecommunications Industry Solutions) Committee T1 Technical Report Number 25 (November 1993). Reserved
1
1
1
BC1: BERT Control Register 1 (Address = 41 Hex)
(MSB) IESYNC SYMBOL IESYNC IEBED IEOF POSITION BC1.7 - RPL3 RPL2 RPL1 (LSB) RPL0
IEBED
BC1.6
IEOF
BC1.5
- RPL3 RPL2 RPL1 RPL0
BC1.4 BC1.3 BC1.2 BC1.1 BC1.0
NAME AND DESCRIPTION Change of Synchronization Status Interrupt Enable. Interrupt enable for Synchronizer Status (BIR.0) 0 = interrupt masked 1 = interrupt enabled Bit Error Detected Interrupt Enable. Interrupt enable for Bit Error Detected (BIR.3) 0 = interrupt masked 1 = interrupt enabled Bit & Error Counter Overflow Interrupt Enable. Interrupt enable for the BERT Bit Counter (BIR.2) and BERT Error Counter (BIR.1) overflow. 0 = interrupt masked 1 = interrupt enabled Not Assigned. Should be set to 0 when written to. Repetitive Pattern Length Bit 3 (RPL3). Refer to Table 15-2 for details. Repetitive Pattern Length Bit 2 (RPL2). Refer to Table 15-2 for details. Repetitive Pattern Length Bit 1 (RPL1). Refer to Table 15-2 for details. Repetitive Pattern Length Bit 0 (RPL0). Refer to Table 15-2 for details.
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Repetitive Pattern Length Configuration
RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6 bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101).
Table 15-2: Repetitive Pattern Length Options
Length 17 Bits 18 Bits 19 Bits 20 Bits 21 Bits 22 Bits 23 Bits 24 Bits 25 Bits 26 Bits 27 Bits 28 Bits 29 Bits 30 Bits 31 Bits 32 Bits RPL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RPL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RPL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RPL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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BC2: BERT Control Register 2 (Address = 42 Hex)
(MSB) EIB2 SYMBOL EIB2 EIB1 EIB0 POSITION BC2.7 SBE - - - (LSB) TC
EIB1 EIB0 SBE - - - TC
BC2.6 BC2.5 BC2.4 BC2.3 BC2.2 BC2.1 BC2.0
NAME AND DESCRIPTION Error Insert Bit 2. Will automatically insert bit errors at the prescribed rate into the generated data pattern. Useful for verifying error detection operation. Refer to Table 15-3 for details. Error Insert Bit 1. Refer to Table 15-3 for details. Error Insert Bit 0. Refer to Table 15-3 for details. Single Bit Error Insert. A low to high transition will create a single bit error. Must be cleared and set again for a subsequent bit error to be inserted. Not Assigned. Should be set to 0 when written. Not Assigned. Should be set to 0 when written. Not Assigned. Should be set to 0 when written. Transmit Pattern Load. A low to high transition loads the pattern generator with the pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for a subsequent loads.
Table 15-3: BERT RATE INSERTION SELECT
EIB2 0 0 0 0 1 1 1 1 EIB1 0 0 1 1 0 0 1 1 EIB0 0 1 0 1 0 1 0 1 Error Rate Inserted No errors automatically inserted 10E-1 10E-2 10E-3 10E-4 10E-5 10E-6 10E-7
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BIR: BERT INFORMATION REGISTER (Address = 43 Hex)
(Refer to Section 7 for explanation of reading latched register bits) (MSB) - SYMBOL - RA1 RA0 RLOS RA1 RA0 POSITION BIR.7 BIR.6 BIR.5 BIR.4 RLOS BED BBCO BEC0 (LSB) SYNC
BED
BIR.3
BBCO
BIR.2
BECO
BIR.1
SYNC
BIR.0
NAME AND DESCRIPTION Not Assigned. Maybe any value when read. Receive All 1's (RA1). A latched bit which is set when 32 consecutive 1's are received. Allowed to be cleared once a 0 is received. Receive All Zeros (RA0). A latched bit which is set when 32 consecutive zeros are received. Allowed to be cleared once a 1 is received. Receive Loss Of Synchronization (RLOS). A latched bit which is set whenever the receive BERT begins searching for a pattern. Once synchronization is achieved, this bit will remain set until read. Bit Error Detected (BED). A latched bit which is set when a bit error is detected. The receive BERT must be in synchronization for it detect bit errors. Cleared when read. Can generate interrupts if enabled via IEBED (BC1.6). BERT Bit Counter Overflow (BBCO). A latched bit which is set when the 32-bit BERT Bit Counter (BBC) overflows. Cleared when read and will not be set again until another overflow occurs. Can generate interrupts if enabled via IEOF (BC1.5). BERT Error Counter Overflow (BECO). A latched bit which is set when the 24-bit BERT Error Counter (BEC) overflows. Cleared when read and will not be set again until another overflow occurs. Can generate interrupts if enabled via IEOF (BC1.5). Real Time Synchronization Status (SYNC). Real time status of the synchronizer (this bit is not latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will be cleared when 6 or more bits out of 64 are received in error. Can generate interrupts on change of state if enabled via IESYNC (BC1.7).
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BAWC: BERT Alternating Word Count Rate. (Address = 44 Hex)
(MSB) (LSB) ALTCNT7 ALTCNT6 ALTCNT5 ALTCNT4 ALTCNT3 ALTCNT2 ALTCNT1 ALTCNT0 SYMBOL ALTCNT7 ALTCNT6 ALTCNT5 ALTCNT4 ALTCNT3 ALTCNT2 ALTCNT1 ALTCNT0 POSITION BAWC.7 BAWC.6 BAWC.5 BAWC.4 BAWC.3 BAWC.2 BAWC.1 BAWC.0 NAME AND DESCRIPTION Alternating Word Count Rate Bit 7. (MSB) Alternating Word Count Rate Bit 6 . Alternating Word Count Rate Bit 5. Alternating Word Count Rate Bit 4. Alternating Word Count Rate Bit 3. Alternating Word Count Rate Bit 2. Alternating Word Count Rate Bit 1. Alternating Word Count Rate Bit 0. (LSB)
When the BERT is programmed in the alternating word mode, the words will repeat for the count loaded into this register then flip to the other word and again repeat for the number of times loaded into this register.
BRP0: BERT Repetitive Pattern Set Register 0 (Address = 45 Hex) BRP1: BERT Repetitive Pattern Set Register 1 (Address = 46 Hex) BRP2: BERT Repetitive Pattern Set Register 2 (Address = 47 Hex) BRP3: BERT Repetitive Pattern Set Register 3 (Address = 48 Hex)
(MSB) RPAT7 RPAT15 RPAT23 RPAT31 RPAT6 RPAT14 RPAT22 RPAT30 RPAT5 RPAT13 RPAT21 RPAT29 POSITION BERTRP3.7 BERTRP0.0 RPAT4 RPAT12 RPAT20 RPAT28 RPAT3 RPAT11 RPAT19 RPAT27 RPAT2 RPAT10 RPAT18 RPAT26 RPAT1 RPAT9 RPAT17 RPAT25 (LSB) RPAT0 RPAT8 RPAT16 RPAT24 BRP0 BRP1 BRP2 BRP3
SYMBOL RPAT31 RPAT0
NAME AND DESCRIPTION MSB of the 32-bit Repetitive Pattern Set LSB of the 32-bit Repetitive Pattern Set
BERT Repetitive Pattern Set. These registers must be properly loaded for the BERT to properly generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is less than 32 bits, then the pattern should be repeated so that all 32 bits are used to describe the pattern. For example if the pattern was the repeating 5-bit pattern ...01101... (where the right most bit is the one sent first and received first) then BRP0 should be loaded with ADh, BRP1 with B5h, BRP2 with D6h, and BRP3 should be loaded with 5Ah. For a pseudorandom pattern, all four registers should be loaded with all 1's (i.e. xFF). For an alternating word pattern, one word should be placed into BRP0 and BRP1 and the other word should be placed into BRP2 and BRP3. For example, if the DDS stress pattern "7E" is to be described, the user would place 00h in BRP0, 00h in BRP1, 7Eh in BRP2, and 7Eh in BRP3 and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be sent and received.
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BBC0: BERT Bit Count Register 0 (Address = 49 Hex) BBC1: BERT Bit Count Register 1 (Address = 4A Hex) BBC2: BERT Bit Count Register 2 (Address = 4B Hex) BBC3: BERT Bit Count Register 3 (Address = 4C Hex)
(MSB) BBC7 BBC15 BBC23 BBC31 BBC6 BBC14 BBC22 BBC30 BBC5 BBC13 BBC21 BBC29 POSITION BBC3.7 BBC0.0 BBC4 BBC12 BBC20 BBC28 BBC3 BBC11 BBC19 BBC27 BBC2 BBC10 BBC18 BBC26 BBC1 BBC9 BBC17 BBC25 (LSB) BBC0 BBC8 BBC16 BBC24 BBC0 BBC1 BBC2 BBC3
SYMBOL BBC31 BBC0
NAME AND DESCRIPTION MSB of the 32-bit Bit Counter LSB of the 32-bit Bit Counter
BERT Bit Counter (BBC0/ BBC1/ BBC2/ BBC3). Once BERT has achieved synchronization, this 32-bit counter will increment for each data bit (i.e. clock) received. Toggling the LC control bit in BC0 can clear this counter. This counter saturates when full and will set the BBCO status bit.
BEC0: BERT Error Count Register 0 (Address = 4D Hex) BEC1: BERT Error Count Register 1 (Address = 4E Hex) BEC2: BERT Error Count Register 2 (Address = 4F Hex)
(MSB) EC7 EC15 EC23 EC6 EC14 EC22 EC5 EC13 EC21 POSITION BEC2.7 BEC0.0 EC4 EC12 EC20 EC3 EC11 EC19 EC2 EC10 EC18 EC1 EC9 EC17 (LSB) EC0 EC8 EC16 BERTEC0 BERTEC1 BERTEC2
SYMBOL EC24 EC0
NAME AND DESCRIPTION MSB of the 24-bit Error Counter LSB of the 24-bit Error Counter
BERT Error Counter (BEC0/ BEC1/ BEC2). Once BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error. Toggling the LC control bit in BC0 can clear this counter. This counter saturates when full and will set the BECO status bit.
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BIC: BERT INTERFACE CONTROL REGISTER (Address = 50 Hex)
(MSB) - SYMBOL - RFUS RRCB RFUS RRCB POSITION BIC.7 BIC.6 BIC.5 RABS TBAT TFUS TTCB (LSB) TABS
RABS TBAT
BIC.4 BIC.3
TFUS TTCB
BIC.2 BIC.1
TABS
BIC.0
NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Receive Framed/Unframed Select. 0 = BERT will not be sent data from the F-bit position (framed) 1 = BERT will be sent data from the F-bit position (unframed) Receive RCHBLK Select. 0 = do not use RCHBLK to select which DS0 channels are to be routed to BERT 1 = use RCHBLK to select which DS0 channels are to be routed to BERT Receive Framer A or B Select. 0 = route data from framer A 1 = route data from framer B Transmit Byte Align Toggle. A 0 to 1 transition will force the BERT to byte align it's pattern with the transmit formatter. This bit must be transitioned in order to byte align the Daly Pattern. Transmit Framed/Unframed Select. 0 = BERT will not source data into the F-bit position (framed) 1 = BERT will source data into the F-bit position (unframed) Transmit TCHBLK Select. 0 = do not use TCHBLK to select which DS0 channels are to contain BERT data 1 = use TCHBLK to select which DS0 channels are to contain BERT data Transmit Formatter A or B Select. 0 = route data to formatter A 1 = route data to formatter B
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16.
ERROR INSERTION FUNCTION
An Error insertion function is available in each formatter of the DS2196 and is used to create errors in the payload portion of the T1 frame in the transmit path. See Figure 21-7 for location. Errors can be inserted over the entire frame or the user may select which channels are to be corrupted. Errors are created by inverting the last bit in the count sequence. For example if the error rate 1 in 16 is selected, the 16th bit is inverted. F-bits are excluded from the count and are never corrupted. Error rate changes occur on frame boundaries. Error insertion options include continuous and absolute number with both options supporting selectable insertion rates. Transmit error insertion setup guideline. 1. 2A. or 2B. Enter desired error rate in the ERC register. Refer to table 16-1 for available rates. Note: If ER3:0 = 0, no errors will be generated even if the constant error insertion feature is enabled. For constant error insertion set CE = 1 (ERC.4). For a defined number of errors: - Set CE = 0 (ERC.4) - Load NOE1 & NOE 2 with the number of errors to be inserted - Toggle WNOE (ERC.7) from 0 to 1, to begin error insertion
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ERCA: ERROR RATE CONTROL REGISTER FRAMER A (Address = 80 Hex) ERCB: ERROR RATE CONTROL REGISTER FRAMER A (Address = 85 Hex)
(MSB) WNOE SYMBOL WNOE RNOE TCBE POSITION ERC.7 CE ER3 ER2 ER1 (LSB) ER0
RNOE
ERC.6
TCBE
ERC.5
NAME AND DESCRIPTION Write NOE Registers. If the Host wishes to update to the NOE registers, this bit must be toggled from a 0 to a 1 after the Host has already loaded the prescribed error count into the NOE registers. The toggling of this bit causes the error count loaded into the NOE registers to be loaded into the error insertion circuitry on the next clock cycle. Subsequent updates require that the WNOE bit be set to 0 and then 1 once again. Read RNOEL Registers. If the Host wishes to obtain the latest count of the number of errors left to be inserted by the error insertion function, then this bit must be toggled from a 0 to a 1. Subsequent reads require that the RNOE bit be set to 0 and then 1 once again. The Host must wait at least 972 ns (1.5 clock periods) after toggling this bit to read the NOEL registers. The Host may read the NOEL registers at any time but they will contain either the count of errors left to be inserted (after toggling the RNOE bit) or the count of the number of errors that the Host has loaded (after writing to the NOE registers). TCHBLK Enable. This bit determines whether the TCHBLK signal should be used to "block" certain channels from being corrupted. When TCBE is set high, then the error insertion logic will not corrupt DS0 channels in which the TCHBLK signal has be programmed high. 0 = all the error insertion logic to corrupt all DS0 channels 1 = allow the error insertion logic to only corrupt the DS0 channels determined by the TCHBLK signal Constant Errors. When this bit is set high (and the ER0 to ER3 bits are not set to 0000), the error insertion logic will ignore the Number Of Error registers (NOE1A, NOE2A, NOE1B, and NOE2B) and generate errors constantly at the selected insertion rate. When CE is set to 0, the NOE registers determine how many errors are to be inserted. Error Rate Bit 3. Refer to Table 16-1 for details. Error Rate Bit 2. Refer to Table 16-1 for details. Error Rate Bit 1. Refer to Table 16-1 for details. Error Rate Bit 0. Refer to Table 16-1 for details.
CE
ERC.4
ER3 ER2 ER1 ER0
ERC.3 ERC.2 ERC.1 ERC.0
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Table 16-1: Error Rate Options
ER3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ER2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ER1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ER0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Error Rate No errors inserted 1 in 16 1 in 32 1 in 64 1 in 128 1 in 256 1 in 512 1 in 1024 1 in 2048 1 in 4096 1 in 8192 1 in 16384 1 in 32768 1 in 65536 1 in 131072 1 in 262144
NOE1A: NUMBER of ERRORS 1 FRAMER A (Address = 81 Hex) NOE1B: NUMBER of ERRORS 1 FRAMER B (Address = 86 Hex) NOE2A: NUMBER of ERRORS 2 FRAMER A (Address = 82 Hex) NOE2B: NUMBER of ERRORS 2 FRAMER B (Address = 87 Hex)
(MSB) C7 - SYMBOL C9 C0 C6 - C5 - POSITION NOE2.1 NOE1.0 C4 - C3 - C2 - C1 C9 (LSB) C0 C8 NOE1 NOE2
NAME AND DESCRIPTION MSB of the 10-bit Number of Errors Counter LSB of the 10-bit Number of Errors Counter
Number Of Errors Registers. The Number Of Error registers determines how many errors will be generated. Up to 1023 errors can be generated. The Host will load the number of errors to be generated into the NOE registers. The Host can also update the number of errors to be created by first loading the prescribed value into the NOE registers and then toggling the WNOE bit in the Error Rate Control registers. Refer to Table 16-2 for examples.
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Table 16-2: Error Insertion examples
Value Write 000h do not create any errors 001h create a single error 002h create 2 errors 3FFh create 1023 errors Read no errors left to be inserted 1 error left to be inserted 2 errors left to be inserted 1023 errors left to be inserted
NOEL1A: NUMBER of ERRORS LEFT 1 FRAMER A (Address = 83 Hex) NOEL1B: NUMBER of ERRORS LEFT 1 FRAMER B (Address = 88 Hex) NOEL2A: NUMBER of ERRORS LEFT 2 FRAMER A (Address = 84 Hex) NOEL2B: NUMBER of ERRORS LEFT 2 FRAMER B (Address = 89 Hex)
(MSB) C7 - SYMBOL C9 C0 C6 - C5 - POSITION NOEL2.1 NOEL1.0 C4 - C3 - C2 - C1 C9 (LSB) C0 C8 NOEL1 NOEL2
NAME AND DESCRIPTION MSB of the 10-bit Number of Errors Left Counter LSB of the 10-bit Number of Errors Left Counter
Number Of Errors Left Registers. The Host can read the NOEL registers at any time (to determine how many errors are left to be inserted) by toggling the RNOE bit in the Error Rate Control registers (ERCA and ERCB) from a 0 to a 1. After the RNOE bit is toggled, the Host may read the NOEL registers after waiting at least 972 ns (1.5 clock periods).
17.
HDLC CONTROLLER
The DS2196 has an enhanced HDLC controller configurable for use with the Facilities Data Link or DS0s. There are 64 byte buffers in both the transmit and receive paths. The user can select any DS0 or multiple DS0s as well as any specific bits within the DS0(s) to pass through the HDLC controller. See Figure 21-7 for details on formatting the transmit side. Note that TBOC.6 = 1 and TDC1.7 = 1 cannot exist without corrupting the data in the FDL. For use with the FDL, see section 18. See Table 17-1 for configuring the transmit HDLC controller.
Table 17-1: TRANSMIT HDLC CONFIGURATION
Function DS0(s) FDL Disable TBOC.6 0 1 0 TDC1.7 1 0 0 TCR1.2 1 or 0 1 1 or 0
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Four new registers were added for the enhanced functionality of the HDLC controller; RDC1, RDC2, TDC1, and TDC2. Note that the BOC controller is functional when the HDLC controller is used for DS0s. Section 18 contains all of the HDLC and BOC registers and information on FDL/Fs Extraction and Insertion with and without the HDLC controller.
17.1 HDLC FOR DS0S
When using the HDLC controllers for DS0s, the same registers shown in section 18 will be used except for the TBOC and RBOC registers and bits HCR.7, HSR.7, and HIMR.7. As a basic guideline for interpreting and sending HDLC messages and BOC messages, the following sequences can be applied.
Receive a HDLC Message
1. 2. 3. 4. Enable RPS interrupts Wait for interrupt to occur Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt Read RHIR to obtain REMPTY status a. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO a1. if CBYTE=0 then skip to step 5 a2. if CBYTE=1 then skip to step 7 b. If REMPTY=1, then skip to step 6 Repeat step 4 Wait for interrupt, skip to step 4 If POK=0, then discard whole packet, if POK=1, accept the packet Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
5. 6. 7. 8.
Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register 2. Enable either the THALF or TNF interrupt 3. Read THIR to obtain TFULL status a. If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to step 6) b. If TFULL=1, then skip to step 5 4. Repeat step 3 5. Wait for interrupt, skip to step 3 6. Disable THALF or TNF interrupt and enable TMEND interrupt 7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
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18.
FDL/Fs EXTRACTION AND INSERTION
Each Framer/Formatter has the ability to extract/insert data from/ into the Facility Data Link (FDL) in the ESF framing mode and from/into Fs-bit position in the D4 framing mode. Since SLC-96 utilizes the Fs-bit position, this capability can also be used in SLC-96 applications. The DS2196 contains a complete HDLC and BOC controller for the FDL and this operation is covered in Section 18.1. To allow for backward compatibility between the DS2196 and earlier devices, the DS2196 maintains some legacy functionality for the FDL and this is covered in Section 18.2. Section 18.3 covers D4 and SLC-96 operation. Please contact the factory for a copy of C language source code for implementing the FDL on the DS2196.
18.1 HDLC AND BOC CONTROLLER FOR THE FDL 18.1.1 General Overview
The DS2196 contains a complete HDLC controller with 64-byte buffers in both the transmit and receive directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC controller performs all the necessary overhead for generating and receiving Performance Report Messages (NPRMs and SPRMs) as described in ANSI T1.403-1998 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the HDLC data stream. The 64-byte buffers in the HDLC controller are large enough to allow a full NPRM or SPRM to be received or transmitted without host intervention. The BOC controller will automatically detect incoming BOC sequences and alert the host. When the BOC ceases, the DS2196 will also alert the host. The user can set the device up to send any of the possible 6-bit BOC codes. There are thirteen registers that the host will use to operate and control the operation of the HDLC and BOC controllers. A brief description of the registers is shown in Table 18-1.
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Table 18-1: HDLC/BOC CONTROLLER REGISTER LIST
NAME HDLC Control Register (HCR) HDLC Status Register (HSR) HDLC Interrupt Mask Register (HIMR) Receive HDLC Information Register (RHIR) Receive BOC Register (RBOC) Receive HDLC FIFO Register (RHFR) Receive HDLC DS0 Control Register 1 (RDC1) Receive HDLC DS0 Control Register 2 (RDC2) Transmit HDLC Information Register (THIR) Transmit BOC Register (TBOC) Transmit HDLC FIFO Register (THFR) Transmit HDLC DS0 Control Register 1 (TDC1) Transmit HDLC DS0 Control Register 2 (TDC2) FUNCTION general control over the HDLC and BOC controllers key status information for both transmit and receive directions allows/stops status bits to/from causing an interrupt status information on receive HDLC controller status information on receive BOC controller access to 64-byte HDLC FIFO in receive direction controls the HDLC function when used on DS0 channels
status information on transmit HDLC controller enables/disables transmission of BOC codes access to 64-byte HDLC FIFO in transmit direction controls the HDLC function when used on DS0 channels
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18.1.2 STATUS REGISTER FOR THE HDLC
Four of the HDLC/BOC controller registers (HSR, RHIR, RBOC, and THIR) provide status information. When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a 1. Some of the bits in these four HDLC status registers are latched and some are real time bits that are not latched. Section 18.1.4 contains register descriptions that list which bits are latched and which are not. With the latched bits, when an event occurs and a bit is set to a 1, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other status registers in the DS2196, the user will always proceed a read of any of the four registers with a write. The byte written to the register will inform the DS2196 which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register will be updated with current value and it will be cleared. When a 0 is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write (for polled driven access) or write-read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2196 with higher-order software languages. Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT pin low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
18.1.3 Basic Operation Details
To allow the framer to properly source/receive data from/to the HDLC and BOC controller the legacy FDL circuitry (which is described in Section 18.2) should be disabled and the following bits should be programmed as shown: TCR1.2 = 1 (source FDL data from the HDLC and BOC controller) TBOC.6 = 1 (enable HDLC and BOC controller) CCR2.5 = 0 (disable SLC-96 and D4 Fs-bit insertion) CCR2.4 = 0 (disable legacy FDL zero stuffer) CCR2.1 = 0 (disable SLC-96 reception) CCR2.0 = 0 (disable legacy FDL zero stuffer) IMR2.4 = 0 (disable legacy receive FDL buffer full interrupt) IMR2.3 = 0 (disable legacy transmit FDL buffer empty interrupt) IMR2.2 = 0 (disable legacy FDL match interrupt) IMR2.1 = 0 (disable legacy FDL abort interrupt). As a basic guideline for interpreting and sending both HDLC messages and BOC messages, the following sequences can be applied:
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Receive a HDLC Message or a BOC
Enable RBOC and RPS interrupts Wait for interrupt to occur If RBOC=1, then follow steps 5 and 6 If RPS=1, then follow steps 7 through 12 If LBD=1, a BOC is present, then read the code from the RBOC register and take action as needed If BD=0, a BOC has ceased, take action as needed and then return to step 1 Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt Read RHIR to obtain REMPTY status a. if REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO a1. if CBYTE=0 then skip to step 9 a2. if CBYTE=1 then skip to step 11 b. if REMPTY=1, then skip to step 10 9. Repeat step 8 10. Wait for interrupt, skip to step 8 11. If POK=0, then discard whole packet, if POK=1, accept the packet 12. disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1. 1. 2. 3. 4. 5. 6. 7. 8.
Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register 2. Enable either the THALF or TNF interrupt 3. Read THIR to obtain TFULL status a. if TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to step 6) b. if TFULL=1, then skip to step 5 4. Repeat step 3 5. Wait for interrupt, skip to step 3 6. Disable THALF or TNF interrupt and enable TMEND interrupt 7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
Transmit a BOC
1. Write 6-bit code into TBOC 2. Set SBOC bit in TBOC=1
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18.1.4 HDLC/BOC Register Description HCRA: HDLC CONTROL REGISTER FRAMER A (Address = 00 Hex) HCRB: HDLC CONTROL REGISTER FRAMER B (Address = A0 Hex)
(MSB) RBR SYMBOL RBR RHR TFS THR TABT RHR TFS POSITION HCR.7 HCR.6 HCR.5 HCR.4 HCR.3 THR TABT TEOM TZSD (LSB) TCRCD
TEOM
HCR.2
TZSD TCRCD
HCR.1 HCR.0
NAME AND DESCRIPTION Receive BOC Reset. A 0 to 1 transition will reset the BOC circuitry. Must be cleared and set again for a subsequent reset. Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset. Transmit Flag/Idle Select. 0 = 7Eh 1 = FFh Transmit HDLC Reset. A 0 to 1 transition will reset both the HDLC controller and the transmit BOC circuitry. Must be cleared and set again for a subsequent reset. Transmit Abort. A 0 to 1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Transmit End of Message. Should be set to a 1 just before the last data byte of a HDLC packet is written into the transmit FIFO at THFR. The HDLC controller will clear this bit when the last byte has been transmitted. Transmit Zero Stuffer Defeat. Overrides internal enable. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Transmit CRC Defeat. 0 = enable CRC generation (normal operation) 1 = disable CRC generation
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HSRA: HDLC STATUS REGISTER FRAMER A (Address = 01 Hex) HSRB: HDLC STATUS REGISTER FRAMER B (Address = A1 Hex)
(MSB) RBOC SYMBOL RBOC RPE RPS POSITION HSR.7 RHALF RNE THALF TNF (LSB) TMEND
RPE
HSR.6
RPS RHALF RNE THALF TNF TMEND
HSR.5 HSR.4 HSR.3 HSR.2 HSR.1 HSR.0
NAME AND DESCRIPTION Receive BOC Detector Change of State. Set whenever the BOC detector sees a change of state from a BOC Detected to a No Valid Code seen or vice versa. The setting of this bit prompt the user to read the RBOC register for details. Receive Packet End. Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. The setting of this bit prompts the user to read the RHIR register for details. Receive Packet Start. Set when the HDLC controller detects an opening byte. The setting of this bit prompts the user to read the RHIR register for details. Receive FIFO Half Full. Set when the receive 64-byte FIFO fills beyond the half waypoint. The setting of this bit prompts the user to read the RHIR register for details. Receive FIFO Not Empty. Set when the receive 64-byte FIFO has at least one byte available for a read. The setting of this bit prompts the user to read the RHIR register for details. Transmit FIFO Half Empty. Set when the transmit 64-byte FIFO empties beyond the half waypoint. The setting of this bit prompts the user to read the THIR register for details. Transmit FIFO Not Full. Set when the transmit 64-byte FIFO has at least one byte available. The setting of this bit prompts the user to read the THIR register for details. Transmit Message End. Set when the transmit HDLC controller has finished sending a message. The setting of this bit prompts the user to read the THIR register for details.
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
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HIMRA: HDLC INTERRUPT MASK REGISTER FRAMER A (Address = 02 Hex) HIMRB: HDLC INTERRUPT MASK REGISTER FRAMER B (Address = A2 Hex)
(MSB) RBOC SYMBOL RBOC RPE RPS RHALF RNE THALF TNF TMEND RPE RPS POSITION HIMR.7 HIMR.6 HIMR.5 HIMR.4 HIMR.3 HIMR.2 HIMR.1 HIMR.0 RHALF RNE THALF TNF (LSB) TMEND
NAME AND DESCRIPTION Receive BOC Detector Change of State. 0 = interrupt masked 1 = interrupt enabled Receive Packet End. 0 = interrupt masked 1 = interrupt enabled Receive Packet Start. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Half Full. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Not Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Half Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Not Full. 0 = interrupt masked 1 = interrupt enabled Transmit Message End. 0 = interrupt masked 1 = interrupt enabled
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RHIRA: RECEIVE HDLC INFORMATION REGISTER FRAMER A (Address = 03 Hex) RHIRB: RECEIVE HDLC INFORMATION REGISTER FRAMER B (Address = A3 Hex)
(MSB) RABT SYMBOL RABT RCRCE ROVR RVM REMPTY POK RCRCE ROVR POSITION RHIR.7 RHIR.6 RHIR.5 RHIR.4 RHIR.3 RHIR.2 RVM REMPTY POK CBYTE (LSB) OBYTE
CBYTE OBYTE
RHIR.1 RHIR.0
NAME AND DESCRIPTION Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more 1's in a row. CRC Error. Set when the CRC checksum is in error. Overrun. Set when the HDLC controller has attempted to write a byte into an already full receive FIFO. Valid Message. Set when the HDLC controller has detected and checked a complete HDLC packet. Empty. A real-time bit that is set high when the receive FIFO is empty. Packet OK. Set when the byte available for reading in the receive FIFO at RHFR is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the CRC was correct). Closing Byte. Set when the byte available for reading in the receive FIFO at RHFR is the last byte of a message (whether the message was valid or not). Opening Byte. Set when the byte available for reading in the receive FIFO at RHFR is the first byte of a message.
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
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RBOCA: RECEIVE BIT ORIENTED CODE REGISTER FRAMER A (Address = 04 Hex) RBOCB: RECEIVE BIT ORIENTED CODE REGISTER FRAMER B (Address = A4 Hex)
(MSB) LBD SYMBOL LBD BD BOC5 BOC4 BOC3 BOC2 BOC1 BOC0 BD BOC5 POSITION RBOC.7 RBOC.6 RBOC.5 RBOC.4 RBOC.3 RBOC.2 RBOC.1 RBOC.0 BOC4 BOC3 BOC2 BOC1 (LSB) BOC0
NAME AND DESCRIPTION Latched BOC Detected. A latched version of the BD status bit (RBOC.6). Will be cleared when read. BOC Detected. A real-time bit that is set high when the BOC detector is presently seeing a valid sequence and set low when no BOC is currently being detected. BOC Bit 5. Last bit received of the 6-bit code word. BOC Bit 4. BOC Bit 3. BOC Bit 2. BOC Bit 1. BOC Bit 0. First bit received of the 6-bit code word.
NOTE:
1. The LBD bit is latched and will be cleared when read. 2. The RBOC0 to RBOC5 bits display the last valid BOC code verified; these bits will be set to all 1's on reset.
RHFRA: RECEIVE HDLC FIFO from FRAMER A (Address = 05 Hex) RHFRB: RECEIVE HDLC FIFO from FRAMER B (Address = A5 Hex)
(MSB) HDLC7 SYMBOL HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 HDLC6 HDLC5 POSITION RHFR.7 RHFR.6 RHFR.5 RHFR.4 RHFR.3 RHFR.2 RHFR.1 RHFR.0 HDLC4 HDLC3 HDLC2 HDLC1 (LSB) HDLC0
NAME AND DESCRIPTION HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte.
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THIRA: TRANSMIT HDLC INFORMATION for FORMATTER A (Address = 06 Hex) THIRB: TRANSMIT HDLC INFORMATION for FORMATTER B (Address = A6 Hex)
(MSB) - SYMBOL - - - - - TEMPTY TFULL TUDR - - POSITION THIR.7 THIR.6 THIR.5 THIR.4 THIR.3 THIR.2 THIR.1 THIR.0 - - TEMPTY TFULL (LSB) TUDR
NAME AND DESCRIPTION Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Transmit FIFO Empty. A real-time bit that is set high when the FIFO is empty. Transmit FIFO Full. A real-time bit that is set high when the FIFO is full. Transmit FIFO Underrun. Set when the transmit FIFO unwantedly empties out and an abort is automatically sent.
NOTE:
The TUDR bit is latched and will be cleared when read.
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TBOCA: TRANSMIT BIT ORIENTED CODE for FORMATTER A (Address = 07 Hex) TBOCB: TRANSMIT BIT ORIENTED CODE for FORMATTER B (Address = A7 Hex)
(MSB) SBOC SYMBOL SBOC HBEN HBEN BOC5 POSITION TBOC.7 TBOC.6 BOC4 BOC3 BOC2 BOC1 (LSB) BOC0
BOC5 BOC4 BOC3 BOC2 BOC1 BOC0
TBOC.5 TBOC.4 TBOC.3 TBOC.2 TBOC.1 TBOC.0
NAME AND DESCRIPTION Send BOC. Rising edge triggered. Must be transitioned from a 0 to a 1 transmit the BOC code placed in the BOC0 to BOC5 bits instead of data from the HDLC controller. Transmit HDLC & BOC Controller Enable. 0 = source FDL data from the TLINK pin 1 = source FDL data from the onboard HDLC and BOC controller BOC Bit 5. Last bit transmitted of the 6-bit code word. BOC Bit 4. BOC Bit 3. BOC Bit 2. BOC Bit 1. BOC Bit 0. First bit transmitted of the 6-bit code word.
THFRA: TRANSMIT HDLC FIFO for FORMATTER A (Address = 08 Hex) THFRB: TRANSMIT HDLC FIFO for FORMATTER B (Address = A8 Hex)
(MSB) HDLC7 SYMBOL HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 HDLC6 HDLC5 POSITION THFR.7 THFR.6 THFR.5 THFR.4 THFR.3 THFR.2 THFR.1 THFR.0 HDLC4 HDLC3 HDLC2 HDLC1 (LSB) HDLC0
NAME AND DESCRIPTION HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte.
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RDC1A: RECEIVE HDLC DS0 CONTROL REGISTER 1 FRAMER A (Address = 90 Hex) RDC1B: RECEIVE HDLC DS0 CONTROL REGISTER 1 FRAMER B (Address = 94 Hex)
(MSB) RDS0E SYMBOL RDS0E RDS0M RDS0M POSITION RDC1.7 RDC1.6 RDC1.5 RD4 RD3 RD2 RD1 (LSB) RD0
RD4 RD3 RD2 RD1 RD0
RDC1.4 RDC1.3 RDC1.2 RDC1.1 RDC1.0
NAME AND DESCRIPTION HDLC DS0 Enable. 0 = use receive HDLC controller for the FDL. 1 = use receive HDLC controller for one or more DS0 channels. Not Assigned. Should be set to 0. DS0 Selection Mode. 0 = utilize the RD0 to RD4 bits to select which single DS0 channel to use. 1 = utilize the RCHBLK control registers to select which DS0 channels to use. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select.
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RDC2A: RECEIVE HDLC DS0 CONTROL REGISTER 2 FRAMER A (Address = 91 Hex) RDC2B: RECEIVE HDLC DS0 CONTROL REGISTER 2 FRAMER B (Address = 95 Hex)
(MSB) RDB8 SYMBOL RDB8 RDB7 RDB6 RDB5 RDB4 RDB3 RDB2 RDB1 RDB7 RDB6 POSITION RDC2.7 RDC2.6 RDC2.5 RDC2.4 RDC2.3 RDC2.2 RDC2.1 RDC2.0 RDB5 RDB4 RDB3 RDB2 (LSB) RDB1
NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to 1 to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 5 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 4 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 3 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to 1 to stop this bit from being used.
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TDC1A: TRANSMIT HDLC DS0 CONTROL REGISTER 1 FRAMER A (Address = 92 Hex) TDC1B: TRANSMIT HDLC DS0 CONTROL REGISTER 1 FRAMER B (Address = 96 Hex)
(MSB) TDS0E SYMBOL TDS0E TDS0M TDS0M POSITION TDC1.7 TDC1.6 TDC1.5 TD4 TD3 TD2 TD1 (LSB) TD0
TD4 TD3 TD2 TD1 TD0
TDC1.4 TDC1.3 TDC1.2 TDC1.1 TDC1.0
NAME AND DESCRIPTION HDLC DS0 Enable. 0 = use transmit HDLC controller for the FDL. 1 = use transmit HDLC controller for 1 or more DS0 channels. Not Assigned. Should be set to 0. DS0 Selection Mode. 0 = utilize the TD0 to TD4 bits to select which single DS0 channel to use. 1 = utilize the TCHBLK control registers to select which DS0 channels to use. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select.
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TDC2A: TRANSMIT HDLC DS0 CONTROL REGISTER 2 FRAMER A (Address = 93 Hex) TDC2B: TRANSMIT HDLC DS0 CONTROL REGISTER 2 FRAMER B (Address = 97 Hex)
(MSB) TDB8 SYMBOL TDB8 TDB7 TDB6 TDB5 TDB4 TDB3 TDB2 TDB1 TDB7 TDB6 POSITION TDC2.7 TDC2.6 TDC2.5 TDC2.4 TDC2.3 TDC2.2 TDC2.1 TDC2.0 TDB5 TDB4 TDB3 TDB2 (LSB) TDB1
NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to 1 to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 5 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 4 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 3 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to 1 to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to 1 to stop this bit from being used.
18.2 LEGACY FDL SUPPORT 18.2.1 Overview
The DS2196 maintains the circuitry that existed in the previous generation of Dallas Semiconductor's single chip transceivers and quad framers. Section 18.2 covers the circuitry and operation of this legacy functionality. In new applications, it is recommended that the HDLC controller and BOC controller described in Section 18.1 be used. On the receive side, it is possible to have both the new HDLC/BOC controller and the legacy hardware working at the same time. However this is not possible on the transmit side since there can be only one source the of the FDL data internal to the device.
18.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The framer will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the RMTCH1 or RMTCH2 registers, then the SR2.2 bit will be set to a 1 and the INT pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern until an important event occurs. The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than five 1's should be transmitted in a row so that the data does not resemble an
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opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2196 will automatically look for five 1's in a row, followed by a 0. If it finds such a pattern, it will automatically remove the zero. If the zero destuffer sees six or more 1's in a row followed by a 0, the 0 is not removed. The CCR2.0 bit should always be set to a 1 when the DS2196 is extracting the FDL. More on how to use the DS2196 in FDL applications in this legacy support mode is covered in a separate Application Note.
RFDLA: RECEIVE FDL REGISTER from FRAMER A (Address = 28 Hex) RFDLB: RECEIVE FDL REGISTER from FRAMER B (Address = C8 Hex)
(MSB) RFDL7 SYMBOL RFDL7 RFDL0 RFDL6 RFDL5 POSITION RFDL.7 RFDL.0 RFDL4 RFDL3 RFDL2 RFDL1 (LSB) RFDL0
NAME AND DESCRIPTION MSB of the Received FDL Code LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first.
RMTCH1A: RECEIVE FDL MATCH REGISTER 1 FRAMER A (Address = 29 Hex) RMTCH2A: RECEIVE FDL MATCH REGISTER 2 FRAMER A (Address = 2A Hex) RMTCH1B: RECEIVE FDL MATCH REGISTER 1 FRAMER B (Address = C9 Hex) RMTCH2B: RECEIVE FDL MATCH REGISTER 2 FRAMER B (Address = CA Hex)
(MSB) RMFDL7 RMFDL6 RMFDL5 RMFDL4 RMFDL3 RMFDL2 RMFDL1 (LSB) RMFDL0
POSITION NAME AND DESCRIPTION RMTCH1A.7 MSB of the FDL Match Code RMTCH2A.7 RMTCH1B.7 RMTCH2B.7 RMFDL0 RMTCH1A.0 LSB of the FDL Match Code RMTCH2A.0 RMTCH1B.0 RMTCH2B.0 When the byte in the Receive FDL Register matches either of the two Receive Match Registers (RMTCH1/RMTCH2), SR2.2 will be set to a 1 and the INT will go active if enabled via IMR2.2.
SYMBOL RMFDL7
18.2.3 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
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is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full 8 bits has been shifted out, the framer will signal the host microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The INT will also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. The framer also contains a zero stuffer, which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than five 1's should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically look for five 1's in a row. If it finds such a pattern, it will automatically insert a 0 after the five 1's. The CCR2.0 bit should always be set to a 1 when the framer is inserting the FDL. More on how to use the DS2196 in FDL applications is covered in a separate Application Note.
TFDLA: TRANSMIT FDL REGISTER for FORMATTER A (Address = 7E Hex) TFDLB: TRANSMIT FDL REGISTER for FORMATTER B (Address = FE Hex)
[Also used to insert Fs framing pattern in D4 framing mode; see Section 18.3] (MSB) TFDL7 SYMBOL TFDL7 TFDL0 TFDL6 TFDL5 POSITION TFDL.7 TFDL.0 TFDL4 TFDL3 TFDL2 TFDL1 (LSB) TFDL0
NAME AND DESCRIPTION MSB of the FDL code to be transmitted LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
18.3 D4/SLC-96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to 1Ch and the following bits must be programmed as shown: TCR1.2=0 (source Fs data from the TFDL register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries) Since the SLC-96 message fields share the Fs-bit position, the user can access the message fields via the TFDL and RFDL registers. Please see the separate Application Note for a detailed description of how to implement a SLC-96 function.
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19.
LINE INTERFACE FUNCTION
The line interface function in the DS2196 contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which wave shapes and drives the T1 line, and (3) the jitter attenuator. Each of these three sections is controlled by the Line Inter-face Control Register (LICR) which is described below.
LICR: LINE INTERFACE CONTROL REGISTER FRAMER A (Address = 7C Hex)
(MSB) LBOS2 SYMBOL LBOS2 LBOS1 LBOS0 EGL LBOS1 LBOS0 POSITION LICR.7 LICR.6 LICR.5 LICR.4 EGL JAS JABDS DJA (LSB) TPD
JAS JABDS DJA TPD
LICR.3 LICR.2 LICR.1 LICR.0
NAME AND DESCRIPTION Line Build Out Select Bit 2. Sets the transmitter build out; see the Table 19-1 Line Build Out Select Bit 1. Sets the transmitter build out; see the Table 19-1 Line Build Out Select Bit 0. Sets the transmitter build out; see the Table 19-1 Receive Equalizer Gain Limit. 0 = -36 dB 1 = -15 dB Jitter Attenuator Select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side Jitter Attenuator Buffer Depth Select. 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) Disable Jitter Attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled Transmit Power Down. 0 = normal transmitter operation 1 = powers down the transmitter and 3-states the TTIP and TRING pins
19.1 RECEIVE CLOCK AND DATA RECOVERY
The DS2196 contains a digital clock recovery system. See the DS2196 Block Diagram in Section 1 and Figure 19-1 for more details. The DS2196 couples to the receive T1 twisted pair via a 1:1 transformer. See Table 19-2 for transformer details. The 1.544 MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding jitter tolerance (see Figure 19-2).
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Normally, the clock that is output at the RCLKLO pin is the recovered clock from the T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive Carrier Loss (LRCL) condition will occur and the RCLKLO will be sourced from the clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLKLO output can exhibit slightly shorter high cycles of the clock. This is due to the highly over sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the Receive AC Timing Characteristics in Section 22 for more details.
19.2 TRANSMIT WAVESHAPING AND LINE DRIVING
The DS2196 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter (DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the DS2196 meet the latest ANSI, AT&T, and ITU specifications. See Figure 19-3. The user will select which waveform is to be generated by properly programming the LBOS3/LBOS2/LBOS1/LBOS0 bits in the Line Interface Control Register (LICR). The DS2196 can set up in a number of various configurations depending on the application. See Table 19-1 and Figure 19-1.
Table 19-1: LINE BUILD OUT SELECT IN LICR
LBO LBO LBO LBO S3 S2 S1 S0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 LINE BUILD OUT 0 to 133 feet/ 133 feet to 266 266 feet to 399 399 feet to 533 533 feet to 655 -7.5 dB -15 dB -22.5 dB Square Wave Output Open Drain Output Driver Enable APPLICATION DSX-1/0dB CSU DSX-1 DSX-1 DSX-1 DSX-1 CSU CSU CSU Custom Wave shape Custom Wave shape
NOTE:
LBOS3 is located at CCR7A.0. Due to the nature of the design of the transmitter in the DS2196, very little jitter (less then 0.005 UIpp broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLKLI. Also, the waveforms that they create are independent of the duty cycle of TCLKLI. The transmitter in the DS2196 couples to the T1 transmit twisted pair via a 1:2 step up transformer for the as shown in Figure 19-1. In order for the devices to create the proper waveforms, this transformer used must meet the specifications listed in Table 19-2.
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Table 19-2: TRANSFORMER SPECIFICATIONS
SPECIFICATION Turns Ratio Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device side) Secondary Receive Transformer DC Resistance Primary (Device side) Secondary RECOMMENDED VALUE 1:1(receive) and 1:2(transmit) 5% 600 mH minimum 1.0 mH maximum 40 pF maximum 1.0W maximum 2.0W maximum 1.2W maximum 1.2W maximum
19.3 JITTER ATTENUATOR
The DS2196 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Figure 19-4. The jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order for the jitter attenuator to operate properly, a 1.544 MHz clock (50 ppm) must be applied at the MCLK pin. Onboard circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLKLI pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/ bursty clock at the TCLKLI pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS2196 will divide the internal nominal 24.704 MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR3.5)
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Figure 19-1: EXTERNAL ANALOG CONNECTIONS
+3.3V Fuse
1uF D1 (nonpolarized)
D2
DS2196
TTIP
0.01uF 0.1uF
+3.3V
Rp
T1 Transmit Line
Fuse
Rp 2:1 (larger winding toward the network)
DVDD DVSS
0.1uF
S
C1
TRING RVDD
D4
D3
RVSS
0.1uF
10 uF Tant
TVDD
Fuse
Rp
470
TVSS RTIP RRING
T1 Receive Line
Fuse
Rp 1:1
470 50
0.1uF
50
MCLK
1.544MHz
Alternate Receive Interface Fuse
Rp
470
T1 Receive Line
Fuse
Rp
RTIP
100
RRING
1:1 0.1uF
470
NOTES:
1. 2. 3. 4. 5. 6. 7.
Resistor values are 1%. Circuit requires use of Schottky diodes for D1-D4. S is a 6V transient suppresser. C1 is 0.1 uF. The Rp resistors are used to prevent the fuses from opening during a surge. See the Separate Application Note for details on how to construct a protected interface. MCLK requires a TTL level 1.544 MHz clock (+50 ppm) for proper device operation.
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Figure 19-2: JITTER TOLERANCE
1K DS2196 Tolerance
UNIT INTERVALS (UIpp)
100
10 Mimimum Tolerance Level as per TR 62411 (Dec. 90)
1
0.1 1 10 100 1K FREQUENCY (Hz) 10K 100K
Figure 19-3: TRANSMIT WAVEFORM TEMPLATE
1.2
1.1
1.0 0.9 N O R M AL IZ E D A M PL IT U D E
MAXIMUM CURVE UI Time Amp. -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05
MINIMUM CURVE UI Time Amp. -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05
0.8
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -500 -400 -300 -200 -100 0 100 200 TIME (ns)
T1.102/87, T1.403, CB 119 (Oct. 79), & I.431 Template
300
400
500
600
700
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Figure 19-4: JITTER ATTENUATION
0dB
JITTER ATTENUATION (dB)
TR 62411 (Dec. 90) Prohibited Area
r Cu 6 tt Ji
2 DS
-20dB
19 er nu te At n io at
ve A
-40dB
Cu B rve
C ur ve
-60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K
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20.
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
20.1 DESCRIPTION
The DS2196 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP, and IDCODE. See Figure 20-1 for a block diagram. The DS2196 contains the following items, which meet the requirements, set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details.
Figure 20-1: BOUNDARY SCAN ARCHITECTURE
Boundary Scan Register Identification Register Bypass Register Instruction Register
MUX
Test Access Port Controller
+V 10K 10K +V 10K +V
Select Output Enable
JTDI
JTMS
JTCLK
JTRST
JTDO
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20.2 TAP CONTROLLER STATE MACHINE
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. Please see Figure 20.2 for details on each of the states described below.
TAP Controller
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
Test-Logic-Reset
Upon power up of the DS2196, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the DS2196 will operate normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and Test registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR
Capture-DR
Data may be parallel-loaded into the Test Data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test register will remain at its current value. On the rising edge of JTCLK, the controller will go to the ShiftDR state if JTMS is low or it will go to the Exit1-DR state if JTMS is high.
Shift-DR
The Test Data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK. If a Test Register selected by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR state, and terminate the scanning process. A rising edge on JTCLK with JTMS low will put the controller in the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All Test registers selected by the current instruction will retain their previous state. The controller will remain in this state while JTMS is low. A rising edge on JTCLK with JTMS high will put the controller in the Exit2-DR state.
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Exit2-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS low will enter the ShiftDR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the Test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle state. With JTMS high, the controller will enter the Select-DR-Scan state.
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the Instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state.
Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller will enter the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller will enter the Shift-IR state.
Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output. The parallel registers, as well as all Test registers remain at their previous states. A rising edge on JTCLK with JTMS high will move the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low will keep the controller in the Shift-IR state while moving data one stage thorough the instruction shift register.
Exit1-IR
A rising edge on JTCLK with JTMS low will put the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process.
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS high, a rising edge on JTCLK will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is low during a rising edge on JTCLK.
Exit2-IR
A rising edge on JTCLK with JTMS low will put the controller in the Update-IR state. The controller will loop back to Shift-IR if JTMS is high during a rising edge of JTCLK in this state.
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Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle state. With JTMS high, the controller will enter the Select-DR-Scan state.
Figure 20-2: TAP CONTROLLER STATE MACHINE
1 Test Logic Reset 0 Run Test/ Idle
0
1
Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0
1
Select IR-Scan 0 1 Capture IR 0
1
0 1
Shift IR 1 Exit IR 0
0 1
0 0
Pause IR 1 Exit2 IR 1 Update IR 1 0
0
20.3 INSTRUCTION REGISTER AND INSTRUCTIONS
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2IR state with JTMS high will move the controller to the Update-IR state The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS2196 with their respective operational binary codes are shown in Table 20-1.
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Table 20-1: Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture
Instruction SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE Selected Register Boundary Scan Bypass Boundary Scan Boundary Scan Boundary Scan Device Identification Instruction Codes 010 111 000 011 100 001
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the DS2196 can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS2196 to shift data into the boundary scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS2196. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device's normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test register is selected. The device identification code will be loaded into the Identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code will always have a `1' in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See Figure 20-3. Table 20-2 lists the device ID codes for the DS2196.
Table 20-2: ID CODE STRUCTURE
Contents Length MSB Version (Contact Factory) 4 bits LSB Device ID (See Table 20-3) 16 bits JEDEC "00010100001" 11 bits "1" 1 bit
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Table 20-3: DEVICE ID CODES
DEVICE DS2196 16-BIT NUMBER 0009 h
HIGHZ
All digital outputs of the DS2196 will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO.
CLAMP
All digital outputs of the DS2196 will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the DS2196 design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is 126 bits in length. Table 20-3 shows all of the cell bit locations and definitions.
Bypass Register
This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-LogicReset state.
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Table 20-4: BOUNDARY SCAN REGISTER DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SCAN REGISTER BIT 3 2 1 0 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SYMBOL PCLK PNRZ WCLK WNRZ JTMS JTCLK JTRST* JTDI JTDO RCL LNRZ LCLK LFSYNC RPOSLO RNEGLO RCLKLO BTS RTIP RRING RVDD RVSS INT* RVSS MCLK UOP3 UOP2 UOP1 UOP0 TTIP TVSS TVDD TRING TPOSLI TNEGLI TCLKLI TCHBLKB/ TLINKB CONTROL TCHBLKB/ TLINKB TCHCLKB/ TLCLKB TYPE I I I I I I I I O O O O O O O O I I I O I O O O O O O I I I I/O O CONTROL BIT DESCRIPTION
0 = TLINKB an input 1 = TCHBLKB an output
36 37
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PIN
SCAN REGISTER BIT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SYMBOL TSYNCB CONTROL TSYNCB TCLKB TSERB TPOSOB/ TNRZB TNEGOB / TFSYNCB TCLKOB DVSS DVDD TCLKOA TNEGOA / TFSYNCA TPOSOA / TNRZA TSERA TCLKA TSYNCA CONTROL TSYNCA TCHCLKA / TLCLKA TCHBLKA / TLINKA CONTROL TCHBLKA / TLINKA MUX BUS CONTROL D0 / AD0 D1 / AD1 D2 / AD2 D3 / AD3 D4 / AD4 D5 / AD5 D6 / AD6 D7 / AD7 DVSS DVDD A0 A1 A2 A3
TYPE I/O I I O O O O O O I I I/O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I I I I
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CONTROL BIT DESCRIPTION 0 = TSYNCB an input 1 = TSYNCB an output
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
0 = TSYNCA an input 1 = TSYNCA an output
0 = TLINKA an input 1 = TCHBLKA an output
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
0 = D0-D7/A0-A7 are inputs 1 = D0-D7/A0-A7 are outputs
DS2196
PIN 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
SCAN REGISTER BIT 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
SYMBOL A4 A5 A6 A7 / ALE RD*(DS*) CS* WR*(R/W*) RCHBLKA / RLINKA RCHCLKA / RLCLKA RCLKIA RPOSIA RNEGIA RCLKA RSERA RMSYNCA RFSYNCA RLOSA/ LOTCA RBPVA DVSS DVDD RBPVB RLOSB/ LOTCB RFSYNCB RMSYNCB RSERB RCLKB RNEGIB RPOSIB RCLKIB RCHCLKB / RLCLKB RCHBLKB / RLINKB WPS
TYPE I I I I I I I O O I I I O O O O O O O O O O O O I I I O O I
CONTROL BIT DESCRIPTION
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21.
TIMING DIAGRAMS
Figure 21-1: RECEIVE SIDE D4 TIMING
FRAME# RFSYNC RFSYNC
1
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
2
RMSYNC RLCLK RLINK
3
Notes: 1. RFSYNC double-wide frame sync is not enabled (RCR2.5 = 0) 2. RFSYNC double-wide frame sync is enabled (RCR2.5 = 1) 3. RLINK data (Fs - bits) is updated one bit prior to even frames and held for two frames
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Figure 21-2: RECEIVE SIDE ESF TIMING
FRAME# RFSYNC RFSYNC RMSYNC RLCLK
3 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22
23
24
2
RLINK RLCLK
4
5
RLINK
6
Notes: 1. RFSYNC double-wide frame sync is not enabled (RCR2.5 = 0) 2. RFSYNC double-wide frame sync is enabled (RCR2.5 = 1) 3. ZBTSI mode disabled (RCR2.6 = 0) 4. RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames 5. ZBTSI mode is enabled (RCR2.6 = 1) 6. RLINK data (Z bits) is updated one bit time before odd frames and held for four frames
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Figure 21-3: RECEIVE SIDE BOUNDARY TIMING
RCLK CHANNEL 23 RSER RFSYNC RMSYNC RLOS RBPV RCHCLK RCHBLK
3 1 LSB MSB
CHANNEL 24
LSB F MSB
CHANNEL 1
2
RLCLK RLINK
4
Notes: 1. RLOS transitions high during the F-bit time that caused an OOF event or when loss of carrier is detected. 2. RBPV transitions high when the bit in error emerges from RSER. If B8ZS is enabled, RBPV will not report the zero replacement code. 3. RCHBLK is programmed to block channel 24. 4. Shown is RLINK/RLCLK in the ESF framing mode
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DS2196
Figure 21-4: TRANSMIT SIDE D4 TIMING
FRAME# TSYNC1/ TFSYNC TSYNC TSYNC TLCLK TLINK
4 2
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
3
Notes: 1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0) 2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1) 3. TSYNC in the multiframe mode (TCR2.3 = 1) 4. TLINK data (Fs - bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled via TCR1.2
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Figure 21-5: TRANSMIT SIDE ESF TIMING
FRAME# TSYNC TSYNC TSYNC
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22
23
24
2
3
TLCLK TLINK
4
TLCLK TLINK
6
7
Notes: 1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0) 2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1) 3. TSYNC in the multiframe mode (TCR2.3 = 1) 4. ZBTSI mode disabled (TCR2.5 = 0) 5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if enabled via TCR1.2 6. ZBTSI mode is enabled (TCR2.5 = 1) 7. TLINK data (Z bits) is sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled via TCR1.2 8. TLINK and TLCLK are not synchronous with TFSYNC
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Figure 21-6: TRANSMIT SIDE BOUNDARY TIMING
TCLK CHANNEL 1 TSER TSYNC TSYNC
1 LSB F MSB LSB MSB
CHANNEL 2
LSB MSB
2
TCHCLK TCHBLK
3
TLCLK TLINK
4 Don't Care
Notes: 1. TSYNC is in the output mode (TCR2.2 = 1) 2. TSYNC is in the input mode (TCR2.2 = 0) 3. TCHBLK is programmed to block channel 4. Shown is TLINK/TLCLK in the ESF framing d
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Figure 21-7: TRANSMIT DATA FLOW
HDLC Controller TSER / TDATA
DS0 insertion enable (TDC1.7) DS2152 TRANSMIT DATA FLOW Figure 15.11 0 1
TCD1 (4:0) TCHBLK
0
TDC2
1
0
1 TDC1.5 IBCC TDR CCR3.1 1 1 TIR1 to TIR3 Idle Code / Per Channel LB 0 Software Signaling Insertion 1 0 TS1 to TS12 In-Band Loop Code Generator
TIR Function Select (CCR4.0) 0 TID R RSER (note#1)
Software Signaling Enable (TCR1.4)
CH 1-12 AIS Enable (CCR7.4) CH 13-24 AIS Enable (CCR7.5) TTR1 to TTR3 Global Bit 7 Stuffing (TCR1.3) Bit 7 Zero Suppression Enable (TCR2.0) BOC Controller TBOC.7 Frame Mode Select (CCR2.7) 0 TFDL Frame Mode Select (CCR2.7) D4 Yellow Alarm Select (TCR2.1) Transmit Yellow (TCR1.0)
C H 1 -1 2 & 1 3 -2 4 A IS E n a ble
Bit 7 Stuffing
D4 Bit 2 Yellow Alarm Insertion FPS or Ft Bit Insertion
TLINK
0
1 1 1 HDLC/BOC Enable (TBOC.6) F-Bit Pass Through (TCR1.6) TFDL Select (TCR1.2) 0 F-Bit Mux 1 FDL Mux
Frame Mode Select (CCR2.7) CRC Pass Through (TCR1.5)
CRC Insertion 0 CRC Mux 1
Frame Mode Select (CCR2.7) D4 Yellow Alarm Select (TCR2.1) Transmit Yellow (TCR1.0) Frame Mode Select (CCR2.7) Transmit Yellow (TCR1.0) BERT Function (Section 15)
D4 12th Fs Bit Yellow Alarm Gen. ESF Yellow Alarm Gen. (00FF Hex in the FDL)
CRC Calculation
KEY: = Register = Device Pin = Selector
BERT GENERATOR & DETECTOR
Error Rate Control (ERC) Number of Errors (NOE1, NOE2)
ERROR INSERTION FUNCTION
Transmit Blue (TCR1.1) B8ZS Enable (CCR2.6) NOTES: 1. TCLK should be tied to RCLK and TSYNC should be tied to RFSYNC for data to be properly sourced from RSER.
AMI or B8ZS Converter / Blue Alarm Gen. To Waveshaping, Filters, and Line Drivers
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Figure 21-8: RECEIVE DATA FLOW
RNEGI RPOSI
B8ZS Decoder 0 1 Receive Mark Code Insertion RCR2.7 Receive Code Select
Channel Enables
RMR1 to RMR3
CCR1.5
Signaling All Ones
SIGNALING EXTRACTION
RS1 to RS12
Receive Signaling
RSER
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22.
OPERATING PARAMETERS
-0.3V to +5.5V -0.3V to +3.63V 0C to +70C -40C to +85C -55C to +125C See J-STD-020A specification
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Lead with respect to VSS (except VDD) Supply voltage (VDD) with Respect to VSS Operating Temperature for DS2196L Operating Temperature for DS2196LN Storage Temperature Soldering Temperature
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0C to +70C for DS2196L) (-40C to +85C for DS2196LN)
PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 3.135 TYP MAX 5.5 +0.8 3.465 UNITS V V V NOTES
1
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 5 7 MAX UNITS pF pF
(tA =25C)
NOTES
DC CHARACTERISTICS (0C to +70C; VDD = 3.135 to 3.465V for DS2196L) (-40C to +85C; VDD = 3.135 to 3.465V for DS2196LN)
PARAMETER Supply Current @ 3.3V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) SYMBOL IDD IIL ILO IOH IOL MIN -1.0 -1.0 +4.0 TYP 85 MAX +1.0 10 UNITS mA A A mA mA NOTES 2 3 4
NOTES:
1. 2. 3. 4. Applies to RVDD, TVDD, and DVDD. TCLK=RCLK=MCLK=1.544 MHz; TTIP & TRING loaded, other outputs open circuited. 0.0V < VIN < VDD. Applied to INT when 3-stated.
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DS2196
AC CHARACTERISTICS - MULTIPLEXED PARALLEL PORT (MUX=1) (0C to +70C; VDD = 3.135 to 3.465V for DS2196L) (-40C to +85C; VDD = 3.135 to 3.465V for DS2196LN)
PARAMETER Cycle Time Pulse Width, DS low or RD* high Pulse Width, DS high or RD* low Input Rise/Fall times R/W* Hold Time R/W* Set Up time before DS high CS* Set Up time before DS, WR* or RD* active CS* Hold time Read Data Hold time Write Data Hold time MUX'd Address valid to AS or ALE fall Muxed Address Hold time Delay time DS, WR* or RD* to AS or ALE rise Pulse Width AS or ALE high Delay time, AS or ALE to DS, WR* or RD* Output Data Delay time from DS or RD* Data Set Up time SYMBOL tCYC pwEL pwEH tR , t F tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD pwASH tASED tDDR tDSW MIN 200 100 100 20 10 50 20 0 10 0 15 10 20 30 10 20 50 150 50 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
(See Figures 22-1 to 22-3 for details)
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DS2196
AC CHARACTERISTICS - NON-MULTIPLEXED PARALLEL PORT (MUX=0 ) (0C to +70C; VDD = 3.135 to 3.465V for DS2196L) (-40C to +85C; VDD = 3.135 to 3.465V for DS2196LN)
PARAMETER Set Up Time for A0 to A7 Valid to CS* Active Set Up Time for CS* Active to either RD*, WR*, or DS* Active Delay Time from either RD* or DS* Active to Data Valid Hold Time from either RD*, WR*, or DS* Inactive to CS* Inactive Hold Time from CS* Inactive to Data Bus 3- state Wait Time from either WR* or DS* Active to Latch Data Data Set Up Time to either WR* or DS* Inactive Data Hold Time from either WR* or DS* Inactive Address Hold from either WR* or DS* inactive SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 0 5 75 10 10 10 20 MIN 0 0 150 TYP MAX UNITS ns ns ns ns ns ns ns ns ns NOTES
See Figures 22-4 to 22-7 for details.
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DS2196
AC CHARACTERISTICS - RECEIVE SIDE (0C to +70C; VDD = 3.135 to 3.465V for DS2196L) (-40C to +85C; VDD = 3.135 to 3.465V for DS2196LN)
PARAMETER RCLKLO Period RCLKLO Pulse Width RCLKLO Pulse Width RCLKI Period RCLKI Pulse Width RPOSI/RNEGI Set UP to RCLKI Falling RPOSI/RNEGI Hold From RCLKI Falling RCLKI Rise and Fall Times Delay RCLKLO to RPOSLO, RNEGLO Valid Delay RCLK to RSER, RLINK Valid Delay RCLK to RCHCLK, RFSYNC, RMSYNC, RCHBLK, RLCLK Delay WCLK/PCLK to WNRZ, PNRZ SYMBOL tLP tLH tLL tLH tCL tCP tCH tCL tSU tHD tR , tF tDD tD1 tD2 tD3 MIN 250 250 200 200 75 75 20 20 25 50 50 50 50 TYP 648 324 324 324 324 648 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 1 1 2 2
See Figures 22-8 to 22-9 for details.
NOTES:
1. Jitter attenuator enabled in the receive path. 2. Jitter attenuator disabled in the receive path.
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DS2196
AC CHARACTERISTICS - TRANSMIT SIDE (0C to +70C; VDD = 3.135 to 3.465V for DS2196L) (-40C to +85C; VDD = 3.135 to 3.465V for DS2196LN)
PARAMETER TCLK Period TCLK Pulse Width TCLKLI Period TCLKLI Pulse Width TSYNC Set Up to TCLK falling TSYNC Pulse Width TSER, TLINK Set Up to TCLK Falling TPOSLI, TNEGLI Set Up to TCLKLI Falling TSER, TLINK Hold from TCLK Falling TPOSLI, TNEGLI Hold from TCLKLI Falling TCLK, TCLKI Rise and Fall Times Delay TCLKO to TPOSO, TNEGO Valid Delay TCLK to TCHBLK, TCHBLK, TSYNC, TLCLK See Figures 22-10 to 22-11 for details. SYMBOL MIN TYP tCP 648 tCH 75 tCL 75 tLP 648 tLH 75 75 tLL tSU 20 tPW tSU tSU tHD tHD tR , tF tDD tD2 50 20 20 20 20 25 50 50 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
t CH -5 or t SH -5
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DS2196
Figure 22-1: INTEL BUS READ AC TIMING (BTS=0 / MUX = 1)
t CYC ALE t ASD WR*
PWASH t ASED PWEH t CS t CH
t ASD PWEL
RD* CS*
t ASL AD0-AD7 t AHL
t DDR
t DHR
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DS2196
Figure 22-2: INTEL BUS WRITE TIMING (BTS=0 / MUX=1)
t CYC ALE t ASD RD*
PWASH t ASED PWEH t CS t CH
t ASD PWEL
WR* CS*
t ASL AD0-AD7 t AHL t DSW
t DHW
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DS2196
Figure 22-3: MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1)
PWASH AS t ASD DS PWEL t RWS R/W* AD0-AD7 (read) CS* AD0-AD7 (write) t ASL t AHL t DSW t DHW t ASL t AHL t DDR t CH t ASED t CYC t RWH PWEH
t DHR
t CS
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DS2196
Figure 22-4: INTEL BUS READ AC TIMING (BTS=0 / MUX=0)
A0 to A7 ADDRESS VALID
D0 to D7
DATA VALID t5
WR*
t1
CS*
t2
t3
t4
RD*
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DS2196
Figure 22-5: INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0)
A0 to A7 ADDRESS VALID
D0 to D7
t7 t1
t8
RD*
CS*
t2
t6
t4
WR*
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DS2196
Figure 22-6: MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0)
A0 to A7 ADDRESS VALID
DATA VALID D0 to D7 t5
R/W*
t1
CS*
t2
t3
t4
DS*
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Figure 22-7: MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0)
A0 to A7 ADDRESS VALID
D0 to D7 t8
R/W* t1 CS* t2 DS* t6
t7
t4
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Figure 22-8: RECEIVE SIDE AC TIMING
RCLK t D1 RSER t D2 RCHCLK t D2 RCHBLK t D2 RSYNC t D2 1 RLCLK t D1 RLINK
Notes: 1. Shown is RLINK/RLCLK in the ESF framing mode. 2. No relationship between RCHCLK and RCHBLK and the other signals is implied.
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DS2196
Figure 22-9: RECEIVE LINE INTERFACE AC TIMING
tR WCLK, PCLKI t SU WNRZ, PNRZ t HD t LL RCLKLO t DD RPOSLO, RNEGLO t LH t LP t CP tF t CL t CH
tR RCLKI
tF t SU
t CL
t CH t CP
RPOSI, RNEGI t HD
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DS2196
Figure 22-10: TRANSMIT SIDE AC TIMING
t CP tR TCLK t SU TSER t D2 TCHCLK TCHBLK t D2 TSYNC1 t SU TSYNC 2 5 TLCLK TLINK t SU t D2 t HD t HD t D2 t HD tF t CL t CH
Notes: 1. TSYNC is in the output mode (TCR2.2 = 1). 2. TSYNC is in the input mode (TCR2.2 = 0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. TLINK is only sampled during F-bit locations. 6. No relationship between TCHCLK and TCHBLK and the other signals is implied.
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DS2196
Figure 22-11: TRANSMIT LINE INTERFACE SIDE AC TIMING
TCLKO TPOSO, TNEGO
TFSYNC t DD tR TCLKLI t SU TPOSLI, TNEGLI t HD tF t LL t LP t LH
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23.
100-PIN LQFP PACKAGE SPECIFICATIONS
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