? 1999 fairchild semiconductor corporation ds010648 www.fairchildsemi.com february 1990 revised november 1999 100311 low skew 1:9 differential clock driver 100311 low skew 1:9 differential clock driver general description the 100311 contains nine low skew differential drivers, designed for generation of multiple, minimum skew differ- ential clocks from a single differential input (clkin, clkin ). if a single-ended input is desired, the v bb output pin may be used to drive the remaining input line. a high on the enable pin (en ) will force a low on all of the clk n outputs and a high on all of the clk n output pins. the 100311 is ideal for distributing a signal throughout a system without worrying about the original signal becoming too corrupted by undesirable delays and skew. features low output-to-output skew 2000v esd protection 1:9 low skew clock driver differential inputs and outputs available to industrial grade temperature range (plcc package only) ordering code: devices also available in tape and reel. specify by appending the suffix letter ?x? to the ordering code. logic symbol pin descriptions connection diagram 28-pin plcc truth table order number package number package description 100311QC v28a 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square 100311qi v28a 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square industrial temperature range ( ? 40 c to + 85 c) pin names description clkin, clkin differential clock inputs en enable clk 0 ? 8 , clk 0 ? 8 differential clock outputs v bb v bb output nc no connect clkin clkin en clk n clk n lhllh hllhl xxhlh
www.fairchildsemi.com 2 100311 absolute maximum ratings (note 1) recommended operating conditions note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: esd testing conforms to mil-std-883, method 3015. commercial version dc electrical characteristics (note 3) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd, t c = 0 c to + 85 c note 3: the specified limits represent the ? worst case ? value for the parameter. since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. conditions for testing sho wn in the tables are cho- sen to guarantee operation under ? worst case ? conditions. storage temperature (t stg ) ? 65 c to + 150 c maximum junction temperature (t j ) + 150 c pin potential to ground pin (v ee ) ? 7.0v to + 0.5v input voltage (dc) v ee to + 0.5v output current (dc output high) ? 50 ma esd (note 2) 2000v case temperature (t c ) commercial 0 c to + 85 c industrial ? 40 c to + 85 c supply voltage (v ee ) ? 5.7v to ? 4.2v symbol parameter min typ max units conditions v oh output high voltage ? 1025 ? 955 ? 870 mv v in = v ih (max) loading with v ol output low voltage ? 1830 ? 1705 ? 1620 mv or v il (min) 50 ? to ? 2.0v v ohc output high voltage ? 1035 mv v in = v ih loading with v olc output low voltage ? 1610 mv or v il (max) 50 ? to ? 2.0v v bb output reference voltage ? 1380 ? 1320 ? 1260 mv i vbb = ? 300 a v diff input voltage differential 150 mv required for full output swing v cm common mode voltage v cc ? 2.0 v cc ? 0.5 v v ih input high voltage ? 1165 ? 870 mv guaranteed high signal for all inputs v il input low voltage ? 1830 ? 1475 mv guaranteed low signal for all inputs i il input low current 0.50 av in = v il (min) i ih input high current v in = v ih (max) clkin, clkin 100 a en 250 i cbo input leakage current ? 10 av in = v ee i ee power supply current ? 115 ? 57 ma inputs open
3 www.fairchildsemi.com 100311 commercial version (continued) ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 4: f max = the highest frequency at which output v ol /v oh levels still meet v in specifications. the f311 will function @ 1 ghz. note 5: t ps describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair ? s low-to-high and high-to-low prop- agation delays. with differential signal pairs, a low-to-high or high-to-low transition is defined as the transition of the tru e output or input pin. note 6: t oslh describes in-phase gate-to-gate differential propagation skews with all differential outputs going low-to-high; t oshl describes the same con- ditions except with the outputs going high-to-low. note 7: t ost describes the maximum worst case difference in any of the t ps , t oslh or t ost delay paths combined. note 8: the skew specifications pertain to differential i/o paths. industrial version dc electrical characteristics (note 9) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd, t c = ? 40 c to + 85 c symbol parameter t c = 0 ct c = + 25 ct c = + 85 c units conditions min typ max min typ max min typ max f max max toggle frequency 750 750 750 mhz (note 4) clkin to q n t plh propagation delay, t phl clkin n to clk n differential 0.75 0.84 0.95 0.75 0.86 0.95 0.84 0.93 1.04 ns figure 3 single-ended 0.65 0.90 1.05 0.67 0.93 1.17 0.74 1.06 1.24 t plh propagation delay 0.75 1.03 1.20 0.80 1.05 1.25 0.85 1.12 1.35 ns figure 2 t phl sel to output t ps lh ? hl skew 10 30 10 30 10 30 ps (note 5)(note 8) t oslh gate ? gate skew lh 20 50 20 50 20 50 (note 6)(note 8) t oshl gate ? gate skew hl 20 50 20 50 20 50 (note 6)(note 8) t ost gate ? gate lh ? hl skew 30 60 30 60 30 60 (note 7)(note 8) t s setup time 250 250 300 ps en n to clkin n t h hold time000ps en n to clkin n t r release time 300 300 300 ps en n to clkin n t tlh transition time 275 500 750 275 480 750 275 460 750 ps figure 4 t thl 20% to 80%, 80% to 20% symbol parameter t c = ? 40 ct c = 0 c to + 85 c units conditions min max min max v oh output high voltage ? 1085 ? 870 ? 1025 ? 870 mv v in = v ih (max) loading with v ol output low voltage ? 1830 ? 1575 ? 1830 ? 1620 mv or v il (min) 50 ? to ? 2.0v v ohc output high voltage ? 1095 ? 1035 mv v in = v ih loading with v olc output low voltage ? 1565 ? 1610 mv or v il (min) 50 ? to ? 2.0v v bb output reference voltage ? 1395 ? 1255 ? 1380 ? 1260 mv i vbb = ? 300 a v diff input voltage differential 150 150 mv required for full output swing v cm common mode voltage v cc ? 2.0 v cc ? 0.5 v cc ? 2.0 v cc ? 0.5 v v ih input high voltage ? 1170 ? 870 ? 1165 ? 870 mv guaranteed high signal for all inputs
www.fairchildsemi.com 4 100311 industrial version (continued) dc electrical characteristics (note 9) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 9: the specified limits represent the ? worst case ? value for the parameter. since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. conditions for testing sho wn in the tables are cho- sen to guarantee operation under ? worst case ? conditions. ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 10: f max = the highest frequency of which output v ol /v oh levels still meet v in specifications. the f311 will function @ 1 ghz note 11: t ps describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's low-to-high and hi gh-to-low prop- agation delays. with differential signal pairs, a low-to-high or high-to-low transition is defined as the transition of the tru e output or input pin. note 12: t oslh describes in-phase gate differential propagation skews with all differential outputs going low-to-high; t oshl describes the same conditions except with the outputs going high-to-low. note 13: t ost describes the maximum worst case difference in any of the t ps , t oslh or t ost delay paths combined. note 14: the skew specifications pertain to differential i/o paths. symbol parameter t c = ? 40 ct c = 0 c to + 85 c units conditions min max min max v il input low voltage ? 1830 ? 1480 ? 1830 ? 1475 mv guaranteed low signal for all inputs i il input low current 0.50 0.50 av in = v il (min) i ih input high current v in = v ih (max) clkin, clkin 100 100 a en 250 250 i cbo input leakage current ? 10 ? 10 av in = v ee i ee power supply current ? 115 ? 57 ? 115 ? 57 ma inputs open v pp minimum input swing 150 150 mv v cmr common mode range v cc ? 2.0 v cc ? 0.5 v cc ? 2.0 v cc ? 0.5 v symbol parameter t c = ? 40 ct c = + 25 ct c = + 85 c units conditions min typ max min typ max min typ max f max max toggle frequency 750 750 750 mhz (note 10) clkin to q n t plh propagation delay, t phl clkin n to clk n differential 0.72 0.81 0.92 0.77 0.86 0.95 0.84 0.93 1.04 ns figure 3 single-ended 0.62 0.89 1.02 0.67 0.93 1.17 0.74 1.06 1.24 t plh propagation delay 0.70 0.97 1.20 0.80 1.05 1.25 0.85 1.12 1.35 ns figure 2 t phl sel to output t ps lh ? hl skew 10 30 10 30 10 30 (note 11)(note 14) t oslh gate ? gate skew lh 20 50 20 50 20 50 ps (note 12)(note 14) t oshl gate ? gate skew hl 20 50 20 50 20 50 (note 12)(note 14) t ost gate ? gate lh ? hl skew 30 60 30 60 30 60 (note 13)(note 14) t s setup time 250 250 300 ps en n to clkin n t h hold time 0 0 0 ps en n to clkin n t r release time 300 300 300 ps en n to clkin n t tlh transition time 275 500 750 275 480 750 275 460 750 ps figure 4 t thl 20% to 80%, 80% to 20%
5 www.fairchildsemi.com 100311 test circuit note: shown for testing clkin to clk1 in the differential mode. l1, l2, l3 and l4 = equal length 50 ? impedance lines. all unused inputs and outputs are loaded with 50 ? in parallel with 3 pf to gnd. scope should have 50 ? input terminator internally. figure 1. ac test circuit switching waveforms figure 2. propagation delay, en to outputs figure 3. propagation delay, clkin/clkin to outputs figure 4. transition times
www.fairchildsemi.com 6 100311 low skew 1:9 differential clock driver physical dimensions inches (millimeters) unless otherwise noted 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square package number v28a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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