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MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
DESCRIPTION
The M62500 is a semiconductor integrated circuit designed and developed as a deflection control of the CRT display monitor. The built-in trigger mode oscillator allows stable PWM control to be gained against a wide range of change of external signals. The M62500 provides a low supply voltage output malfunction preventive circuit (UVLO) and software start function optimum to horizontal output correction of monitor, high voltage drive and high voltage regulator.
PIN CONFIGURATION (TOP VIEW)
GND 1 VREF 2 Tin 3 Delay Adj 4 CAGC1 5 DTC 6 IN1 (+) 7 24 VCC 23 DRIVE OUTPUT 22 Phase Adj 21 Duty Adj 20 DOUBLE SPEED SWITCH 19 RAGC 18 CAGC2 17 IN2 (+) 16 IN2 (-) 15 FB2 14 COLLECTOR2 13 OUT2
FEATURES
PWM output in synchronization with external signals Wide range of PWM control frequency 15kHz to 150kHz The PWM output phase is adjustable against external signals Soft start Built-in low voltage output malfunction prevention circuit Start VCC>9V Stop VCC<6V
IN1 (-) 8 FB1 9 COLLECTOR1 10 OUT1 11 P.GND 12
Outline 24P4D (P) 24P2V-A (FP)
APPLICATION
CRT display monitor
BLOCK DIAGRAM
VCC 24 DRIVE OUTPUT 23 Phase Adj 22 Duty Adj 21 DOUBLE SPEED SWITCH 20 RAGC 19 CAGC2 18 IN2 (+) 17 IN2 (-) 16 FB2 COLLECTOR2 OUT2 15 14 13
PHASE CONT
EDGE DETECTION (SWITCH)
GEN AGC
WIND COMP
DUTY CONT
comp
GEN VREF DELAY AGC
OUTPUT START START (VCC>9V) STOP (VCC<6V) VCC
1 GND
2 VREF
3 Tin
4 Delay Adj
5 CAGC1
6 DTC
7 IN1 (+)
8 IN1 (-)
9
10
11
12 P. GND
FB1 COLLECTOR1 OUT1
( 1 / 11 )
MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
ABSOLUTE MAXIMUM RATINGS (Ta=25C, unless otherwise noted)
Symbol VCC VOUT IOUT Vd Id VICM VID Parameter Supply voltage Output voltage Output current Drive output voltage Drive output current Common mode input voltage range of error amplifier Common mode differential input voltage of error amplifier Power dissipation Thermal derating Operating temperature Storage temperature Ratings 15 15 150 15 20 -0.3 to VCC VCC P FP 1400 1000 P FP 11.2 8 -20 to +75 -40 to +125 Unit V V mA V mA V V mW mW/C C C
Pd K Topr Tstg
Note. For the polarity of current, the direction in which current flows to the IC is specified positive (+), while the direction in which current flows out from the IC is specified to be negative (-).
( 2 / 11 )
MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
ELECTRICAL CHARACTERISTICS (VCC=12V, fIN=40kHz, Ta=25C, unless otherwise noted)
Block
Symbol VCC ICC VCC ON VCC OFF VIO IIb IIO VICM AV SR VOR Isink Isource VsatL VsatH VREF Reg-in Reg-L TCVREF IREF MAX IS IIN VIN L VIN H IDelay TD min TD max IDTC Vth U Vth L TDuty IDuty Duty min Duty max Duty IPhase T2 min T2 max T2 Vsat D ILD Ifh Vfh
Parameter Range of power supply voltage Dissipation current Activation start voltage Activation stop voltage Input offset voltage Input bias voltage Input offset current Common mode input range Open loop gain Through rate Output voltage range 1) Output sink current Output source current Output saturation voltage L Output saturation voltage H Reference voltage Input stability Load voltage
Temperature coefficient of reference voltage
Test conditions
Without signal
IO=100mA IO=-100mA IREF=-5mA VCC=7 to 14V IREF=-5mA IREF=0 to -5mA Ta=-20 to +75C
Maximum reference current Short-circuit current Input current "L" input voltage "H" input voltage Input current Minimum delay time Maximum delay time Input current
Upper limit voltage of saw tooth wave Lower limit voltage of saw tooth wave
VIN=5V
VDelay adj=0V VDelay adj=3.0V
PWM output duty Input current Minimum duty Maximum duty Duty Input current
Minimum leading time of drive output Minimum leading time of drive output
VDTC=2.5V VDuty adj=2.5V
VDuty adj=2.5V VPhase adj=2.5V
Leading time of drive output Output saturation voltage Output leak current fh pin current fh switching voltage
VPhase adj=1.0V Id=10mA VDO=12V Vfh=5V
V mA V V mV -100 nA -100 100 nA -0.3 VCC-2 V 70 110 dB 4 V/s 0.3 VREF-1.5 V 10 mA -10 mA 0.7 1.4 V 9.5 10.5 V 4.80 5.00 5.20 V 1 10 mV 2 20 mV 0.01 %/C -40 mA -70 mA -- 200 140 A -- -- 0.6 V 2.0 -- V -- -0.1 A -0.6 -- -- s 0.8 1 10 s 15 -- 2.0 A -- 0.5 V 0.65VREF 0.7VREF 0.75VREF V 0.28VREF 0.3VREF 0.32VREF 45 50 % 55 -6.5 -1.3 A -- -- 10 % 20 % 80 95 -- % 45 50 55 -- -3.5 -0.7 A -- 0.7 1.6 s 9 9.4 -- s 7.0 4.5 5.5 s 0.4 V 1 A 430 -- 330 A 0.4VREF 0.5VREF 0.6VREF V 40 9 6.0
Min. VCC off 20 8 5.4
Limits Typ.
Max. 14 70 10 6.6 7
Unit
Note 1. Output must not be reversed with input of 0.
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MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
EXPLANATION OF TERMINALS
Pin No.
1
Symbol GND
Function and peripheral circuit of pins GND
VCC
2
VREF
5.0V reference voltage External load of about 5mA can be taken out.
2
VREF S Tin 3 FF R Q
3
Tin
Trigger input Read at the rising edge
VREF
4
Delay Adj
Delay adjustment Delay of read trigger signal VDelay : 0 to 3.0V TDelay : 1 to 10sec
4
VREF
5 18
CAGC1 CAGC2
AGC capacitance Connects capacitance between each pin and GND and sets up AGC sensitivity
5 18
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MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
EXPLANATION OF TERMINALS (Cont.)
Pin No. Symbol Function and peripheral circuit of pins
6
DTC
Dead time control (PWM comparator + pin)
6
VCC
7 8 16 17
IN1 (+) IN1 (-) IN2 (-) IN2 (+)
Air amplifier input pin
17 7
8 16
VCC 9 15
9 15
FB1 FB2
Air amplifier output (PWM comparator + input pin)
10 14
10 11 12 13 14
COLLECTOR1 OUT1 P.GND OUT2 COLLECTOR2
PWM output section
11 13
12
VREF
19
RAGC
AGC current setup Connects resistance between pin 19 and GND and sets up AGC current on the OUT2 side.
19
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MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
EXPLANATION OF TERMINALS (Cont.)
Pin No. Symbol Function and peripheral circuit of pins
VREF
20
fh/2fh
Double speed switch Switches frequency of OUT2 and drive output to the double frequency. OPEN, GND fh VREF 2fh
20
VREF
21
Duty Adj
Duty adjustment of drive output
21
Phase adjustment of drive output against OUT2 (T2)
VREF
22
Phase Adj
DRIVE OUT 22 OUT2 T2
VREF
23
DRIVE OUTPUT
Open collector output
23
24
VCC
Supply terminal
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MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
APPLICATION EXAMPLE
VCC C4 VR1 1 C1 Tin R1 C2 2 3 4 5 Cagc1 6 +IN1 -IN1 R2 7 R4 C4 R3 R5 C3 R6 8 9 10 11 12 18 17 16 15 14 13 R9 C5 R7 C6 19 Cagc2 R10 +IN2 -IN2 24 23 22 21 20 C9 C8 C7 Ragc R12 VR4 VR3 C10 DOUT
VR2 D1
R8 R11
OUT1
OUT2
C1, C10
: Is required for stabilization of Vcc and VREF. Is normally set to tens of F to hundreds of F.
R2, R3, R10, R11 : A gain setup constant of error Amp. To R4, R5, R8, R9 C3, C4, C5, C6 assure the stability of feedback, R4 and R8 shall be set to several k to tens of k to set the gain to approx. 20dB to 40dB with f=1 kHz. If the gain is too low, jitter may take place. It is therefore recommended to set C3 and C5 to tens of pF to hundreds of pF, C4 and C6 to thousands of pF to tens of thousands of pF, and R5 and R9 to tens of k to hundreds of k. Ragc C7 : Resistance for setting AGC on the OUT2 side. Is set with Ragc=27k. : If f to be input into Tin suddenly changes, addition of C7 shortens non-control time of Dout (output of "H"). As a capacitance value, it is recommended to adopt 2.2F. In the case of adding C7, however, Cagc20.68F is recommended. R6, R7 : Current limit resistance of OUT1/2. Is normally set to several . Insertion of direct limit resistance into OUT1/2 pin is also effective. R12 : Pull-up resistance of DOUT output. DOUT is an open collector output and requires R12. Is normally set to several k.
* Note: To reduce interference in the signal system, pins 1 GND and 12 P.GND shall be grounded at a point in the power supply block.
VR 1, 2, 3, 4
: Is determined taking into account the load capability of VREF. (External load capability of approx. 5mA) Shall be normally set to approx. 10k.
C2, C8, C9
: Is added to high impedance pin of voltage control for improvement in noise margin. Depends on the device installation environment. Shall be normally set to approx. 0.1F.
C4, D1
: Is added for the execution of software start. Set a time constant, taking into account the set value of VR2.
R1
: Is added to reduce interference by Tin and outputs. With VIN=approx. 2.5V to 5V, the resistance value of approx. 22k is recommended.
Cagc 1, 2
: Capacitance necessary for stabilization of AGC. As the capacitance is larger, the stability is larger, but the characteristic of answering becomes worse. The capacitance value of 1F is recommended.
( 7 / 11 )
MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
SETUP OF VOLTAGE CONTROL BLOCK
TD vs. VDELAY Adj CHARACTERISTICS (f=40kHz)
20
Applying a voltage to the DELAY Adj pin can control the delay time of OUT1 to TIN.
10 TIN
TD
TD
OUT1 0 0 2.0 4.0
VDELAY Adj (V)
PWM OUTPUT MINIMUM DUTY vs. VDTC CHARACTERISTICS (f=40kHz)
100
Applying a voltage to the DTC pin can control the dead time of PWM output.
80
60 TH 40 OUT1, 2 T 20
PWM output minimum duty
0 0 1 2 3 4
TDUTY= TH X100 (%) T
VDTC (V)
T2 vs. VPhase CHARACTERISTICS (f=40kHz)
10
Applying a voltage to the Phase Adj pin can control a leading time of drive output to OUT2.
8
6 OUT2 4 T2 2 DRIVE OUT 0 0 1 2 3 4 5 T2
VPhase (V)
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MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
T2 vs. f CHARACTERISTICS
10 VPhase=2300mV 8 VPhase=1350mV 6 VPhase=650mV 4 VPhase=250mV 2
0
0
50
100
150
TIN f (kHz)
DRIVE OUTPUT DUTY vs. VDUTY CHARACTERISTICS (f=40kHz)
100
Applying a voltage to the DUTY Adj pin can control drive output duty.
80
60
TH
Drive output
40 T
20
Drive output duty TDUTY= TH X100 (%) T
0
0
1
2
3
4
VDUTY (V)
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MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
TIME CHART
VCC 24
DRIVE OUTPUT 23
PHASE ADJ 22
DUTY ADJ 21
DOUBLE SPEED SWITCH 20
RAGC 19
CAGC2 18
IN2 (+) 17
IN2 (-) 16
FB2 COLLECTOR2 OUT2 15 14 13
PHASE CONT
E
WIND COMP
DUTY CONT
EDGE DETECTION (SWITCH)
GEN
AGC
D
F
C
comp
B
GEN VREF AGC
A
OUTPUT START START (VCC>9V) STOP (VCC<6V) VCC
DELAY
1 GND
2 VREF
3 Tin
4 Delay Adj
5 CAGC1
6 DTC
7 IN1 (+)
8 IN1 (-)
9
10
11
12 P. GND
FB1 COLLECTOR1 OUT1
PIN WAVE
PIN 3 TIN
A POINT B POINT
FB1 PIN 9
C POINT PIN 11 OUT1 TD
D POINT
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MITSUBISHI (Dig./Ana. INTERFACE)
M62500P/FP
SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC
PIN WAVE (Cont.)
D POINT E POINT
PIN 20 Low
F POINT
PIN 13 OUT2 PIN 23 D.OUT T1 T2 TL TH
FB2 PIN 15
E POINT
F POINT PIN 20 High PIN 13 OUT2 PIN 23 D.OUT
PWM OUT NON-CONTROL STATUS
With trigger input at pin
3
3.5V
1.5V FB>3.5V, FB>DTC High OUT1, 2
FB<1.5V, FB>DTC
Without trigger at pin
3
(in case of GND)
OUT1, 2 Low (GND)
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