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ILX703A
2048-pixel CCD Linear Image Sensor (B/W) with Shutter Function For the availability of this product, please contact the sales office.
Description The ILX703A is a reduction type CCD linear sensor designed for facsimile, image scanner and OCR use. This sensor reads B4 size documents at a density of 200 DPI (Dot Per Inch). Featuring a shutter function, correspondences with the sensitivity correction, etc, is possible. A built-in timing generator and clockdrivers ensure direct drive at 5V logic for easy use. Features * Number of effective pixels: 2048 pixels * Pixel size: 14m x 14m (14m pitch) * Built-in timing generator and clock-drivers * Shutter function * Ultra low lag * Maximum clock frequency: 5MHz Absolute Maximum Ratings * Supply voltage VDD1 VDD2 * Operating temperature * Storage temperature Pin Configuration (Top View) 22 pin DIP (Ceramic)
11 6 -10 to +55 -30 to +80
V V C C
VOUT GND GND SHSW CLK VDD1 GND VDD2 SHUT
1 2 3 4 5 6 7 8 9
1
22 21 20 19 18 17 16 15 14 13
VDD2 EXRS VDD1 RSSW VGG GND GND VDD1 NC NC GND
NC 10 ROG 11 2048
12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E93124D78-PS
Block Diagram
VDD1
NC
GND
VDD1
GND
VDD2
GND
NC
22 20
17 16 10
15
14
13 12
Shutter drain Shutter gate
S1
S2
D34
D35
NC D37 D38
Shutter gate pulse generator
D14
D15
D33
VOUT . CCD analog shift register
1
Read out gate
Output amplifier Sample-and-hold circuit
VGG 18
Clock-drivers
Clock pulse generator Sample-and-hold pulse generator
Mode selector
2 7
3
6 8 5
19
S2047
Read out gate pulse generator
S2048
D36
D39
9
VDD1
GND
GND
GND
VDD2
CLK
EXRS
RSSW
SHSW
ROG
SHUT
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21 4
11
ILX703A
ILX703A
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol VOUT GND GND SHSW CLK VDD1 GND VDD2 SHUT NC ROG GND NC NC VDD1 GND GND VGG RSSW VDD1 EXRS VDD2 Signal output GND GND Switch Description
{
with S/H GND without S/H VDD2
Clock pulse 9V power supply GND 5V power supply Shutter pulse NC Clock pulse GND NC NC 9V power supply GND GND Output circuit gate bias Reset pulse swithover pin (External RS VDD2, Internal RS GND) 9V power supply RS input pin during external RS pulse usage 5V power supply
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ILX703A
Recommended Voltage Item VDD1 VDD2 Min. 8.5 4.75 Typ. 9.0 5.0 Max. 9.5 5.25 Unit V V
Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
Mode Description Mode in use RS Internal Externel S/H Yes No No Pin condition 4 pin SHSW 19 pin RSSW 21 pin EXRS GND VDD2 VDD2 GND GND VDD2 VDD2 VDD2 RS
Input Capacity of Pins Item Input capacity of CLK pin Input capacity of ROG pin Input capacity of SHUT pin Input capacity of EXRS pin Symbol CCLK CROG CSHUT CEXRS Min. -- -- -- -- Typ. 10 10 10 10 Max. -- -- -- -- Unit pF pF pF pF
Recommended Input Pulse Voltage Parameter Input clock high level Input clock low level Min. 4.5 0.0 Typ. 5.0 -- Max. 5.5 0.5 Unit V V
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ILX703A
Electro-optical Characteristics (Ta = 25C, VDD1 = 9V, VDD2 = 5V, Clock frequency: 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)), When Internal RS (Pin 19 = GND, Pin 21 = VDD2) Item Sensitivity 1 Sensitivity 2 Sensitivity 3 Sensitivity 4 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Shutter lag Symbol R1 R2 R3 R4 PRNU VSAT VDRK DSNU IL DR SE IVDD1 IVDD2 TTE ZO VOS SHUT Min. 22.5 -- -- -- -- 1.5 -- -- -- -- -- -- -- 92.0 -- -- 0 Typ. 30 95 20 500 2.0 1.8 0.3 0.5 0.02 6000 0.060 8.0 3.0 97.0 600 4.5 1.0 Max. 37.5 -- -- -- 8.0 -- 2.0 3.0 -- -- -- 14.0 6.0 -- -- -- 5.0 Unit V/(lx * s) V/(lx * s) V/(lx * s) V/(lx * s) % V mV mV % -- lx * s mA mA % V % Remarks Note 1 Note 2 Note 3 Note 4 Note 5 -- Note 6 Note 6 Note 7 Note 8 Note 9 -- -- -- -- Note 10 Note 11
Notes) 1) For the sensitivity test light is applied with a uniform intensity of illumination. 2) W lamp (2854K) 3) Light source: LED = 570nm 4) Light source: LED = 660nm 5) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = (VMAX - VMIN)/2 x 100 [%] VAVE
The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE. 6) Integration time is 10ms. 7) VOUT = 500mV 8) DR = VSAT/VDRK When optical accumulated time is shorter, the dynamic range gets wider because dark voitage is in proportion to optical accumulated time. 9) SE = VSAT/R1
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ILX703A
10) VOS is defined as indicated below.
D31 OS D32 D33 S1
VOS
GND
11) To stipulate the lag during shutter operation, use the formula below. Place the output voltage average value during shutter operation at VSHUT and the output voltage average value when the shutter is not in operation at VAVE. (Refer to Figure 7.) SHUT = VSHUT x 100 [%] VAVE Please note that the shutter pulse at this time accord with Figure 6.
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Figure 1. Clock Timing Diagram (For internal RS mode)
5
ROG
0
2 3 4
2087
1
5
CLK
0
D1
1
VOUT
D2 D3 D4 D5 D6
Dummy signal (33 pixels)
D11 D12 D13 D14 D15
Optical black (18 pixels)
D31 D32 D33 S1 S2 S3 S4
Effective picture elements signal (2048 pixels)
1-line output period (2087 pixels)
S2045 S2046 S2047 S2048 D34 D35 D36 D37 D38 D39
Dummy signal (6 pixels)
Internal S/H is not in use (Pin4 VDD2) ILX703A
2
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Figure 2. Clock Timing Diagram (For external RS mode)
5
ROG
0
2 3 4
2087
1
5
CLK
0
5
RS
0
1
VOUT
D2 D3 D4 D5 D6
Dummy signal (33 pixels)
D11 D12 D13 D14 D15
Optical black (18 pixels)
D31 D32 D33 S1 S2 S3 S4
Effective picture elements signal (2048 pixels)
1-line output period (2087 pixels)
S2045 S2046 S2047 S2048 D34 D35 D36 D37 D38 D39
Dummy signal (6 pixels)
2
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ILX703A
ILX703A
Figure 3. CLK, VOUT Timing (For internal RS mode)
t1 t2
CLK t3 t4
t10
VOUT
t17
Item CLK pulse rise/fall time CLK pulse duty1 CLK - VOUT 1 CLK - VOUT 2 1 100 x t3/(t3 + t4)
Symbol t1, t2 -- t10 t17
Min. 0 40 50 30
Typ. 10 50 80 75
Max. -- 60 110 120
Unit ns % ns ns
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ILX703A
Figure 4. CLK, RS, VOUT Timing (For external RS mode)
t1 t2
CLK t3 t5 t4
RS t8 t6 t11 t9 t7 t10
VOUT t18
Item CLK, RS pulse rise/fall time CLK pulse duty1 CLK - RS pulse timing CLK - RS pulse timing RS pulse period CLK - VOUT RS - VOUT 1 100 x t3/(t3 + t4)
Symbol t1, t2, t8, t9 -- t6 t7 t5 t10 t11, t18
Min. -- 40 0 50 50 50 30
Typ. 10 50 100 100 100 80 50
Max. 50 60 -- -- -- 110 70
Unit ns % ns ns ns ns ns
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ILX703A
Figure 5. ROG, CLK Timing
ROG
t13
t14
t15
CLK t12 t16
Item ROG, CLK pulse timing ROG pulse rise/fall time ROG pulse period
Symbol t12, t16 t13, t15 t14
Min. 500 0 500
Typ. 1000 10 1000
Max. -- -- --
Unit ns ns ns
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Figure 6. Shutter Operation Mode Clock
5
ROG
0
5
CLK
0 2087 bits or more
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Light source ON
5
SHUT
0 1ms
Illumination
During shutter lag evaluation, the light source will be accompanied by a flash.
ILX703A
Figure 7. Shutter Pulse and Output Voltage
ROG
5V
0V
Illumination
ON
OFF
ON
OFF
ON
OFF
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Shutter ON VSHUT VAVE
SHUT
5V
0V
VOUT
ILX703A
ILX703A
Description of Shutter Pin 9 1) The state at 5V is when the shutter is not in operation. 2) When dropped to 0V, the shutter gate will open, letting the accumulated charge of the sensor be thrown away to the shutter drain.
ROG
5V 0V The charge is sent to the transfer register as signal charge.
Accumulated charge of the sensor The charge up to this point will be thrown away to the shutter drain.
SHUT
5V 0V Shutter gate ON
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ILX703A
Example of Representative Characteristics
Spectral sensitivity characteristics (Standard characteristics)
1.0 Ta = 25C 0.9 0.8
Relative sensitivity
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 800 Wavelength [nm] 900 1000
MTF of main scanning direction (Standard characteristics)
0 1.0 Spatial frequency [cycles/mm] 7.1 14.3 21.4 28.6 35.7 1.0 0
MTF of sub scanning direction (Standard characteristics)
Spatial frequency [cycles/mm] 7.1 14.3 21.4 28.6 35.7
0.8
0.8
X-MTF
0.6
0.6
0.4
Y-MTF
0.4 0.2 0.2 0 0 0.2 0.4 0.6 0.8 Normalized spatial frequency 1.0 0 0 0.2 0.4 0.6 0.8 Normalized spatial frequency 1.0
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ILX703A
Dark signal voltage rate vs. Ambient temperature (Standard characteristics)
VDD1, VDD2 supply current vs. Clock frequency (Standard characteristics)
IVDD1 IVDD2
10
10
5
5
1
IVDD1, IVDD2 - VDD1, VDD2 supply current [mA]
0 10 20 30 40 50 Ta - Ambient temperature [C]
Dark signal voltage rate
1
0.5
0.5
0.1
0.1 0.1M
1M Clock frequency [Hz]
5M
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Application Circuit (When internal RS)
10/16V
1
5V
9V 22 VDD2 (D) EXRS VDD1 (A) RSSW VGG GND (A) GND (A) VDD1 (A) NC NC GND (D) 21 20 19 18 17 16 15 14 13 12
22 pin DIP
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VOUT 1 5 (D) GND 2 SHSW 4 CLK (A) GND 3 (A) VDD1 6 (D) GND 7 (D) VDD2 8 SHUT 9 CLK 2SA1175 SHUT
NC 10
ROG 11
0.01
10/16V 0.01 ROG 22/10V
3k
Output signal
ILX703A
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ILX703A
Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Regulation for raising and lowering the power supply voltage When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V). 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
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Package Outline
Unit: mm
22pin DIP (400mil)
22
12
5.0 0.5
1 40.2
11
1. The height from the bottom to the sensor surface is 1.61 0.3mm.
4.0 0.5
2.54 0.51
2.6 3.3 0.5
2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5 .
0.3
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
Cer-DIP
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
3.9g
(AT STAND OFF) 10.16
H
0.25
V No.1 Pixel
9.0 10.0 0.5
0 to 9
7.35 0.8
41.6 0.5 28.672 (14m x 2048Pixels)
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ILX703A

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