View CXD2307_110199.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXD2307R
10-bit 50MSPS RGB 3-channel D/A Converter
Description The CXD2307R is a 10-bit high-speed D/A converter for video band, featuring RGB 3-channel I/O. This is ideal for use in high-definition TVs and high-resolution displays. Features * Resolution 10-bit * Maximum conversion speed 50MSPS * RGB 3-channel I/O * Differential linearity error 0.5LSB * Low power consumption; 300 mW (max.) * Single +5 V power supply * Low glitch * Stand-by function Structure Silicon gate CMOS IC 64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage AVDD, DVDD 7 V * Input voltage (All pins) VIN VDD+0.5 to VSS-0.5 V * Output current (for each channel) IOUT 0 to 15 mA * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS 4.75 to 5.25 V * Reference input voltage VREF 1.8 to 2.0 V * Clock pulse width TPW1,TPW0 9 ns (min.) to 1.1 s (max.) * Operating temperature Topr -20 to +85 C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E92928D01
CXD2307R
Block Diagram
62 DVDD (LSB) R0 63 R1 64 R2 1 R3 R4 2 3 LATCHES DECODER CLOCK GENERATOR DECODER CURRENT CELLS (FOR FULL SCALE) 4LSB'S CURRENT CELLS 31 RCK 43 ROR 40 VRR 37 IRR 56 AVDD 57 AVDD 46 VGG 6MSB'S CURRENT CELLS LATCHES DECODER CLOCK GENERATOR DECODER CURRENT CELLS (FOR FULL SCALE) 4LSB'S CURRENT CELLS 32 GCK 45 ROG 41 VRG 38 IRG 52 AVDD 53 AVDD 48 VGB 6MSB'S CURRENT CELLS 58 BO 59 BO 54 GO 55 GO 6MSB'S CURRENT CELLS 4LSB'S CURRENT CELLS 60 AVDD 61 AVDD 44 VGR
50 RO 51 RO
R5 4 R6 R7 5 6
R8 7 (MSB) R9 (LSB) G0 8 9
G1 10 G2 11 G3 12 G4 13 G5 14 G6 15 G7 16 G8 17 (MSB) G9 18 (LSB) B0 19 B1 20 B2 21 B3 22 B4 23 B5 24 B6 25 B7 26 B8 27 (MSB) B9 28 DECODER DECODER LATCHES
33 BCK CLOCK GENERATOR CURRENT CELLS (FOR FULL SCALE) BIAS VOLTAGE GENERATOR 47 ROB
42 VRB 39 IRB
35 VB 36 AVSS
BLK 29 CE 30
49 AVSS 34 DVSS
--2--
CXD2307R
AVss
VGG
VRG
VRR
DVss
ROG
VGR
ROR
VGB
ROB
VRB
IRB
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVss 49 RO 50 RO 51 AVDD 52 AVDD 53 GO 54 GO 55 AVDD 56 AVDD 57 BO 58 BO 59 AVDD 60 AVDD 61 32 GCK 31 RCK 30 CE 29 BLK 28 B9 27 B8 26 B7 25 B6 24 B5 23 B4 22 B3 21 B2 20 B1 19 B0 (LSB) 18 G9 17 G8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DVDD 62 (LSB) R0 63 R1 64
R6
(LSB) G0
G3
G4
R8
G5
R5
R4
R9
VB
G2
Pin Description and Equivalent Circuit Pin No. 63 to 8 9 to 18 19 to 28 Symbol R0 to R9 G0 to G9 B0 to B9 I/O Equivalent circuit Description Digital input. R0 (LSB) to R9 (MSB) G0 (LSB) to G9 (MSB) B0 (LSB) to B9 (MSB) Blanking input. This is synchronized with the clock input signal for each channel. No signal for High (0 V output). Output generated for Low. Chip enable pin. This is not synchronized with the clock input signal. No signal at for High (0 V output) to minimize power consumption.
29
BLK
63 to
DVDD
I 30 CE
33 DVSS
31 32 33 34
RCK GCK BCK DVSS --
G1
Clock input.
Digital ground.
--3--
G6
G7
R3
R2
R7
BCK
IRG
IRR
Pin Configuration
CXD2307R
Pin No.
Symbol
I/O
Equivalent circuit
DVDD
Description
DVDD
35
VB
O
35
Connect to DVSS with a capacitor of approximately 0.1 F.
DVSS
36, 49
AVSS
--
AVDD 43
Analog grounds.
43 45 47
ROR ROG ROB
45
O
47 AVSS
Connect to VGR, VGG, and VGB with the control method of output amplitude. See Application Circuit.
AVDD
44 46 48
VGR VGG VGB
44
I
46 48 AVSS
Connect a capacitor of approximately 0.1 F.
AVDD
37 38 39
IRR IRG IRB
37
O
38 39 AVSS
Connect to AVSS with a resistance of 3.3 k .
AVDD
40 41 42
VRR VRG VRB
I
40 41 42 AVSS
Set output full-scale value (2.0 V).
--4--
CXD2307R
Pin No. 50 54 58 51 55 59 52, 53, 56, 57, 60, 61 62
Symbol RO
I/O
Equivalent circuit
AVDD 50
Description
GO BO O RO
54 58 AVSS AVDD 51
Current output pins. Output can be retrieved by connecting a resistance of 200 to AVSS.
GO BO AVDD DVDD -- --
55 59 AVSS
Reverse current output pins. Normally connected to AVSS.
Analog VDD. Digital VDD.
Timing Chart
tPW1 tPW0
CLK
1.5V
ts th
ts th
ts th
DATA
tPD
100%
D/A OUT tPD tPD
50%
0%
I/O Correspondence Table (output full-scale voltage: 2.00 V) Input code MSB LSB 1111111111 : 1000000000 : 0000000000 Output voltage 2.0 V 1.0 V 0V
--5--
CXD2307R
Electrical Characteristics Item Resolution Conversion speed Integral non-linearity error Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage Output full-scale ratio 1 Output full-scale current Output offset voltage Glitch energy Crosstalk Supply current Analog input resistance Input capacitance Output capacitance Digital input voltage Digital input current Setup time Hold time Propagation delay time CE enable time 2 Symbol n FCLK EL ED VOC VFS FSR IFS VOS GE CT IDD ISTB RIN CI Co VIH VIL IIH IIL ts th tPD tE tD
(FCLK=50 MHz, AVDD=DVDD=5 V, ROUT=200 , VREF=2.0 V, Ta=25 C) Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=-20 to 85 C Endpoint Min. Typ. 10 Max. Unit bit MSPS LSB LSB V V % mA mV pV*s dB mA M 9 RO,GO,BO AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C 50 2.15 0.85 -5 7 3 10 CE=HL CE=LH -1 1 1 2 2 x 100 (%) 5 pF pF V A ns ns ns ms ms
0.5 -2.0 -0.5 1.8 1.8 1.9 1.9 1.5 9.5
50 2.0 0.5 2.0 2.0 3.0 10 1
For the same gain (See the Application Circuit) When "0000000000" data input When 1 kHz sine wave input CE= "L" CE= "H" VGR, VGG, VGB, VRR, VRG, VRB
0
100 54 55
60 1
1
1 2
Full-scale voltage for each channel Full-scale voltage average value for each channel When the external capacitors for the VG pins are 0.1 F. Full-scale output ratio =
Electrical Characteristics Measurement Circuit Analog Input Resistance Digital Input Current
}
+5.25V
Measurement Circuit
AVDD, DVDD
A
CXD2307R
V
AVSS, DVSS
--6--
CXD2307R
Maximum Conversion Speed Measurement Circuit
10 bit COUNTER WITH LATCH R0 to R9 63 to 8 G0 to G9 9 to 18 B0 to B9 19 to 28 29 BLK 30 CE 35 VB 0.1 DVss CLK 50MHZ SQUARE WAVE 31 RCK 32 GCK 33 BCK RO 50 RO 51 GO 54 GO 55 BO 58 BO 59 VGR to VGB 44, 46, 48 ROR to ROB 43, 45, 47 VRR to VRB 40 to 42 IRR to IRB 37 to 39 AVDD 0.1 2V
200 AVss 200 AVss 200 AVss OSCILLO SCOPE
3.3k
Setup Time Hold Time Glitch Energy
}
Measurement Circuit
10 bit COUNTER WITH LATCH R0 to R9 63 to 8 G0 to G9 9 to 18 B0 to B9 19 to 28 29 BLK 30 CE 35 VB RO 50 RO 51 GO 54 GO 55 BO 58 BO 59 AVDD 0.1 2V 200 AVss 200 AVss 200 AVss OSCILLO SCOPE
DELAY CONTROLLER
CLK 50MHZ SQUARE WAVE
DELAY CONTROLLER
VGR to VGB 0.1 44, 46, 48 ROR to ROB DVss 43, 45, 47 31 RCK VRR to VRB 32 GCK 40 to 42 IRR to IRB 33 BCK 37 to 39
3.3k
Cross Talk Measurement Circuit
ALL "1" DIGITAL WAVEFORM GENERATOR R0 to R9 63 to 8 G0 to G9 9 to 18 B0 to B9 19 to 28 29 BLK 30 CE 35 VB
RO 50 RO 51 GO 54 GO 55 BO 58 BO 59 AVDD
200 AVss 200 AVss 200 AVss 0.1 2V SPECTRUM ANALYZER
CLK 50MHZ SQUARE WAVE
VGR to VGB 0.1 44, 46, 48 ROR to ROB DVss 43, 45, 47 31 RCK VRR to VRB 32 GCK 40 to 42 IRR to IRB 33 BCK 37 to 39
3.3k
--7--
CXD2307R
DC Characteristics Measurement Circuit
CONTROLLER
R0 to R9 63 to 8 G0 to G9 9 to 18 B0 to B9 19 to 28 29 BLK 30 CE 35 VB 0.1 DVss
RO 50 RO 51 GO 54 GO 55 BO 58 BO 59
200 AVss 200 AVss 200 AVss AVDD 0.1 2V DVM
CLK 50MHZ SQUARE WAVE
31 RCK 32 GCK 33 BCK
VGR to VGB 44, 46, 48 ROR to ROB 43, 45, 47 VRR to VRB 40 to 42 IRR to IRB 37 to 39
3.3k
Propagation Delay Time Measurement Circuit
R0 to R9 63 to 8 G0 to G9 9 to 18 B0 to B9 19 to 28 29 BLK 30 CE 35 VB 0.1 DVss CLK 50MHZ SQUARE WAVE
RO 50 RO 51 GO 54 GO 55 BO 58 BO 59 AVDD
FREQUENCY DEMULTIPLIER
200 AVss 200 AVss 200 AVss 0.1 2V OSCILLO SCOPE
VGR to VGB 44, 46, 48 ROR to ROB 43, 45, 47 31 RCK VRR to VRB 32 GCK 40 to 42 33 BCK IRR to IRB 37 to 39
3.3k
--8--
CXD2307R
Application Circuit
3.3k 0.1F 1k
(Gain equal)
0.1F
NC NC NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 ROUT 200 50 51 52 53 GOUT 200 54 55 56 57 BOUT 200 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Clock input
B channel input
DVDD DVSS
AVDD AVSS
R channel input
G channel input
(Gain independently)
0.1F 1k 3.3k 0.1F Clock input 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 ROUT 200 50 51 52 53 GOUT 200 54 55 56 57 BOUT 200 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DVDD DVSS AVDD AVSS B channel input
R channel input
G channel input
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--9--
CXD2307R
Notes on Operation * How to select the output resistance The CXD2307R is a D/A converter of the current output type. To obtain the output voltage connect the resistance to the current output pins RO, GO and BO. For specifications we have: Output full scale voltage VFS=1.8 to 2.0 [V] Output full scale current IFS=less than 15 [mA] Calculate the output resistance value from the relation of VFS=IFS x ROUT. Also, 16 times resistance of the output resistance is connected to reference current pin IRR, IRG and IRB. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS=VREF x 16ROUT/RIR. VREF is the voltage set at VRR,VRG and the VRB pin, and ROUT is the resistance connected to the current output pins RO, GO and BO while RIR is connected to IRR, IRG and IRB. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. * Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. * Power supply and ground To reduce noise effects separate analog and digital systems in the device periphery. For power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 F, as close as possible to the pin. * Latch up Analog power supply and digital power supply have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. * RO, GO and BO pins The RO, GO and BO pins are the inverted current output pins described in the Pin Description. The sums shown below become the constant value for any input data. a) The sum of the currents output from RO and RO b) The sum of the currents output from GO and GO c) The sum of the currents output from BO and BO However, the performances such as the linearity error of the inverted current output pin output current is not guaranteed. * Output full-scale voltage For the applications using the RGB signal, the color balance may be broken up when the no-adjusted output full-scale voltage is used.
--10--
CXD2307R
Latch Up Prevention The CXD2307R is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD and DVDD, when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources
DVDD AVDD
AVDD +5V +5V C CXD2307R
DVDD C DIGITAL IC
AVSS AVSS DVSS
DVSS
b. When analog and digital supplies are from a common source (i)
DVDD
AVDD +5V C CXD2307R
DVDD C DIGITAL IC
AVSS AVSS DVSS
DVSS
(ii)
DVDD
AVDD +5V C CXD2307R
DVDD C DIGITAL IC
AVSS AVSS DVSS
DVSS
--11--
CXD2307R
2. Example when latch up easily occurs a. When analog and digital supplies are from different sources
DVDD AVDD
AVDD +5V +5V C CXD2307R
DVDD C DIGITAL IC
AVSS AVSS DVSS
DVSS
b. When analog and digital supplies are from common source (i)
DVDD AVDD
AVDD +5V C CXD2307R
DVDD C DIGITAL IC
AVSS AVSS DVSS
DVSS
(ii)
DVDD AVDD
AVDD +5V CXD2307R
DVDD C DIGITAL IC
AVSS AVSS DVSS
DVSS
--12--
CXD2307R
Example of Representative Characteristics
80
70
Crosstalk CT [dB]
60
50 AVDD=DVDD=5V FCLK=50MSPS ROUT=200 RIR=3.3k Ta=25C 40
100k
1M Output frequency FO [HZ] Output frequency vs. Crosstalk
10M
60
1.9
Current consumption IDD [mA]
AVDD=DVDD=5V FCLK=50MSPS VREF=2.0V ROUT=200 RIR=3.3k 50
Full-scale voltage VFS [V]
AVDD=DVDD=5V FCLK=50MSPS VREF=2.0V ROUT=200 RIR=3.3k 1.8
-20
0
25
50
75
-20
0
25
50
75
Ambient temperature Ta [C] Ambient temperature vs. Current consumption
Ambient temperature Ta [C] Ambient temperature vs. Full-scale voltage
--13--
CXD2307R
Package Outline
Unit : mm
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
A 64 1 0.5 16 0.13 M + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g
--14--
0.5 0.2
(11.0)

▲Up To Search▲

Price & Availability of CXD2307

	To Download CXD2307 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .