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DS1238A MicroManager
www.dalsemi.com
FEATURES
Holds microprocessor in check during power transients Halts and restarts an out-of-control microprocessor Warns microprocessor of an impending power failure Converts CMOS SRAM into nonvolatile memory Unconditionally write protects memory when power supply is out of tolerance Delays write protection until completion of the current memory cycle Consumes less than 200 nA of battery current Controls external power switch for high current applications Debounces pushbutton reset Accurate 10% power supply monitoring Optional 5% power supply monitoring designated DS1238A-5 Provides orderly shutdown in microprocessor applications Pin-for-pin compatible with MAX691 Standard 16-pin DIP or space-saving 16-pin SOIC Optional industrial temperature range -40C to +85C
PIN ASSIGNMENT
VBAT VCCO VCC GND PF RVT OSCIN OSCSEL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RST RST WDS CEI CEO ST NMI IN VBAT VCCO VCC GND PF RVT OSCIN OSCSEL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RST RST WDS CEI CEO ST NMI IN
16-Pin DIP (300-mil) See Mech. Drawings Section
16-Pin SOIC (300-mil) See Mech. Drawings Section
PIN DESCRIPTION
VBAT VCCO VCC GND PF
RVT
OSCIN OSCSEL IN
NMI ST
CEO CEI WDS RST
RST
- +3-Volt Battery Input - Switched SRAM Supply Output - +5-Volt Power Supply Input - Ground - Power-Fail - Reset Voltage Threshold - Oscillator In - Oscillator Select - Early Warning Input - Non-Maskable Interrupt - Strobe Input - Chip Enable Output - Chip Enable Input - Watchdog Status - Reset Output (active low) - Reset Output (active high)
DESCRIPTION
The DS1238A MicroManager provides all the necessary functions for power supply monitoring, reset control, and memory backup in microprocessor-based systems. A precise internal voltage reference and comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally write protects external memory. The DS1238A also provides early warning detection of a user-defined threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset 1 of 13 111899
DS1238A
debounce circuit connected to the RST pin. An internal watchdog timer can also force the reset outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Oscillator control pins OSCSEL and OSCIN provide either external or internal clock timing for both the reset pulse width and the watchdog timeout period. The Watchdog Status and Reset Voltage Threshold are provided via WDS and RVT , respectively. A block diagram of the DS1238A is shown in NO TAG.
PIN DESCRIPTION
PIN NAME VBAT VCCO VCC PF
RVT
DESCRIPTION +3V battery input provides nonvolatile operation of control functions. VCC output for nonvolatile SRAM applications. +5V primary power input. Power-fail indicator, active high, used for external power switching as shown in NO TAG. Reset Voltage Threshold. Indicates that VCC is below the reset voltage threshold. Oscillator input or timing capacitor. See NO TAG. Oscillator Select. Selects internal or external clock functions. See NO TAG. Early warning power-fail input. This voltage sense point can be tied (via resistor divider) to a user-selected voltage. Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending power failure. Strobe input. A high-to-low transition will reset the watchdog timer, indicating that software is still in control. Chip enable output. Used with nonvolatile SRAM applications. Chip enable input. Watchdog Status. Indicates that a watchdog timeout has occurred. Active low reset output. Active high reset output.
OSCIN OSCSEL IN
NMI ST CEO CEI WDS RST
RST
POWER MONITOR
The DS1238A employs a bandgap voltage reference and a precision comparator to monitor the 5-volt supply (VCC) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RVT , RST, and RST outputs are driven to the active state. The VCC trip point (VCCTP) is set for 10% operation so that the RVT , RST and RST outputs will become active as VCC falls below 4.5 volts (4.37 typical). The VCCTP for the 5% operation option (DS1238A-5) is set for 4.75 volts (4.62 typical). The RST and RST signals are excellent for microprocessor reset control, as processing is stopped at the last possible moment of in-tolerance VCC. On power-up, RVT will become inactive as soon as VCC rises above VCCTP. However, the RST and RST signals remain active for a minimum of 50 ms (100 ms typical) after VCCTP is reached to allow the power supply and microprocessor to stabilize.
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DS1238A
DS1238A FUNCTIONAL BLOCK DIAGRAM Figure 1
WATCHDOG TIMER
The DS1238A provides a watchdog timer function which forces the WDS , RST, and RST signals to the active state when the strobe input ( ST ) is not stimulated for a predetermined time period. This time period is described below in NO TAG. The watchdog timeout period begins as soon as RST and RST are inactive. If a high-to-low transition occurs at the ST input prior to timeout, the watchdog timer is reset and begins to timeout again. The ST input timing is shown in NO TAG. In order to guarantee that the watchdog timer does not timeout, a high-to-low transition on ST must occur at or less than the minimum timeout of the watchdog as described in the AC Electrical Characteristics. If the watchdog timer is allowed to time out, the WDS , RST, and RST outputs are driven to the active state. WDS is a latched signal which indicates the watchdog status, and is activated as soon as the watchdog timer completes a 3 of 13
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full period as outlined in NO TAG. The WDS pin will remain low until one of three operations occurs. The first is to strobe the ST pin with a falling edge, which will both set the WDS as well as the watchdog timer count. The second is to leave the ST pin open, which disables the watchdog. Lastly, the WDS pin is active low whenever VCC falls below VCCTP and activates the RVT signal. The ST input can be derived from microprocessor address, data, or control signals, as well as microcontroller port pins. Under normal operating conditions, these signals would routinely reset the watchdog timer prior to timeout. The watchdog is disabled by leaving the ST input open, or as soon as VCC falls to VCCTP.
NON-MASKABLE INTERRUPT
The DS1238A generates a non-maskable interrupt ( NMI ) for early warning of a power failure to the microprocessor. A precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated by an internal band gap. The IN pin is a high-impedance input allowing for a userdefined sense point. An external resistor voltage divider network (NO TAG) is used to interface with high voltage signals. This sense point may be derived from the regulated 5-volt supply, or from a higher DC voltage level closer to the main system power input. Since the IN trip point VTP is 1.27 volts, the proper values for R1 and R2 can be determined by the equation as shown in NO TAG. Proper operation of the DS1238A requires that the voltage at the IN pin be limited to VIH. Therefore, the maximum allowable voltage at the supply being monitored (VMAX) can also be derived as shown in NO TAG. A simple approach to solving this equation is to select a value for R2 of high enough value to keep power consumption low, and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for microprocessor shutdown between NMI and RST or RST . When the supply being monitored decays to the voltage sense point, the DS1238A will force the NMI output to an active state. Noise is removed from the NMI power-fail detection circuitry using built-in time domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an internal ring oscillator running at approximately 30 kHz (33 s/cycle). Three consecutive samplings of out-of-tolerance supply (below VSENSE) must occur at the IN pin to active NMI . Therefore, the supply must be below the voltage sense point for approximately 100 s or the comparator will reset. In this way, power supply noise is removed from the monitoring function preventing false trips. During a power-up, any IN pin levels below VTP detected by the comparator are disabled from reaching the NMI pin until VCC rises to VCCTP. As a result, any potential active NMI will not be initiated until VCC reaches VCCTP. Removal of an active low level on the NMI pin is controlled by the subsequent rise of the IN pin above VTP. The initiation and removal of the NMI signal during power up depends on the relative voltage relationship between VCC and the IN pin voltage. Note that a fast-slewing power supply may cause the NMI to be virtually nonexistent on power-up. This is of no consequence, however, since an RST will be active. The NMI voltage will follow VCC down until VCC decays to VBAT. Once VCC decays to V BAT , the NMI pin will enter a tri-state mode.
ST INPUT TIMING Figure 2
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OSCILLATOR CONTROLS Table 1
Watchdog Timeout Period (typ) OSCIN External Ext Clk Ext Cap Internal Low Hi/Open OSCSEL Low Low Hi/Open Hi/Open First Period Following a Reset 20480 Clks 2.2 sec X Cpf 47 pf 2.7 sec 2.7 sec Other Timeout 5120 Clocks 550 ms X Cpf 47 pf 170 ms 2.7 sec Reset Active Duration 641 Clks 69 ms X Cpf 47 pf 85 ms 85 ms
Note that the OSCIN and OSCSEL pins are tri-stated when VCC is below VBAT.
POWER MONITOR, WATCHDOG TIMER, AND PUSHBUTTON RESET Figure 3
PUSHBUTTON RESET TIMING Figure 4
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NON-MASKABLE INTERRUPT Figure 5
VSENSE =
R1 +R2 x 1.27 R2
VSENSE x 5.0 = VMAX 1.27
MAXVOLTAGE =
Example 1: 5-Volt Supply, R2 = 10k Ohms, VSENSE = 4.8 Volts 4.8 =
Example 2: 12-Volt Supply, R2 = 10k Ohms, VSENSE = 9.0 Volts 9.0 = R1 + 10k x 1.27 R1 = 60.9k Ohm 10k
9.00 x 5.0 = 35.4 Volts 1.27
R1 + 10k x 1.27 R1 = 27.8k Ohm 10k
VMAX =
NMI FROM IN INPUT Figure 6
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MEMORY BACKUP
The DS1238A provides all of the necessary functions required to battery back a static RAM. First, an internal switch is provided to supply SRAM power from the primary 5-volt supply (VCC) or from an external battery (VBAT), whichever is greater. Second, the same power-fail detection described in the power monitor section is used to hold the chip enable output ( CEO ) to within 0.3 volts of VCC or to within 0.7 volts of VBAT. The output voltage diode drop from VBAT (0.7V) is necessary to prevent charging of the battery in violation of UL standards. Write protection occurs as VCC falls below VCCTP as specified. If CEI is low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high, or the period tCE expires. This delay of write protection until the current memory cycle is completed prevents the corruption of data. If CEO is in an inactive state at the time of VCC fail detection, CEO will be unconditionally disabled within tCF. During nominal supply conditions CEO will follow CEI with a maximum propagation delay of 20 ns. NO TAG shows a typical nonvolatile SRAM application.
FRESHNESS SEAL
In order to conserve battery capacity during initial construction of an end system, the DS1238A provides a freshness seal that electrically disconnects the battery. This means that upon battery attachment, the VCCO output will remain inactive until VCC is applied. This prevents VCCO from powering other devices when the battery is first attached, and VCC is not present. Once VCC is applied, the freshness seal is broken and cannot be invoked again without subsequent removal and reattachment of the battery.
POWER SWITCHING
When larger operating currents are required in a battery-backed system, the internal switching devices of the DS1238A may be too small to support the required load through VCCO with a reasonable voltage drop. For these applications, the PF output is provided to gate external power switching devices. As shown in Figure 8, power to the load is switched from VCC to battery on power-down, and from battery to VCC on power-up. The DS1336 is designed to use the PF output to switch between VBAT and VCC. It provides better leakage and switchover performance than currently available discrete components. The transition threshold for PF is set to the external battery voltage VBAT, allowing a smooth transition between sources. Any load applied to the PF pin by an external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should be taken into consideration when sizing the battery.
NONVOLATILE SRAM Figure 7
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POWER SWITCHING Figure 8
Note: If freshness on the DS1238A is not used, and VBAT01 for system use.
PF
on the DS1336 may be tied to OUT1. This will free IN4, OUT4,
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 9 and Figure 10. Figure 9 illustrates the relationship for power down. As VCC falls, the IN pin voltage drops below VTP. As a result, the processor is notified of an impending power failure via an active NMI . This gives the processor time to save critical data in nonvolatile SRAM. As the power falls further, VCC crosses VCCTP, the power monitor trip point. When VCC reaches VCCTP, and active RST and RST are given. At this time, CEO is brought high to write-protect the RAM. When the VCC reaches VBAT, a power-fail is issued via the PF pin. Figure 10 shows the power-up sequence. As VCC slews above VBAT, the PF pin is deactivated. An active reset occurs as well as an NMI . Although the NMI may be short due to slew rates, reset will be maintained for the standard tRPU timeout period . At a later time, if the IN pin falls below VTP, a new NMI will occur. If the processor does not issue an ST , a watchdog reset will also occur. The second NMI and RST are provided to illustrate these possibilities.
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POWER-DOWN TIMING Figure 9
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POWER-UP TIMING Figure 10
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ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to Ground Voltage on I/O Relative to Ground Operating Temperature Operating Temperature (Industrial Version) Storage Temperature Soldering Temperature -0.5V to +7.0V -0.5V to VCC + 0.5V 0C to 70C -40C to +85C -55C to +125C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER SYMBOL MIN TYP MAX
(0C to 70C)
UNITS NOTES
Supply Voltage Supply Voltage (5% Option) Input High Level Input Low Level IN Input Pin Battery Input
VCC VCC VIH VIL VIN VBAT
4.5 4.75 2.0 -0.3 0 0
5.0 5.0
5.5 5.5 VCC+0.3 +0.8 VCC 4.0
V V V V V V
1 1 1 1 1 1
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL MIN
(0C to 70C; VDD= 5V 10%)
TYP MAX UNITS NOTES
Supply Current Battery Current Supply Output Current (VCCO = VCC - 0.3V) Supply Out Current (VCC < VBAT) Supply Output Voltage Battery Back Voltage Low Level @ RST Output Voltage @ -500 A
CEO
ICC IBAT ICC01 ICC02 VCCO VCCO VOL VOH VOHL ILI ILO IOL IOH VCCTP VCCTP ICCIN VTP -1.0 4.25 4.50 -1.0 1.15 11 of 13 1.27 4.37 4.62 -1.0 -1.0 VCC-0.5V VCC-0.1V VBAT-0.8 VCC-0.3 VBAT-0.8 0
4 200 100 1
mA nA mA mA V V
2 2, 12 3 4 1 6 1 1 6 2 11 9 10 1
0.4
V V V
and PF Output
Input Leakage Current Output Leakage Current Output Current @ 0.4V Output Current @ 2.4V Power Sup. Trip Point Power Supply Trip (5% Option) IN Input Pin Current IN Input Trip Point
+1.0 +1.0 4.0 4.50 4.75 +1.0 1.35
A A mA mA V V A V
1
DS1238A
AC ELECTRICAL CHARACTERISTICS
PARAMETER
(0C to 70C; VCC= 5V 10%)
MIN 40 TYP 100 MAX 175 UNITS NOTES
VCC Fail Detect to RST, RST VTP to NMI RESET Active OSCSEL=high
ST
SYMBOL tRPD
s s ms ns ms s 13
tIPD tRST tST tPB tF tPD tCF tFPU tRPU tFB1 tREC tR tCE tTD
40 40 20 30 300
100 85
175 150
Pulse Width
PBRST @ VIL VCC Slew Rate 4.75 to 4.25 Chip Enable Prop Delay VCC Fail to Chip Enable High VCC Valid to RST (RC=1) VCC Valid to RST VCC Slew to 4.25 to VBAT Chip Enable Output Recovery Time VCC Slew 4.25 to 4.75 Chip Enable Pulse Width Watchdog Time Delay Int Clock Long period Short period Watchdog Time Delay, Ext Clock, after Reset Normal VBAT Detect to PF OSC IN Frequency
20 7 40 10 0.1 0 5 1.7 110 2.7 170 20480 5120 12 100 144 100 150
ns s ns ms s s s s s ms clocks clocks 8 7 5 11
tTD
tPPF fOSC 0
2 250
s kHz
CAPACITANCE
PARAMETER SYMBOL MIN TYP MAX
(tA=25C)
UNITS NOTES
Input Capacitance Output Capacitance
CIN COUT
5 7
pF pF
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NOTES:
1. All voltages referenced to ground. 2. Measured with VCCO, CEO , PF, ST , RST, RST , and NMI pin open. 3. ICCO1 is the maximum average load which the DS1238A can supply at VCC-.3V through the VCCO pin during normal 5-volt operation. 4. ICCO2 is the maximum average load which the DS1238A can supply through the VCCO pin during data retention battery supply operation, with a maximum drop of 0.8 volts for commercial, 1.0V for industrial. 5. With tR = 5 s. 6. VCCO is approximately VBAT-0.5V at 1 A load. 7. tREC is the minimum time required before CEI / CEO memory access is allowed. 8. tCE maximum must be met to insure data integrity on power loss. 9. All outputs except RST which is 25 A max. 10. All outputs except RST , RTV , and NMI which is 25 A min. 11. The ST pin will sink 50 A in normal operation. The OSCIN pin will sink 5 A in normal operation. The OSCSEL pin will sink 10 A in normal operation. 12. IBAT is measured with VBAT=3.0V. 13. ST should be active low before the watchdog is disabled (i.e., before the ST input is tristated).
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