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FINAL
COM'L: -12/15/20
IND: -18/24
MACHLV210-12/15/20
High Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s Low-voltage operation, 3.3-V JEDEC compatible -- VCC = +3.0 V to +3.6 V s < 5 mA standby current s Patented design allows minimal standby current without speed degradation s Exclusively designed for 3.3-V applications s 44 Pins s 64 Macrocells s 12 ns tPD Commercial 18 ns tPD Industrial s 83.3 MHz fCNT
Lattice Semiconductor
s 38 Bus-Friendly Inputs s 32 Outputs s 64 Flip-flops; 2 clock choices s 4 "PAL22V16" blocks with buried macrocells s Pin-, function-, and JEDEC-compatible with MACH210 s Pin-compatible with MACH110, MACH111, MACH210, MACH211, and MACH215
GENERAL DESCRIPTION
The MACHLV210 is a member of the highperformance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 at an equal speed with a lower cost per macrocell. It is architecturally identical to the MACH210, with the addition of I/O pull-up/pull-down resistors and low-voltage, low-power operation. The MACHLV210 provides 3.3-V operation with lowpower CMOS technology. The patented design allows for minimal standby current without speed degradation by limiting the leakage current when signals are not switching. At less than 5 mA maximum standby current, the MACHLV210 is ideal for low-power applications. The MACHLV210 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially "PAL22V16" structures complete with product-term arrays and programmable macrocells, including additional buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACHLV210 has two kinds of macrocell: output and buried. The MACHLV210 output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACHLV210 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements.
Publication# 17908 Rev. D Issue Date: May 1995
Amendment /0
BLOCK DIAGRAM
I0-I1, I3-I4 8 I/O Cells 8 Macrocells
OE
I/O0-I/O7 8 I/O Cells 8 Macrocells 8
I/O8-I/O15
8 8 Macrocells
OE
8 Macrocells
2
44 x 68 AND Logic Array and Logic Allocator 22
44 x 68 AND Logic Array and Logic Allocator 22
4
Switch Matrix 22 44 x 68 AND Logic Array and Logic Allocator
OE
22 44 x 68 AND Logic Array and Logic Allocator
OE
2
Macrocells 8 I/O Cells 8 8
Macrocells 8
Macrocells 8 I/O Cells 8 8
Macrocells 8
2
I/O24-I/O31
I/O16-I/O23
CLK0/I2, CLK1/I5
17908D-1
2
MACHLV210-12/15/20
CONNECTION DIAGRAM Top View PLCC
I/O31 I/O30 I/O2 I/O1 VCC I/O29 I/O28 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O14 I/O15 GND I/O18 I/O19 VCC I/O12 I/O13 I/O16 I/O17 I/O20 I/O0 GND 2 I/O4 6 I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 I/O3 5
4
3
1 44 43 42 41 40 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21
17908D-2
Note: Pin-compatible with MACH110, MACH111, MACH210, MACH211, and MACH215.
PIN DESIGNATIONS
CLK/I = GND = I = I/O = VCC Clock or Input Ground Input Input/Output
= Supply Voltage
MACHLV210-12/15/20
3
ORDERING INFORMATION Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH LV
210
-12
J
C
FAMILY TYPE MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank = Standard Processing
TECHNOLOGY LV = Low Voltage
OPERATING CONDITIONS C = Commercial (0C to +70C)
DEVICE NUMBER 210 = 64 Macrocells, 44 Pins, Input Pull-Up/Pull-Down Resistors
PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
SPEED -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
Valid Combinations MACHLV210-12 MACHLV210-15 MACHLV210-20 JC
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
MACHLV210-12/15/20 (Com'l)
ORDERING INFORMATION Industrial Products
Programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH LV
210
-18
J
I
FAMILY TYPE MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank = Standard Processing
TECHNOLOGY LV = Low Voltage
OPERATING CONDITIONS I = Industrial (-40C to +85C)
DEVICE NUMBER 210 = 64 Macrocells, 44 Pins, Input Pull-Up/Pull-Down Resistors
PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
SPEED -18 = 18 ns tPD -24 = 24 ns tPD
Valid Combinations MACHLV210-18 MACHLV210-24 JI
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
MACHLV210-18/24 (Ind)
5
FUNCTIONAL DESCRIPTION
The MACHLV210 consists of four PAL blocks connected by a switch matrix. There are 32 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs. The MACHLV210 inputs and I/O pins have advanced pull-up/pull-down resistors that enable the inputs to be pulled to the last driven state. While it is always a good design practice to tie unused pins high or low, the MACHLV210 pull-up/pull-down resistors provide design security and stability in the event that unused pins are left disconnected.
Output
Table 1. Logic Allocation Macrocell
Buried Available Clusters
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15
The PAL Blocks
Each PAL block in the MACHLV210 (Figure 1) contains a 64-product-term logic array, a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 22 inputs. This makes the PAL block look effectively like an independent "PAL22V16" with 8 buried macrocells. In addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are provided. One of the two output enable product terms can be chosen within each I/O cell in the PAL block. All flip-flops within the PAL block are initialized together.
C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15
The Macrocell
The MACHLV210 has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured with or without the flip-flop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock/ gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch.
The Switch Matrix
The MACHLV210 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device.
The Product-term Array
The MACHLV210 product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. Two of the special-purpose product terms provide programmable output enable; one provides asynchronous reset, and one provides asynchronous preset.
The Logic Allocator
The logic allocator in the MACHLV210 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. 6
The I/O Cell
The I/O cell in the MACHLV210 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus.
MACHLV210-12/15/20
Benefits of Lower Operating Voltage
The MACHLV210 has an operating voltage range of 3.0 V to 3.6 V. Low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for portable applications. Because power is proportional to the square of the voltage, reduction of the supply voltge from 5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery life for portable applications.
Lower power consumption can also be used to reduce the size and weight of the battery. Thus, 3.3-V designs facilitate a reduction in the form factor. The MACHLV210 is not designed to interface between 3.3-V and 5.0-V logic. Latch-up may occur if VOH for the MACHLV210 is greater than VIH for the 5.0-V device. Although this scenario is unlikely, interfacing the MACHLV210 with 5.0-V devices is not encouraged without necessary latch-up design precautions.
MACHLV210-12/15/20
7
0
4
8
12
16
20
24
28
32
36
40
43 Output Enable Output Enable Asynchronous Reset Asynchronous Preset
M0
2
Output Macro cell
I/O Cell
I/O
M1
Buried Macro cell 2 I/O Cell
I/O
M2
2
Output Macro cell
M3
0
Buried Macro cell 2 I/O Cell
C0 C1 C2 C3 C4 Logic Allocator C5 C6 M6
Output Macro cell 2
I/O
M4
2
Output Macro cell
M5
Buried Macro cell 2 I/O Cell I/O
Switch Matrix
C7 C8 C9
M7
Buried Macro cell 2 I/O Cell
I/O
M8
Output Macro cell 2
C10 C11 C12 C13 C14 C15
63
M9
Buried Macro cell 2 I/O Cell
I/O
M10
2
Output Macro cell
M11
Buried Macro cell 2 I/O Cell
I/O
M12
Output Macro cell 2
M13
Buried Macro cell 2 I/O Cell
I/O
M14 M15
Output Macro cell 2
Buried Macro cell 2
0
4
8
12
16
20
24
28
32
36
40
43 CLK0 CLK1
16 8 14128G-2
17908D-3
Figure 1. MACHLV210 PAL Block 8 MACHLV210-12/15/20
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +5.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +3.0 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -2 mA, VCC = Min VIN = VIH or VIL IOL = 2 mA, VCC = Min VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 3.6 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = 3.3 V, TA = 25C, f = 0 MHz (Note 4) f = 25 MHz -30 2 60 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.4 Typ Max Unit V V V V A A A A mA mA mA
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.
MACHLV210-12 (Com'l)
9
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VCC = 3.3 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH -12 Parameter Description Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback to Clock Register Data Hold Time Clock to Output Clock Width External Feedback fMAX Maximum Frequency (Note 1) Internal Feedback (fCNT) No Feedback (fCNT) tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register Setup Input Register Clock Width Maximum Input Register Frequency 1/(tWICL + tWICH) Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup 10 13 D-type T-type LOW HIGH 12 13 5 6 90.9 2 1.5 17 19 2 1.5 15 5 15 LOW HIGH D-type T-type D-type T-type 5 6 58.8 55.6 83.3 76.9 90.9 9 0 9 D-type T-type 9 10 0 8 Min Max 12 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns
10
MACHLV210-12 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued)
Parameter Symbol tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER -12 Parameter Description Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable 12 12 12 12 12 12 16 Min 5 17 16 Max Unit ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions.
MACHLV210-12 (Com'l)
11
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +5.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -2 mA, VCC = Min VIN = VIH or VIL IOL = 2 mA, VCC = Min VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 3.6 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = 3.3 V, TA = 25C (Note 4) f = 0 MHz f = 25 MHz -30 2 60 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.4 Typ Max Unit V V V V A A A A mA mA mA
IOZH IOZL
ISC ICC
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset.
12
MACHLV210-15/20 (Com'l)
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VCC = 3.3 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH Parameter Description Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Clock Register Data Hold Time Clock to Output (Note 3) Clock Width External Feedback fMAX Maximum Frequency (Note 1) 1/(tS + tCO) LOW HIGH D-type T-type D-type Internal Feedback (fCNT) No Feedback tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS 1/(tWL + tWH) T-type 5 6 50 47.6 66.6 62.5 90.9 10 0 11 5 17 2.5 1.5 18 D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup 12 14 1/(tWICL + tWICH) LOW HIGH 13 14 5 6 90.9 2.5 1.5 19 22 16 18 27 20 7 8 66.7 3 2 25 29 3 3 24 7 23 D-type T-type 10 11 0 10 7 8 38.5 37 50 47.6 66.7 14 0 15 -15 Min Max 15 14 15 0 12 -20 Min Max 20 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output (Note 3) Gate Width LOW Input, I/O, or Feedback to Output Through Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register Setup
MACHLV210-15/20 (Com'l)
13
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued)
Parameter Symbol Parameter Description tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 3) Input, I/O, or Feedback to Output Disable (Note 3) 15 15 15 15 15 15 20 20 20 20 20 -15 Min Max 5 21 20 20 20 26 -20 Min Max 7 28 26 Unit ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 16 outputs switching.
14
MACHLV210-15/20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +5.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C) . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
INDUSTRIAL OPERATING RANGES
Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +3.0 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -2 mA, VCC = Min VIN = VIH or VIL IOL = 2 mA, VCC = Min VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 3.6 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = 3.3 V, TA = 25C (Note 4) f = 0 MHz f = 25 MHz -30 2 60 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.4 Typ Max Unit V V V V A A A A mA mA mA
IOZH IOZL
ISC ICC
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset.
MACHLV210-18/24 (Ind)
15
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VCC = 3.3 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH Parameter Description Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Clock Register Data Hold Time Clock to Output (Note 3) Clock Width External Feedback fMAX Maximum Frequency (Note 1) 1/(tS + tCO) LOW HIGH D-type T-type D-type Internal Feedback (fCNT) No Feedback tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS 1/(tWL + tWH) T-type 6 7.5 40 38 53 50 72.5 12 0 13.5 6 20.5 3 2.5 22 D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup 14.5 17 1/(tWICL + tWICH) LOW HIGH 16 17 6 7.5 72.5 3 2.5 23 26.5 19.5 22 32.5 24 8.5 10 53 4 3 30 34.5 4 4 29 8.5 28 D-type T-type 12 13.5 0 12 8.5 10 30.5 29.5 40 38 53 17 0 18 -18 Min Max 18 17 18 0 14.5 -24 Min Max 24 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output (Note 3) Gate Width LOW Input, I/O, or Feedback to Output Through Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register Setup
16
MACHLV210-18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued)
Parameter Symbol Parameter Description tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 3) Input, I/O, or Feedback to Output Disable (Note 3) 18 18 18 18 18 18 24 24 24 24 24 -18 Min Max 6 25.5 24 24 24 31.5 -24 Min Max 8.5 34 31.5 Unit ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit at the back of this Data Sheet for test conditions. 3. Parameters measured with 16 outputs switching.
MACHLV210-18/24 (Ind)
17
KEYS TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care; Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT*
3.3 V
S1
R1 Output R2 Test Point
CL
17908D-4
Commercial Specification tPD, tCO tEA tER S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 30 pF 1.6 K 5 pF 1.6 K CL R1 R2
Measured Output Value 1.5 V 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
18
MACHLV210-12/15/20
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 3.3 V, TA = 25C
IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 -40 -60 -80 .2 .4 .6 .8 1.0
Output, LOW
IOH (mA) 25 1 -3 -2 -1 -25 -50 -75 -100 -125 -150 2 3 4 5 VOH (V)
17908D-5
17908D-6
Output, HIGH II (mA)
20 VI (V) -2 -1 -20 -40 -60 -80 -100
17908D-7
1
2
3
4
5
Input MACHLV210-12/15/20 19
TYPICAL ICC CHARACTERISTICS
VCC = 3.3 V, TA = 25C
150
125
100 MACHLV210
ICC (mA)
75
50
25
0 0 10 20 30 40 50 60 70
17908D-8
Frequency (MHz)
The selected "typical" pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.
20
MACHLV210-12/15/20
ENDURANCE CHARACTERISTICS
The MACHLV210 is manufactured using our advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar
Parameter Symbol
parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory.
Parameter Description
Test Conditions Max Storage Temperature
Min 10 20 100
Unit Years Years Cycles
tDR N
Min Pattern Data Retention Time Max Reprogramming Cycles
Max Operating Temperature Normal Programming Conditions
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
>50 k
ESD Program/Verify Protection Circuitry Input
VCC
>50 k
Preload Circuitry Output
Feedback Input
17908D-9
MACHLV210-12/15/20
21
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja jma Typ Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient Thermal impedance, junction to ambient with air flow 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air PLCC 15 40 36 33 31 29 Units C/W C/W C/W C/W C/W C/W
Plastic jc Considerations
The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
22
MACHLV210-12/15/20
SWITCHING WAVEFORMS
Input, I/O, or Feedback
VT tPD
Combinatorial Output
VT
17908D-10
Combinatorial Output
Input, I/O, or Feedback tS Clock VT tCO Registered Output
VT tH
Input, I/O, or Feedback tSL Gate tPDL VT
17908D-11
VT tHL VT tGO VT
17908D-12
Latched Out
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH Clock tWL
17908D-13
Gate tGWS
VT
17908D-14
Clock Width
Gate Width (MACH 2, 3, and 4)
Registered Input tSIR Input Register Clock Combinatorial Output VT tICO
VT tHIR
Registered Input Input Register Clock VT Output Register Clock
VT
VT
tICS
VT
17908D-16
17908D-15
Registered Input (MACH 2 and 4)
Input Register to Output Register Setup (MACH 2 and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACHLV210-12/15/20
23
SWITCHING WAVEFORMS
Latched In tSIL Gate
VT tHIL VT tIGO
Combinatorial Output
VT
17908D-17
Latched Input (MACH 2 and 4)
tPDLL Latched In Latched Out Input Latch Gate tIGOL VT
VT
tIGS Output Latch Gate
tSLL VT
17908D-18
Latched Input and Output (MACH 2, 3, and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
24
MACHLV210-12/15/20
SWITCHING WAVEFORMS
tWICH Clock tWICL
17908D-19
VT
Input Latch Gate tWIGL
VT
17908D-20
Input Register Clock Width (MACH 2 and 4)
Input Latch Gate Width (MACH 2 and 4)
tARW Input, I/O, or Feedback tAR Registered Output VT tARR Clock VT
17908D-21
tAPW VT Input, I/O, or Feedback tAP Registered Output VT tAPR Clock VT
17908D-22
VT
Asynchronous Reset
Asynchronous Preset
Input, I/O, or Feedback tER Outputs VOH - 0.5V VOL + 0.5V
VT tEA VT
17908D-23
Output Disable/Enable
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACHLV210-12/15/20
25
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called "fCNT." The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
tS
t CO fMAX External; 1/(tS + tCO) CLK
tS
fMAX Internal (fCNT) CLK
LOGIC
REGISTER
REGISTER
LOGIC
tS
tSIR
tHIR fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
17908D-24
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
26
MACHLV210-12/15/20
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the
Parameter Symbol tPR tS tWL
wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Descriptions Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
Max 10 See Switching Characteristics
Unit s
VCC
Power 4V
tPR
Registered Output
tS
Clock
tWL
17908D-25
Power-Up Reset Waveform
MACHLV210-12/15/20
27
USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device's internal state can shorten test sequences, since it is easier to reach the state of interest. The observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 2. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 3. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support.
Reset Figure 3. Combinatorial Latch
17908D-27
Preloaded HIGH D Q1
Q
AR
Preloaded HIGH D Q2
Q
AR
On Preload Mode Off
Q1
AR
Q2
Figure 2. Preload/Reset Conflict
17908D-26
Set
28
MACHLV210-12/15/20
PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches)
.685 .695
.650 .656
.042 .056
.062 .083
Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630
.013 .021
.026 .032
.050 REF
.009 .015
.090 .120 .165 .180
SEATING PLANE
TOP VIEW
SIDE VIEW
16-038-SQ PL 044 DA78 6-28-94 ae
*For reference only. BSC is an ANSI standard for Basic Space Centering.
MACHLV210-12/15/20
33

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