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 74FR240 Octal Buffer/Line Driver with 3-STATE Outputs
October 1991 Revised August 1999
74FR240 Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74FR240 is an inverting octal buffer and line driver designed to be employed as memory and address driver, clock driver and bus oriented transmitter or receiver.
Features
s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs sink 64 mA and source 15 mA s Guaranteed pin-to-pin skew
Ordering Code:
Order Number 74FR240SC 74FR240SJ 74FR240PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names OE1, OE2 I0-I7 O0-O7 Description Output Enable Input (Active-LOW) Inputs Outputs
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Outputs In L H X (Pins 12, 14, 16, 18) H L Z Outputs In L H X (Pins 3, 5, 7, 9) H L Z
(c) 1999 Fairchild Semiconductor Corporation
DS010901
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74FR240
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) Twice the Rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOD IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ CIN Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input Low Current Input Leakage Test Output Circuit Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Input Capacitance 9 37 31 8.0 -100 4.75 3.75 20 -20 -225 50 100 13 45 38 2.4 2.0 0.55 5 7 -150 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A V A A A mA A A mA mA mA pF Min Min Min Min Max Max Max 0.0 0.0 Max Max Max Max 0.0 Max Max Max 5.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -15 mA IOL = 64 mA VIN = 2.7V VIN = 7.0V VIN = 0.5V IID = 1.9 A, All Other Pins Grounded VIOD = 150 mV, All Other Pins Grounded VOUT = 2.7V VOUT = 0.5V VOUT = 0.0V VOUT = VCC VOUT = 5.25V All Outputs HIGH All Outputs LOW Outputs 3-STATE
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74FR240
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay An to Bn or Bn to An Output Enable Time 1.0 1.0 2.6 2.6 1.7 1.7 VCC = +5.0V CL = 50 pF Typ 3.3 2.9 4.0 6.3 3.3 2.9 Max 4.7 4.7 7.0 7.0 6.6 6.6 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 1.0 1.0 2.6 2.6 1.7 1.7 Max 4.7 4.7 7.0 7.0 6.6 6.6 ns ns ns Units
Extended AC Electrical Characteristics
TA = 0C to +70C VCC = +5.0V Symbol Parameter CL = 50 pF Eight Outputs Switching (Note 3) Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 5) tOSLH (Note 5) tOST (Note 5) Pin-to-Pin Skew for HL Transitions Pin-to-Pin Skew for LH Transitions Pin-to-Pin Skew for HL/LH Transitions Output Disable Time Propagation Delay An to Bn or Bn to An Output Enable Time 1.0 1.0 2.6 2.6 1.7 1.7 Max 6.4 6.4 7.2 7.2 6.8 6.8 2.0 1.1 3.1 Min 2.3 2.3 Max 8.3 8.3 ns ns ns ns ns ns TA = 0C to +70C VCC = +5.0V CL = 250 pF (Note 4) Units
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase, i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc. Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW, (tOSHL), LOW-to-HIGH, (tOSLH), or HIGH-to-LOW and/or LOW-to-HIGH, (t OST). Specifications guaranteed with all outputs switching in phase.
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74FR240
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74FR240 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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