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| DS12B887 DS12B887 Real Time Clock FEATURES PIN ASSIGNMENT NC NC NC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC SQW NC RCLR NC IRQ NC DS NC R/W AS CS * Drop-in replacement for IBM AT computer clock/calendar * Pin compatible with the MC146818B and DS1287 * Totally nonvolatile with over 10 years of operation in the absence of power * Self-contained * Counts subsystem includes lithium, quartz, and support circuitry seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation alarm * Binary or BCD representation of time, calendar, and * 12- or 24-hour clock with AM and PM in 12-hour mode * Daylight Savings Time option * Multiplex bus for pin efficiency * Interfaced with software as 128 RAM locations - 14 bytes of clock and control registers - 114 bytes of general purpose RAM 24 PIN ENCAPSULATED PACKAGE PIN DESCRIPTION AD0-AD7 NC CS AS R/W DS IRQ SQW VCC GND RCLR - - - - - - - - - - - Multiplexed Address/Data Bus No Connection Chip Select Address Strobe Read/Write Input Data Strobe Interrupt Request Output Square Wave Output +5 Volt Supply Ground RAM Clear * Programmable square wave output signal * Bus-compatible interrupt signals (IRQ) * Three interrupts are separately software-maskable and testable - Time-of-day alarm once/second to once/day - Periodic rates from 122 s to 500 ms - End of clock update cycle DESCRIPTION The DS12B887 Real Time Clock plus RAM is designed to be a direct replacement for the DS1287A or DS12887A. The DS12B887 is identical in form, fit, and function to the DS1287A or DS12887A, with the exception of RCLR, and has an additional 64 bytes of general purpose RAM. Access to this additional RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle. A lithium energy source, quartz crystal, and write-protection circuitry are contained within a 24-pin dual in-line package. As such, the DS12B887 is a complete subsystem replacing 16 components in a typical application. The functions include a nonvolatile time-of-day clock, an alarm, a onehundred-year calendar, programmable interrupt, square wave generator, and 114 bytes of nonvolatile static RAM. The real time clock is distinctive in that time-of-day and memory are maintained even in the absence of power. ECopyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. 080895 1/16 DS12B887 OPERATION The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS12B887. The following paragraphs describe the function of each pin. BLOCK DIAGRAM DS12B887 Figure 1 OSC. B8 B64 B64 CS VCC VBAT POWER SWITCH AND WRITE PROTECT VCC POK PERIODIC INTERRUPT/SQUARE WAVE SELECTOR SQUARE WAVE OUT CS SQW IRQ REGISTERS A,B,C,D DS R/W AS ADO- AD7 BCD/ BINARY INCREMENT USER RAM 114 BYTES RAM CLEAR LOGIC RCLR BUS INTERFACE DOUBLE BUFFERED CLOCK/ CALENDAR UPDATE CLOCK, CALENDAR, AND ALARM RAM POWER-DOWN/POWER-UP CONSIDERATIONS The Real Time Clock function will continue to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the DS12B887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A). This time period allows the system to stabilize after power is applied. When VCC falls below 4.25 volts, the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin. The DS12B887 is, therefore, writeprotected. When the DS12B887 is in a write-protected state, all inputs are ignored and all outputs are in a high impedance state. When VCC falls below a level of approximately 3 volts, the external VCC supply is switched off and an internal lithium energy source supplies power to the Real Time Clock and the RAM memory. 080895 2/16 DS12B887 SIGNAL DESCRIPTIONS GND, VCC - DC power is provided to the device on these pins. VCC is the +5 volt input. When 5 volts are applied within normal limits, the device is fully accessible and data can be written and read. When VCC is below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of 1 minute per month at 25oC regardless of the voltage input on the VCC pin. SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the Real Time Clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in Register B. The SQW signal is not available when VCC is less than 4.25 volts typical. PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 1 SELECT BITS REGISTER A RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tPI PERIODIC INTERRUPT RATE None 3.90625 ms 7.8125 ms 122.070 ms 244.141 ms 488.281 ms 976.5625 ms 1.953125 ms 3.90625 ms 7.8125 ms 15.625 ms 31.25 ms 62.5 ms 125 ms 250 ms 500 ms SQW OUTPUT FREQUENCY None 256 Hz 128 Hz 8.192 kHz 4.096 kHz 2.048 kHz 1.024 kHz 512 Hz 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 080895 3/16 DS12B887 AD0-AD7 (Multiplexed Bidirectional Address/Data Bus) - Multiplexed buses save pins because address information and data information time share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS12B887 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS/ ALE, at which time the DS12B887 latches the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a read cycle the DS12B887 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as RD transitions high. AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address to be latched within the DS12B887. DS (Data Strobe or Read Input) - The DS pin is called Read(RD). RD identifies the time period when the DS12B887 drives the bus with read data. The RD signal is the same definition as the Output Enable (OE) signal on a typical memory. R/W (Read/Write Input)-The R/W signal is an active low signal called WR. In this mode the R/W pin has the same meaning as the Write Enable signal (WE) on generic RAMs. CS (Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the DS12B887 to be accessed. CS must be kept in the active state during RD and WR. Bus cycles which take place without asserting CS will latch addresses but no access will occur. When VCC is below 4.25 volts, the DS12B887 internally inhibits access cycles by internally disabling the CS input. This action protects both the real time clock data and RAM data during power outages. IRQ (Interrupt Request Output) - The IRQ pin is an active low output of the DS12B887 that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin the processor program normally reads the C register. When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an external pull-up resistor. RCLR (RAM Clear) - The RCLR pin is used to clear (set to logic 1) all 114 bytes of general-purpose RAM but does not affect the RAM associated with the real time clock. In order to clear the RAM, RCLR must be forced to an input logic of (-0.3 to +0.8 volts) when VCC is applied. The RCLR function is designed to be used via human interface (shorting to ground manually or by switch) and not to be driven with external buffers. This pin is internally pulled up. Do not use an external pull-up resistor on this pin. ADDRESS MAP The address map of the DS12B887 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and four bytes which are used for control and status. All 128 bytes can be directly written or read except for the following: 1. Registers C and D are read-only. 2. Bit 7 of Register A is read-only. 3. The high order bit of the seconds byte is read-only. The contents of four registers (A,B,C, and D) are described in the "Registers" section. 080895 4/16 DS12B887 ADDRESS MAP DS12B887 Figure 2 0 14 BYTES 13 14 0D 0E 00 0 1 2 3 4 5 6 7 8 9 10 11 12 127 7F 13 SECONDS SECONDS ALARM MINUTES MINUTES ALARM HOURS HOURS ALARM DAY OF THE WEEK DAY OF THE MONTH MONTH YEAR REGISTER A REGISTER B REGISTER C REGISTER D BINARY OR BCD INPUTS 080895 5/16 TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the ten time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a logic one to prevent updates from occurring while access is being attempted. In addition to writing the ten time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of Register B must be set to the appropriate logic level. All ten time, calendar, and alarm bytes must use the same data mode. The set bit in Register B should be cleared after the data mode bit has been written to allow the real time clock to update the time and calendar bytes. Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the ten data bytes. Table 2 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The 24-12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when it is a logic one. The time, calendar, and alarm bytes are always accessible because they are double buffered. Once per second the ten bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later in this text. The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high . The second use condition is to insert a "don't care" state in one or more of the three alarm bytes. The "don't care" code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the "don't care" condition when at logic 1. An alarm will be generated each hour when the "don't care" bits are set in the hours byte. Similarly, an alarm is generated every minute with "don't care" codes in the hours and minute alarm bytes. The "don't care" codes in all three alarm bytes create an interrupt every second. DS12B887 TIME, CALENDAR AND ALARM DATA MODES Table 2 ADDRESS LOCATION 0 1 2 3 4 FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm Hours-12-hr Mode Hours-24-hr Mode 5 Hours Alarm-12-hr Hours Alarm-24-hr 6 7 8 9 Day of the Week Sunday = 1 Date of the Month Month Year DECIMAL RANGE 0-59 0-59 0-59 0-59 1-12 0-23 1-12 0-23 1-7 1-31 1-12 0-99 RANGE BINARY DATA MODE 00-3B 00-3B 00-3B 00-3B 01-0C AM, 81-8C PM 00-17 01-0C AM, 81-8C PM 00-17 01-07 01-1F 01-0C 00-63 BCD DATA MODE 00-59 00-59 00-59 00-59 01-12AM,81-92PM 00-23 01-12AM,81-92PM 00-23 01-07 01-31 01-12 00-99 NONVOLATILE RAM The 114 general purpose nonvolatile RAM bytes are not dedicated to any special function within the DS12B887. They can be used by the processor program as nonvolatile memory and are fully available during the update cycle. have occurred much earlier. As a result, there are cases where the program should clear such earlier initiated interrupts before first enabling new interrupts. When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag bits are set independent of the state of the corresponding enable bit in Register B. The flag bit can be used in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which software can interrogate as necessary. When a flag is set, an indication is given to software that an interrupt event has occurred since the flag bit was last read; however, care should be taken when using the flag bits as they are cleared each time Register C is read. Double latching is included with Register C so that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed. One, two, or three bits can be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no interrupts a re lost. The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the corresponding interrupt enable bit is also set, the IRQ pin is INTERRUPTS The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic interrupt can be selected for rates from 500 ms to 122 s. The update-ended interrupt can be used to indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is described in greater detail in other sections of this text. The processor program can select which interrupts, if any, are going to be used. Three bits in Register B enable the interrupts. Writing a logic 1 to an interruptenable bit permits that interrupt to be initiated when the event occurs. A zero in an interrupt-enable bit prohibits the IRQ pin from being asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set at an active level, although the interrupt initiating the event may 080895 6/16 DS12B887 asserted low. IRQ is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a one whenever the IRQ pin is being driven low. Determination that the RTC initiated an interrupt is accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the DS12B887. The act of reading Register C clears all active flag bits and the IRQF bit. rupt can be used with software counters to measure inputs, create output intervals, or await the next needed software function. UPDATE CYCLE The DS12B887 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time increments. However, the time countdown chain continues to update the internal copy of the buffer. This feature allows time to maintain accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and calendar information is consistent. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a "don't care" code is present in all three positions. There are three methods that can handle access of the real time clock that avoid any possibility of accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared before leaving the interrupt routine. A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs 244 s later. If a low is read on the UIP bit, the user has at least 244 s before the time/calendar data will be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244 s. The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts that occur at a rate of greater than tBUC allow valid time and date information to be reached at each occurrence of the periodic interrupt. The reads should be complete within 1 ( t PI/ + tBUC) to ensure that data is not read during the 2 OSCILLATOR CONTROL BITS When the DS12B887 is shipped from the factory, the internal oscillator is turned off. This feature prevents the lithium energy cell from being used until it is installed in a system. A pattern of 010 in bits 4 through 6 of Register A will turn the oscillator on and enable the countdown chain. A pattern of 11X will turn the oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4 through 6 keep the oscillator off. SQUARE WAVE OUTPUT SELECTION Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of Figure 1. The first purpose of selecting a divider tap is to generate a square wave output signal on the SQW pin. The RS0-RS3 bits in Register A establish the square wave output frequency. These frequencies are listed in Table 1. The SQW frequency selection shares its 1-of-15 selector with the periodic interrupt generator. Once the frequency is selected, the output of the SQW pin can be turned on and off under program control with the square wave enable bit (SQWE). PERIODIC INTERRUPT SELECTION The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once every 122 s. This function is separate from the alarm interrupt which can be output from once per second to once per day. The periodic interrupt rate is selected using the same Register A bits which select the square wave frequency (see Table 1). Changing the Register A bits affects both the square wave frequency and the periodic interrupt output. However, each function has a separate enable bit in Register B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE bit in Register B. The periodic inter- update cycle. 080895 7/16 DS12B887 UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3 UIP BIT IN REGISTER A tBUC UF BIT IN REGISTER B t PI/ PF BIT IN REGISTER C tPI tPI = Periodic interrupt time interval per Table 1. tBUC = Delay time before update cycle = 244 s. 2 t PI/ 2 REGISTERS The DS12B887 has four control registers which are accessible at all times, even during the update cycle. REGISTER A MSB BIT 7 UIP BIT 6 DV2 BIT 5 DV1 BIT 4 DV0 BIT 3 RS3 BIT 2 RS2 BIT 1 RS1 LSB BIT 0 RS0 only combination of bits that will turn the oscillator on and allow the RTC to keep time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update will occur at 500 ms after a pattern of 010 is written to DV0, DV1, and DV2. RS3, RS2, RS1, RS0 These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic interrupt. The user can do one of the following: 1. Enable the interrupt with the PIE bit; 2. Enable the SQW output pin with the SQWE bit; 3. Enable both at the same time and the same rate; or 4. Enable neither. Table 1 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the RS bits. UIP The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a one, the update transfer will soon occur. When UIP is a zero, the update transfer will not occur for at least 244 s. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is zero. The UIP bit is read only. Writing the SET bit in Register B to a one inhibits any update transfer and clears the UIP status bit. DV0, DV1, DV2 These three bits are used to turn the oscillator on or off and to reset the countdown chain. A pattern of 010 is the 080895 8/16 DS12B887 REGISTER B MSB BIT 7 SET BIT 6 PIE BIT 5 AIE BIT 4 UIE BIT 3 SQWE BIT 2 DM BIT 1 24/12 LSB BIT 0 DSE rate-selection bits RS3 through RS0 is driven out on a SQW pin. When the SQWE bit is set to zero, the SQW pin is held low. SQWE is a read/write bit. DM SET When the SET bit is a zero, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a one, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. SET is a read/write bit. The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD format. The DM bit is set by the program to the appropriate format and can be read as required. A one in DM signifies binary data while a zero in DM specifies Binary Coded Decimal (BCD) data. 24/12 PIE The periodic interrupt enable PIE bit is a read/write bit which allows the Periodic Interrupt Flag (PF) bit in Register C to drive the IRQ pin low. When the PIE bit is set to one, periodic interrupts are generated by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A zero in the PIE bit blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is still set at the periodic rate. PIE is not modified by any internal DS12B887 functions. The 24/12 control bit establishes the format of the hours byte. A one indicates the 24-hour mode and a zero indicates the 12-hour mode. This bit is read/write. DSE The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when DSE is set to one. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a zero. AIE The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a one, permits the Alarm Flag (AF) bit in register C to assert IRQ. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes including a "don't care" alarm code of binary 11XXXXXX. When the AIE bit is set to zero, the AF bit does not initiate the IRQ signal. The internal functions of the DS12B887 do not affect the AIE bit. REGISTER C MSB BIT 7 IRQF BIT 6 PF BIT 5 AF BIT 4 UF BIT 3 0 BIT 2 0 BIT 1 0 LSB BIT 0 0 IRQF The Interrupt Request Flag (IRQF) bit is set to a one when one or more of the following are true: PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 That is, IRQF = (PF * PIE) + (AF * AIE) + (UF * UIE). Any time the IRQF bit is a one, the IRQ pin is driven low. All flag bits are cleared after Register C is read by the program. UIE The Update Ended Interrupt Enable (UIE) bit is a read/ write that enables the Update End Flag (UF) bit in Register C to assert IRQ. The SET bit going high clears the UIE bit. SQWE When the Square Wave Enable (SQWE) bit is set to a one, a square wave signal at the frequency set by the 080895 9/16 DS12B887 PF The Periodic Interrupt Flag (PF) is a read-only bit which is set to a one when an edge is detected on the selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a one independent of the state of the PIE bit. When both PF and PIE are ones, the IRQ signal is active and will set the IRQF bit. The PF bit is cleared by a software read of Register C. BIT 0 THROUGH BIT 3 These are unused bits of the status Register C. These bits always read zero and cannot be written. REGISTER D MSB BIT 7 VRT BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 LSB BIT 0 0 AF A one in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time. If the AIE bit is also a one, the IRQ pin will go low and a one will appear in the IRQF bit. A read of Register C will clear AF. VRT The Valid RAM and Time (VRT) bit is set to the one state by Dallas Semiconductor prior to shipment. This bit is not writable and should always be a one when read. If a zero is ever present, an exhausted internal lithium energy source is indicated and both the contents of the RTC data and RAM data are questionable. UF The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to one, the one in UF causes the IRQF bit to be a one which will assert the IRQ pin. UF is cleared by reading Register C. BIT 6 THROUGH BIT 0 The remaining bits of Register D are not usable. They cannot be written and, when read, they will always read zero. 080895 10/16 DS12B887 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -40C to +70C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. The Dallas Semiconductor DS12B887 built to the highest quality standards and manufactured for long term reliability. All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods. However, standard versions of the DS12B887 are not exposed to environmental stresses, such as burn-in, that some industrial applications require. For specific reliability information on this product, please contact the factory in Dallas at (214) 450-0448. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Power Supply Voltage Input Logic 1 Input Logic 0 SYMBOL VCC VIH VIL MIN 4.5 2.2 -0.3 TYP 5.0 MAX 5.5 VCC+0.3 +0.8 UNITS V V V (0C to 70C) NOTES 1 1 1 DC ELECTRICAL CHARACTERISTICS PARAMETER Power Supply Current Input Leakage I/O Leakage Output @ 2.4V Output @ 0.4V Write Protect Voltage SYMBOL ICC1 IIL ILO IOH IOL VTP 4.0 4.25 -1.0 -1.0 -1.0 MIN TYP 7 (0C to 70C; VCC = 4.5 to 5.5V) MAX 15 +1.0 +1.0 UNITS mA mA mA mA 4.0 4.5 mA V 3 1,4 1 NOTES 2 CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 7 UNITS pF pF (tA = 25C) NOTES 080895 11/16 DS12B887 AC ELECTRICAL CHARACTERISTICS PARAMETER Cycle Time Pulse Width, DS/E Low or RD/WR High Pulse Width, DS/E High or RD/WR Low Input Rise and Fall Time Chip Select Setup Time Before DS, WR, or RD Chip Select Hold Time Read Data Hold Time Write Data Hold Time Muxed Address Valid Time to AS/ ALE Fall Muxed Address Hold Time Delay Time DS/E to AS/ALE Rise Pulse Width AS/ALE High Delay Time, AS/ALE to DS/E Rise Output Data Delay Time From DS/E or RD Data Setup Time IRQ Release from DS SYMBOL tCYC PWEL PWEH tR,tF tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW tIRDS 20 0 10 0 30 10 20 60 40 20 100 MIN 385 150 125 TYP (0C to 70C; VCC = 4.5V to 5.5V) MAX DC UNITS ns ns ns 30 ns ns ns 80 ns ns ns ns ns ns ns 120 ns ns 2 ms 5 NOTES NOTES: 1. All voltages are referenced to ground. 2. All outputs are open. 3. Applies to the AD0-AD7 pins, the IRQ pin,and the SQW pin when each is in the high impedance state. 4. The IRQ pin is open drain. 5. Measured with a load of 50 pf + 1 TTL gate. 080895 12/16 DS12B887 DS12B887 BUS TIMING FOR WRITE CYCLE tCYC ALE (AS PIN) tASD PWASH RD (DS PIN) tASD tASED PWEH WR (R/W PIN) PWEL tCS tCH CS tAHL tASL tDSW tDHW AD0-AD7 080895 13/16 DS12B887 DS12B887 BUS TIMING FOR READ CYCLE tCYC ALE (AS PIN) tASD PWASH tASED PWEH RD (DS PIN) tASD PWEL WR (R/W PIN) tDDR tCS tCH CS tAHL tASL tDHR AD0-AD7 DS12B887 IRQ RELEASE DELAY TIMING DS IRQ tIRDS 080895 14/16 DS12B887 POWER DOWN/POWER UP TIMING VCC 4.50V 3.2V tF tPD tREC tR CS CURRENT SUPPLIED FROM INTERNAL LITHIUM ENERGY CELL DATA RETENTION tDR POWER DOWN/POWER UP TIMING PARAMETER CS at VIH before Power-Down VCC slew from 4.5V to 0V (CS at VIH) VCC slew from 0V to 4.5V (CS at VIH) CS at VIH after Power-Up SYMBOL tPD tF tR tREC MIN 0 300 100 20 200 TYP MAX UNITS ms ms ms ms NOTES (tA = 25C) PARAMETER Expected Data Retention SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES NOTE: The real time clock will keep time to an accuracy of +1 minute per month during data retention time for the period of tDR. WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. 080895 15/16 DS12B887 DS12B887 REAL TIME CLOCK PLUS RAM 24 13 1 A 12 C E F D K 11 EQUAL SPACES AT .100 .010 TNA G J H B PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 24-PIN MIN 1.320 33.53 0.675 17.15 0.345 8.76 0.100 2.54 0.015 0.38 0.110 2.79 0.090 2.29 0.590 14.99 0.008 0.20 0.015 0.38 MAX 1.335 33.91 0.700 17.78 0.370 9.40 0.130 3.30 0.030 0.76 0.140 3.56 0.110 2.79 0.630 16.00 0.012 0.30 0.021 0.53 NOTE: PINS 2, 3, 16, 20, AND 22 ARE MISSING BY DESIGN. 080895 16/16 |
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