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| FUJITSU SEMICONDUCTOR DATA SHEET DS05-20889-1E FLASH MEMORY CMOS 32M (2M x 16) BIT Page Dual Operation MBM29PDS322TE/BE s DESCRIPTION 10/11 The MBM29PDS322TE/BE is 32M-bit, 1.8 V-only Flash memory organized as 2M words of 16 bits each. The device is offered in 63-ball FBGA package. This device is designed to be programmed in system with standard system 1.8 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The device is organized into two banks, Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu's standard 1.8 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. (Continued) s PRODUCT LINE-UP Part No. Ordering Part No. VCC = 2.0 V +0.2 V -0.2 V MBM29PDS322TE/BE 10 100 45 100 35 11 115 45 115 45 Max. Random Address Access Time (ns) Max. Page Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) s PACKAGE 63-ball plastic FBGA (BGA-63P-M01) MBM29PDS322TE/BE 10/11 (Continued) The device provides truly high performance non-volatile Flash memory solution. The device offers fast page access times of 45 ns with random access times of 100 ns and 115 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The page size is 4 words. The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 1.8 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system's microprocessor to read the boot-up firmware from the Flash memory. Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29PDS322TE/BE 10/11 s FEATURES * 0.23 m Process Technology * Simultaneous Read/Write operations (Dual Bank) Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program * High performance Page Mode 45 ns maximum page access time (100 ns random access time) 4 words Page Size * Single 1.8 V read, program, and erase Minimized system level power requirements * Compatible with JEDEC-standard commands Use the same software commands as E2PROMs. * Compatible with JEDEC-standard world-wide pinouts 63-ball FBGA (Package suffix: PBT) * Minimum 100,000 program/erase cycles * Sector erase architecture Eight 4 Kword and sixty-three 32 Kword sectors in word mode Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture T = Top sector B = Bottom sector * Hidden ROM (Hi-ROM) region 64 Kbyte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status. At VIH, allows removal of boot sector protection. At VACC, increases program performance. * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector. * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address. * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device. * Sector group protection Hardware method disables any combination of sector groups from program or erase operations. * Sector Group Protection Set function by Extended sector group protection command * Fast Programming Function by Extended Command * Temporary sector group unprotection Temporary sector group unprotection via the RESET pin. 3 MBM29PDS322TE/BE 10/11 Table 1: MBM29PDS322TE/BE Device Bank Division Bank 1 Bank 2 Organization Megabits Sector Sizes Megabits Sector Sizes x 16 Eight 4 Kword, seven 32 Kword Device Part Number MBM29PDS322TE/BE 4 Mbit 28 Mbit Fifty-six 32 Kword 4 MBM29PDS322TE/BE 10/11 s PIN ASSIGNMENT (TOP VIEW) A8 N.C.* B8 N.C.* (Marking Side) L8 N.C.* M8 N.C.* A7 N.C.* B7 N.C.* C7 A13 D7 A12 E7 A14 F7 A15 G7 A16 H7 N.C. J7 DQ15 K7 VSS L7 N.C.* M7 N.C.* C6 A9 D6 A8 E6 A10 F6 A11 G6 DQ7 H6 DQ14 J6 DQ13 K6 DQ6 C5 WE D5 RESET E5 N.C. F5 A19 G5 DQ5 H5 DQ12 J5 VCC K5 DQ4 C4 RY/BY D4 WP/ACC E4 A18 F4 A20 G4 DQ2 H4 DQ10 J4 DQ11 K4 DQ3 C3 A7 D3 A17 E3 A6 F3 A5 G3 DQ0 H3 DQ8 J3 DQ9 K3 DQ1 A2 N.C.* C2 A3 D2 A4 E2 A2 F2 A1 G2 A0 H2 CE J2 OE K2 VSS L2 N.C.* M2 N.C.* A1 N.C.* B1 N.C.* L1 N.C.* M1 N.C.* (BGA-63P-M01) *: Peripheral balls on each corner are shorted together via the substrate but not connected to the die. 5 MBM29PDS322TE/BE 10/11 s PIN DESCRIPTION Table 2: MBM29PDS322TE/BE Pin Configuration Pin name A20 to A0 DQ15 to DQ0 CE OE WE RY/BY RESET WP/ACC N.C. VSS VCC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Hardware Write Protection/Program Acceleration No Internal Connection Device Ground Device Power Supply Function 6 MBM29PDS322TE/BE 10/11 s BLOCK DIAGRAM VCC VSS Y-Gating Bank 2 address A20 to A0 Cell Matrix (Bank 2) X-Decoder RESET WE CE OE WP/ACC DQ15 to DQ0 State Control & Command Register RY/BY Status Control DQ15 to DQ0 X-Decoder Cell Matrix (Bank 1) Bank 1 address Y-Gating 16 DQ15 to DQ0 CE OE WE RESET WA/ACC RY/BY s LOGIC SYMBOL 21 A20 to A0 7 MBM29PDS322TE/BE 10/11 s DEVICE BUS OPERATION Operation Auto-Select Manufacturer Code *1 Auto-Select Device Code *1 Extended Auto-Select Device Code *1 Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Group Protection *2, *4 Verify Sector Group Protection *2, *4 Temporary Sector Group Unprotection *5 Reset (Hardware) / Standby Boot Block Sector Write Protection *6 Table 3: MBM29PDS322TE/BE User Bus Operations DQ15 to CE OE WE A0 A1 A2 A3 A6 A9 DQ0 L L L L H L L L L X X X L L L L X H H VID L X X X H X X X H H H H X H L L H L/H A0 X X A0 L L X X X L L H A1 X X A1 H H X X X L L H A2 X X A2 L L X X X L L H A3 X X A3 L L X X X L L L A6 X X A6 L L X X X VID VID VID A9 X X A9 VID VID X X X Code Code Code DOUT High-Z High-Z DIN X Code X High-Z X RESET H H H H H H H H H VID L X WP/ ACC X X X X X X X X X X X L Legend: L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See Table 3. *2: Refer to section on Sector Group Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC must be between the minimum and maximum of the operation range. *5: It is also used for the extended sector group protection. *6: Protect "outermost" 2 x 4 Kwords of the boot block sectors. 8 MBM29PDS322TE/BE 10/11 Table 4: MBM29PDS322TE/BE Command Definitions Command Sequence Read/Reset Read/Reset Auto select Program Chip Erase Sector Erase Word Word Word Word Word Word Fourth Bus Bus First Bus Second Bus Third Bus Fifth Bus Sixth Bus Write Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Cycles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 4 6 6 1 1 3 2 2 4 1 3 4 6 4 XXXh F0h 555h 555h 555h 555h 555h BA BA 555h -- -- 55h 55h 55h 55h 55h -- -- 55h PD *4 F0h 60h -- 55h 55h 55h 55h -- 555h (BA) 555h 555h 555h 555h -- -- 555h -- -- SPA -- 555h 555h 555h (HRBA) -- F0h 90h A0h 80h 80h -- -- 20h -- -- 40h -- 88h A0h 80h -- RA -- PA 555h 555h -- -- -- -- -- SPA -- -- (HRA) PA 555h -- RD -- PD -- -- -- -- -- -- -- -- 55h 55h -- -- -- -- -- -- -- -- -- 55h -- -- -- -- -- 555h SA -- -- -- -- -- -- -- -- -- HRA -- -- -- -- -- 10h 30h -- -- -- -- -- -- -- -- -- 30h -- AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh B0h 30h -- -- AAh 2AAh AAh 2AAh -- -- -- -- -- SD -- -- PD -- -- -- -- -- -- -- -- -- Erase Suspend Erase Resume Set to Fast Mode Fast Program *1 Word Word AAh 2AAh PA XXXh A0h BA Reset from Word Fast Mode *1 Extended Sector Group Protection *2 90h XXXh SPA -- Word Word Word Word Word Word XXXh 60h (BA) 55h 555h 555h 555h 555h 98h Query Hi-ROM Entry Hi-ROM Program *3 Hi-ROM Erase *3 Hi-ROM Exit *3 AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh -- 555h 90h XXXh 00h *1: This command is valid while Fast Mode. *2: This command is valid while RESET = VID. *3: This command is valid while Hi-ROM mode. *4: The data "00h" is also acceptable. Note 1.Address bits A20 to A12 = X = "H" or "L" for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA). 2.Bus operations are defined in Table 8. 3.RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. 9 MBM29PDS322TE/BE 10/11 Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A20 to A15) 4.RD = Data read from location RA during the read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. 5.SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6.HRA = Address of the Hi-ROM area 29PDS322TE (Top Boot Type)Word Mode:1F8000h to 1FFFFFh 29PDS322BE (Bottom Boot Type)Word Mode:000000h to 007FFFh 7.HRBA =Bank Address of the Hi-ROM area 29PDS322TE (Top Boot Type):A20 = A19 = A18 = A17 = A16 = A15 = 1 29PDS322BE (Bottom Boot Type):A20 = A19 = A18 = A17 = A16 = A15 = 0 8.The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A10 to A0 9.Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. SA = 10 MBM29PDS322TE/BE 10/11 Table 5.1 MBM29PDS322TE Sector Group Protection Verify Autoselect Codes Type Manufacture's Code Device Code Word Extended Device Word Code *3 Word Sector Group Protection A20 to A12 BA *2 A6 VIL VIL VIL VIL VIL A3 VIL VIL VIH VIH VIL A2 VIL VIL VIH VIH VIL A1 VIL VIL VIH VIH VIH A0 VIL VIH VIL VIH VIL Code (HEX) 04h 227Eh 2206h 2201h 01h*1 BA*2 BA*2 BA *2 Sector Group Addresses *1:Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2:When VID is applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous operation unable to be executed. Consequently, specifying the bank address is not demanded. However, the bank address needs to be indicated when Autoselect mode is read out at command mode; because then it becomes OK to activate simultaneous operation. *3:A read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that there will require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh. Table 5.2 Expanded Autoselect Code Table Type Manufacturer's Code Device Code Extended Device Code Sector Group Protection (W): Word mode Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h (W) 227Eh (W) 2206h (W) 2201h 01h 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 11 MBM29PDS322TE/BE 10/11 Table 5.3 MBM29PDS322BE Sector Group Protection Verify Autoselect Codes A6 A3 A2 A1 A0 Code (HEX) A20 to A12 BA*2 BA *2 *2 Type Device Code Manufacture's Code Word Extended Device Word Code *3 Word Sector Group Protection VIL VIL VIL VIL VIL VIL VIL VIH VIH VIL VIL VIL VIH VIH VIL VIL VIL VIH VIH VIH VIL VIH VIL VIH VIL 04h 227Eh 2206h 2200h 01h*1 BA BA*2 Sector Group Addresses *1:Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2:When VID is applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous operation unable to be executed. Consequently, specifying the bank address is not demanded. However, the bank address needs to be indicated when Autoselect mode is read out at command mode; because then it becomes OK to activate simultaneous operation. * 3:A read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that there will require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh. Table 5.4 Expanded Autoselect Code Table Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 1 Type Manufacturer's Code Device Code (W) 227Eh (W) 2206h Extended Device Code (W) 2200h Sector Group Protection (W): Word mode 01h 12 MBM29PDS322TE/BE 10/11 s FLEXIBLE SECTOR-ERASE ARCHITECTURE Table 6.1 Sector Address Tables (MBM29PDS322TE) Sector Address Sector Bank Sector A20 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 Bank 2 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Bank Address A19 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x16) x Address Range 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh (Continued) 13 MBM29PDS322TE/BE 10/11 (Continued) Sector Address Bank Sector A20 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 Bank 2 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 Bank 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bank Address A19 A18 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A16 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 (x16) x Address Range 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F8FFFh 1F9000h to 1F9FFFh 1FA000h to 1FAFFFh 1FB000h to 1FBFFFh 1FC000h to 1FCFFFh 1FD000h to 1FDFFFh 1FE000h to 1FEFFFh 1FF000h to 1FFFFFh MBM29PDS322TE Top Boot Sector Architecture 14 MBM29PDS322TE/BE 10/11 Table 6.2 Sector Address Tables (MBM29PDS322BE) Sector Address Sector Bank Sector A20 SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 Bank 2 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bank Address A19 A18 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 A17 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x16) x Address Range 1F8000h to 1FFFFFh 1F0000h to 1F7FFFh 1E8000h to 1EFFFFh 1E0000h to 1E7FFFh 1D8000h to 1DFFFFh 1D0000h to 1D7FFFh 1C8000h to 1CFFFFh 1C0000h to 1C7FFFh 1B8000h to 1BFFFFh 1B0000h to 1B7FFFh 1A8000h to 1AFFFFh 1A0000h to 1A7FFFh 198000h to 19FFFFh 190000h to 197FFFh 188000h to 18FFFFh 180000h to 187FFFh 178000h to 17FFFFh 170000h to 177FFFh 168000h to 16FFFFh 160000h to 167FFFh 158000h to 15FFFFh 150000h to 157FFFh 148000h to 14FFFFh 140000h to 147FFFh 138000h to 13FFFFh 130000h to 137FFFh 128000h to 12FFFFh 120000h to 127FFFh 118000h to 11FFFFh 110000h to 117FFFh 108000h to 10FFFFh 100000h to 107FFFh 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh (Continued) 15 MBM29PDS322TE/BE 10/11 (Continued) Sector Address Bank Sector A20 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 Bank 2 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 Bank 1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank Address A19 A18 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 (x16) x Address Range 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh MBM29PDS322BE Bottom Boot Sector Architecture 16 MBM29PDS322TE/BE 10/11 Table 7.1 Sector Group Address Table (MBM29PDS322TE) (Top Boot Block) A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 1 1 X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 X X X SA60 to SA62 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59 X X X SA1 to SA3 X X X SA0 Sector Group SGA0 17 MBM29PDS322TE/BE 10/11 Table 7.2 Sector Group Address Table (MBM29PDS322BE) (Bottom Boot Block) A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 1 1 X X X X X X X X X X X X X X 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 X X X SA70 X X X SA67 to SA69 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 X X X SA8 to SA10 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 18 MBM29PDS322TE/BE 10/11 s FUNCTIONAL DESCRIPTION Simultaneous Operation The device has feature, which is capable of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank selection can be selected by bank address (A20 to A15) with zero latency. The device has two banks which contain Bank 1 (4 KW x eight sectors, 32 KW x seven sectors) and Bank 2 (32 KW x fifty-six sectors). The simultaneous operation can not execute multi-function mode in the same bank. Table 8 shows the possible combinations for simultaneous operation. (Refer to Figure 12 Back-to-Back Read/Write Timing Diagram.) Table 8 Simultaneous Operation Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode * Case 1 2 3 4 5 6 7 Bank 2 Status Read mode Autoselect mode Program mode Erase mode * Read mode Read mode Read mode *: An erase operation may also be suspended to read from or program to a sector not being erased. Read Mode The device has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used as the gate data to the output pins if a device is selected. Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time (tOE) is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from "H" or "L". Page Mode Read The device is capable of fast Page mode read operation. This mode provides faster read access speed for random locations within a page. The Page size of the device is 4 words, within the appropriate Page being selected by the higher address bits A20 to A2 and the LSB bits A1 and A0 within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is equal to tACC and subsequent Page read access (as long as the locations specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast Page mode accesses are obtained by keeping A20 to A2 constant and changing A1 and A0 to select the specific word, within that page. See Figure 5.4 for timing specifications. 19 MBM29PDS322TE/BE 10/11 Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition, the current consumed is less than 5 A Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L"). Under this condition the current consumed is less than 5 A Max. Once the RESET pin is taken high, the device requires tRH as wake up time for outputs to be valid for read access. In the standby mode, the outputs are in the high impedance state, independently of the OE input. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption. To activate this mode, the device automatically switches themselves to low power mode when the device addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 50 A (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically, and the device reads the data for changed addresses. Output Disable With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (10.0 V to 11.0 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are DON'T CARES except A6, A3, A2, A1, and A0. (See Table 3.) The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 4. (Refer to Autoselect Command section.) In the command Autoselect mode, the bank addresses BA; (A20 to A12) must point to a specific bank during the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while array data can be read from the other bank. A read cycle from address (BA)00h returns the manufacturer's code (Fujitsu = 04h). And a read cycle from address (BA)01h, (BA)0Eh to (BA)0Fh returns the device code. (See Tables 5.1 to 5.4.) In case of applying VID on A9, since both Bank 1 and Bank 2 enter Autoselect mode, the simultaneous operation can not be executed. 20 MBM29PDS322TE/BE 10/11 Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The device features hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (See Table 7.) The sector group protection feature is enabled using programming equipment at the user's site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. Tables 6.1 and 6.2 define the sector address for each of the seventy one (71) individual sectors, and tables 7.1 and 7.2 define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See Figures 16 and 24 for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the device will produce "0" for unprotected sector. In this mode, the lower order addresses, except for A0, A1, A2, A3, and A6 are DON'T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical "1" at DQ0 for a protected sector group. See Tables 5.1 to 5.4 for Autoselect codes. Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to Figures 17 and 25. Extended Sector Group Protection In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60h). A sector group is 21 MBM29PDS322TE/BE 10/11 typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output is logical "0", please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to the Figures 18 and 26.) RESET Hardware Reset The device may be reset by driving the RESET pin to VIL. The RESET pin vs. a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional "tRH" before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 14 for the timing diagram. Refer to Temporary Sector Group Unprotection for additional functionality. Boot Block Sector Protection The Write Protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two "outermost" 4K word boot sectors independently of whether those sectors are protected or unprotected using the method described in "Sector Protection/Unprotection". The two outermost 4K word boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (MBM29PDS322TE: SA69 and SA70, MBM29PDS322BE: SA0 and SA1) If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 4K word boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector protection/unprotection". Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See Figure 19. 22 MBM29PDS322TE/BE 10/11 s COMMAND DEFINITIONS The device operations are selected by writing specific address and data sequences into the command register. Some commands require Bank Address (BA) input. When command sequences are inputted to bank being read, the commands have priority over reading. Table 4 defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover, both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by firstly writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and actual data of memory cell can be read from the another bank. Following the command write, a read cycle from address (BA)00h retrieves the manufacture code of 04h. A read cycle at address (BA)01h returns 7Eh to indicate that this device uses extended device code. The successive read cycle from (BA)0Eh to (BA)0Fh returns this extended device code for this device. (See Tables 5.1 to 5.4.) The sector state (protection or unprotection) will be informed by address (BA)02h. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See Table 3.) The manufacture and device codes can be allowed to read from selected bank. To read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read. If the software (program code) for Autoselect command is stored into the Flash memory, the device and manufacture codes should be read from the other bank which doesn't contain the software. To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, writing Read/Reset command sequence must precede the Autoselect command. 23 MBM29PDS322TE/BE 10/11 Word Programming The device is programmed on a word-by-word basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 9, Hardware Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Figure 20 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 24 MBM29PDS322TE/BE 10/11 Sector Erase Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table4. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70). Sector erase does not require the user to program the device prior to erase. The device automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The sector erase begins after the "tTOW" time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform. Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 25 MBM29PDS322TE/BE 10/11 Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Extended Command (1) Fast Mode The device has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to the Figure 27.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to the Figure 27.) 26 MBM29PDS322TE/BE 10/11 Hidden ROM (Hi-ROM) Region The Hi-ROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Hi-ROM region is 32 Kwords in length and is stored at the same address as the 4 KW x8 sectors. The MBM29PDS322TE occupies the address of the word mode 1F8000h to 1FFFFFh and the MBM29PDS322BE type occupies the address of the word mode 000000h to 007FFFh. After the system has written the Enter HiROM command sequence, the system may read the Hi-ROM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the Hi-ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. When reading the Hi-ROM region, either change addresses or change CE pin from "H" to "L". The same procedure should be taken (changing addresses or CE pin from "H" to "L") after the system issues the Exit Hi-ROM command sequence to read actual data of memory cell. Hidden ROM (Hi-ROM) Entry Command The device has a Hidden ROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. Hidden ROM area is 32 K words and in the same address area as 4 KW sector. The address of top boot is 1F8000h to 1FFFFFh at word mode and the bottom boot is 000000h to 007FFFh at word mode. These areas are normally the boot block area (4 KW x8 sector). Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called Hidden ROM mode when the Hidden ROM area appears. Sector other than the boot block area could be read during Hidden ROM mode. Read/program/erase of the Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to exit the Hidden ROM mode. The bank address of the Hidden ROM should be set on the third cycle of this reset command sequence. Hidden ROM (Hi-ROM) Program Command To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden ROM mode. This command is the same as the program command in usual except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. It is necessary to pay attention to the address to be programmed. If the address other than the Hidden ROM area is selected to program, data of the address will be changed. Hidden ROM (Hi-ROM) Erase Command To erase the Hidden ROM area, write the Hidden ROM erase command sequence during Hidden ROM mode. This command is same as the sector erase command in the past except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. It is necessary to pay attention to the sector address to be erased. If the sector address other than the Hidden ROM area is selected, the data of the sector will be changed. 27 MBM29PDS322TE/BE 10/11 Hidden ROM (Hi-ROM) Protect Command There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup command(60h), set the sector address in the Hidden ROM area and (A6, A3, A2,A1, A0) = (0,0,0,1,0), and write the sector group protect command(60h) during the Hidden ROM mode. The same command sequence could be used because, it is the same as the extension sector group protect in the past except that it is in the Hidden ROM mode and it does not apply high voltage to RESET pin. Please refer to "Function Explanation Extended Sector Group Protection" for details of extension sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, set the sector address in the Hidden ROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0), and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address in the Hidden ROM area, and read. When "1" appears on DQ0, the protect setting is completed. "0" will appear on DQ0 if it is not protected. Please apply write pulse again. The same command sequence could be used for the above method because other than the Hidden ROM mode, it is the same as the sector group protect previously mentioned. Please refer to "Function Explanation Sector Group Protection" for details of the sector group protect setting. Other sector group will be effected if the address other than those for Hidden ROM area is selected for the sector group address, so please be careful. Once it is protected, protection can not be cancelled, so please pay the closest attention. Write Operation Status Detailed in Table 9 are all the status flags that can determine the status of the bank for the current mode operation. The read operation from the bank which doesn't operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase and which are not. The status flag is not output from bank (non-busy bank) which doesn't execute Embedded Algorithm. For example, there is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] 28 MBM29PDS322TE/BE 10/11 Table 9 Hardware Sequence Flags DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 Status DQ6 Toggle Toggle 1 Data Toggle Toggle Toggle Toggle DQ5 0 0 0 DQ3 0 1 0 DQ2 1 Toggle * Toggle Data 1* 1 N/A N/A Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Suspended Mode Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspend(Non-Erase Suspended Sector) ed Mode In Progress Data Data 0 1 1 1 0 0 1 0 *: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. Note 1.DQ0 and DQ1 are reserve pins for future use. 2.DQ4 is Fujitsu internal use. 29 MBM29PDS322TE/BE 10/11 DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read device will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read device will produce a "1" on DQ7. The flowchart for Data Polling (DQ7) is shown in Figure 23. For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected sectors. Otherwise, the status may be invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 s, then the bank returns to read mode. Once the Embedded Algorithm operation is close to completion, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that device is driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See Table 9.) See Figure 10 for the Data Polling timing specifications and diagrams. DQ6 Toggle Bit I The device also features the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will results in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 1 s and then stop toggling with data unchanged. In erase, device will erase all selected sectors except for ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data unchanged. Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank is actively erased (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6 to toggle. To operate toggle bit function properly, CE or OE must be high when bank address is changed. 30 MBM29PDS322TE/BE 10/11 See Figure 11 for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of device under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 8. The DQ5 failure condition may also appear if a user tries to program a non blank location without pre-erase. In this case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never read valid data on DQ7 bit and DQ6 never stop toggling. Once device has exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since device was incorrectly used. If this occurs, reset device with command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence sector erase time-out will begin. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun.If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See Table 9: Hardware Sequence Flags. DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also and. Furthermore, DQ2 can also be used to determine which sector is being erased. When device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed. 31 MBM29PDS322TE/BE 10/11 Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to Figure 23.) Table 10 Toggle Bit Status DQ6 DQ7 DQ7 0 1 DQ7 Toggle Toggle 1 Toggle Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program Note DQ2 1 Toggle (Note) Toggle 1 (Note) Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from nonerase suspend sector address will indicate logic "1" at the DQ2 bit. RY/BY Ready/Busy The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded Algorithms are either in progress or has been completed. If output is low, device is busy with either a program or erase operation. If output is high, device is ready to accept any read/write or erase operation. If the device is placed in an Erase Suspend mode, RY/BY output will be high. During programming, RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin will indicate a busy condition during RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. 32 MBM29PDS322TE/BE 10/11 Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up device automatically resets internal state machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. Power On/Off Timing The RESET pin must be held low during VCC ramp up to insure that device power up correctly. (Refer to Figure 5.3.) Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 33 MBM29PDS322TE/BE 10/11 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, and RESET (Note 1) Power Supply Voltage (Note 1) A9, OE, and RESET (Note 2) WP/ACC (Note 3) Symbol Tstg TA VIN, VOUT VCC VIN VACC Rating Min. -55 -40 -0.5 -0.5 -0.5 -0.5 Max. +125 +85 VCC+0.5 +3.0 +11.5 +10.5 Unit C C V V V V Notes: 1.Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns. 2.Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCC) does not exceed +9.0V. Maximum DC input voltage on A9, OE and RESET pins is +11.5 V which may positive overshoot to +12.5 V for periods of up to 20 ns. 3.Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may positive overshoot to +12.0 V for periods of up to 20ns when Vcc is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING RANGES Parameter Ambient Temperature Power Supply Voltage Symbol TA VCC Part No. MBM29PDS322TE/BE 10/11 MBM29PDS322TE/BE 10/11 Value Min. -40 +1.8 Max. +85 +2.2 Unit C V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 34 MBM29PDS322TE/BE 10/11 s MAXIMUM OVERSHOOT / UNDERSHOOT 0.2 x VCC -0.5 V -2.0 V 20 ns 20 ns 20 ns Figure 1 Maximum Undershoot Waveform VCC + 2.0 V VCC + 0.5 V 0.8 x VCC 20 ns 20 ns 20 ns Figure 2 Maximum Overshoot Waveform 1 +12.5 V +11.5 V VCC + 0.5 V 20 ns 20 ns 20 ns Note: This waveform is applied for A9, OE and RESET Figure 3 Maximum Overshoot Waveform 2 35 MBM29PDS322TE/BE 10/11 s ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current VCC Active Current *1 VCC Active Current *2 VCC Current (Standby) VCC Current (Standby, Reset) VCC Current (Automatic Sleep Mode) *3 VCC Active Current *5 (Read-While-Program) VCC Active Current *5 (Read-While-Erase) VCC Active Current (Erase-Suspend-Program) VCC Active Current (Intra-Page Read) WP/ACC Accelerated Program Current Input Low Level Input High Level Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration *4 Voltage for Autoselect and Sector Protection (A9, OE, RESET) *4 Output Low Voltage Level Output High Voltage Level Symbol ILI ILO ILIT ICC1 ICC2 ICC3 ICC4 Conditions VIN = VSS to VCC, VCC = VCC Max. VOUT = VSS to VCC, VCC = VCC Max. VCC = VCC Max. A9, OE, RESET = 11.0 V CE = VIL, OE = VIH, f = 8 MHz CE = VIL, OE = VIH, f = 1 MHz CE = VIL, OE = VIH VCC = VCC Max., CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max.,WE/ACC = VCC 0.3 V, RESET = VSS 0.3 V VCC = VCC Max., CE = VSS 0.3 V, RESET = VCC 0.3 V VIN = VCC 0.3 V or VSS 0.3 V CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH, f = 20 MHz VCC = VCC Max. WP/ACC = VACC Max. -- -- -- Value Min. -1.0 -1.0 -- -- -- -- -- -- Max. +1.0 +1.0 35 21 3 30 5 5 Unit A A A mA mA mA A A A mA mA mA mA mA V V V ICC5 -- 5 ICC6 ICC7 ICC8 ICC9 IACC VIL VIH VACC -- -- -- -- -- -0.5 0.8x VCC 8.5 55 55 35 5 20 0.2x VCC VCC+0.3 12.5 VID VOL VOH -- IOL = 100 A, VCC = VCC Min. IOH = -100 A 10.0 -- VCC-0.1 11.0 0.1 -- V V V *1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC is active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: Applicable for only VCC applying. *5: Embedded Algorithm (program or erase) is in progress. (@5 MHz) 36 MBM29PDS322TE/BE 10/11 2. AC Characteristics * Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Page Read Cycle Time Page Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode Symbol JEDEC tAVAV tAVQV -- -- tELQV tGLQV tEHQZ tGHQZ tAXQX -- Standard tRC tACC tPRC tPACC tCE tOE tDF tDF tOH tREADY -- CE = VIL OE = VIL -- CE = VIL OE = VIL OE = VIL -- -- -- -- -- Value(Note) Conditions 100 45 0 10 100 45 100 35 30 30 20 115 45 0 11 115 45 115 45 30 30 20 Unit ns ns ns ns ns ns ns ns ns s Min. Max. Min. Max. Note: Test Conditions: Output Load: CL = 50 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 2.0 V Timing measurement reference level Input: 1.0 V Output: 1.0 V Device Under Test CL Figure 4 Test Conditions 37 MBM29PDS322TE/BE 10/11 * Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Read Hold Time Toggle and Data Polling CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Programming Operation Sector Erase Operation *1 VCC Setup Time Rise Time to VID * 2 3 Symbol JEDEC tAVAV tAVWL -- tWLAX -- tDVWH tWHDX -- -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- 2 Value 10 tWC tAS 100 0 15 60 0 60 0 0 10 20 20 0 0 0 0 0 0 60 60 60 60 50 500 500 4 100 4 16 1 115 0 15 60 0 60 0 0 10 20 20 0 0 0 0 0 0 60 60 60 60 50 500 500 4 100 4 11 16 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns s s s Standard Min. Typ. Max. Min. Typ. Max. tASO tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP Rise Time to VACC * Voltage Transition Time *2 Write Pulse Width *2 OE Setup Time to WE Active * -- (Continued) 38 MBM29PDS322TE/BE 10/11 (Continued) Parameter CE Setup Time to WE Active *2 Recover Time From RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time Power On / Off Time -- -- -- -- -- -- -- -- -- Symbol JEDEC Value 10 4 0 500 200 -- -- 50 -- -- -- -- -- -- -- -- -- -- -- 20 100 -- -- -- -- 90 90 4 0 500 200 -- -- 50 -- -- 11 -- -- -- -- -- -- -- -- -- -- -- -- -- 90 115 -- 20 115 Unit s ns ns ns ns ns s s ns Standard Min. Typ. Max. Min. Typ. Max. tCSP tRB tRP tRH tBUSY tEOE tTOW tSPD tPS *1: This does not include the preprogramming time. *2: This timing is for Sector Group Protection operation. *3: This timing is for Accelerated Program operation. 39 MBM29PDS322TE/BE 10/11 s ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Word Programming Time Chip Programming Time Program/Erase Cycle FBGA PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Condition Value Typ. TBD TBD TBD TBD Max. TBD TBD TBD TBD Unit pF pF pF pF Limits Min. -- -- -- 100,000 Typ. 1 16 -- -- Max. 10 360 100 -- Unit s s s cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead -- Note: Test conditions TA = 25C, f = 1.0 MHz 40 MBM29PDS322TE/BE 10/11 s TIMING DIAGRAM * Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L": Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State tRC Address tACC Addresses Stable CE tOE tDF OE tOEH WE tCE High-Z tOH High-Z Outputs Output Valid Figure 5.1 Read Operation Timing Diagram 41 MBM29PDS322TE/BE 10/11 tRC Address tACC Address Stable CE tRH tRP tRH tCE RESET tOH High-Z Outputs Outputs Valid Figure 5.2 Hardware Reset/Read Operation Timing Diagram 42 MBM29PDS322TE/BE 10/11 A2 to A20 Same Page Addresses A0 to A1 Aa tRC tACC Ab tPRC Ac CE tCE OE tOEH tOE tDF WE Output High-Z tPACC tOH Da tPACC tOH Db tOH Dc Figure 5.3 Page Read Operation Timing Diagram 43 MBM29PDS322TE/BE 10/11 3rd Bus Cycle Data Polling PA tAS tAH PA tRC Address 555h tWC CE tCS tCH tCE OE tWP tGHWL tWPH tWHWH1 tOE WE tDS tDH tOH PD DQ7 DOUT DOUT Data A0h Notes: 1.PA is address of the memory location to be programmed. 2.PD is data to be programmed at word address. 3.DQ7 is the output of the complement of the data written to the device. 4.DOUT is the output of the data written to the device. 5.Figure indicates last two bus cycles out of four bus cycle sequence. Figure 6 Alternate WE Controlled Program Operation Timing Diagram 44 MBM29PDS322TE/BE 10/11 3rd Bus Cycle Data Polling PA tAS tAH PA Address 555h tWC WE tWS tWH OE tCP tCPH tWHWH1 tGHEL CE tDS tDH Data A0h PD DQ7 DOUT Notes: 1.PA is address of the memory location to be programmed. 2.PD is data to be programmed at word address. 3.DQ7 is the output of the complement of the data written to the device. 4.DOUT is the output of the data written to the device. 5.Figure indicates last two bus cycles out of four bus cycle sequence. Figure 7 Alternate CE Controlled Program Operation Timing Diagram 45 MBM29PDS322TE/BE 10/11 Address 555h tWC 2AAh tAH 555h 555h 2AAh SA * tAS CE tCS tCH OE tGHWL tWP tWPH WE tDS tDH Data tVCS AAh 55h 80h AAh 55h 10h/ 30h VCC *: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase. Figure 8 Chip/Sector Erase Operation Timing Diagram 46 MBM29PDS322TE/BE 10/11 CE tCH tOE tDF OE tOEH WE tCE * DQ7 Data DQ7 DQ7 = Valid Data High-Z tWHWH1 or 2 DQ6 to DQ0 Data tBUSY DQ6 to DQ0 = Output Flag tEOE DQ6 to DQ0 Valid Data High-Z RY/BY *: DQ7 = Valid Data (The device has completed the Embedded operation). Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram 47 MBM29PDS322TE/BE 10/11 CE tOEH WE tOES OE tDH Data (DQ7 to DQ0) DQ6 = Toggle DQ6 = Toggle * DQ6 = Stop Toggle tOE DQ7 = DQ0 Data Valid DQ6 *: DQ6 stops toggling (The device has completed the Embedded operation). Figure 10 Toggle Bit I during Embedded Algorithm Operation Timing Diagram 48 MBM29PDS322TE/BE 10/11 Read tRC Command tWC BA2 (555h) tAH Read tRC BA1 tACC tCE Command tWC BA2 (PA) Read tRC BA1 Read tWC BA2 (PA) tAS Address BA1 tAS tAHT CE tOE tCEPH OE tGHWL tWP tOEH tDF WE tDS Valid Output Valid Input (A0h) tDH tDF Valid Output Valid Input (PD) Valid Output DQ Status Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1. BA2: Address of Bank 2. Figure 11 Bank-to-Bank Read/Write Timing Diagram Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE Erase Suspend Read DQ6 DQ2 Toggle DQ2 and DQ6 with OE Note: DQ2 is read from the erase-suspended sector. Figure 12 DQ2 vs. DQ6 49 MBM29PDS322TE/BE 10/11 CE The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY Figure 13 RY/BY Timing Diagram during Program/Erase Operation Timing Diagram WE RESET tRP tRB RY/BY tREADY Figure 14 RESET, RY/BY Timing Diagram 50 MBM29PDS322TE/BE 10/11 tPS tPS RESET VCC 0V VIH 1.8 V 1.8 V Address Valid Data In Data Valid Data Out tRH tACC Figure 15 Power On / Off Timing Diagram 51 MBM29PDS322TE/BE 10/11 A20, A19, A18 A17, A16, A15 A14, A13, A12 SPAX SPAY A6, A3, A2, A0 A1 VID VIH A9 VID VIH OE tVLHT tVLHT tWPP tVLHT tVLHT WE tOESP CE tCSP Data tVCS tOE 01h VCC SPAX: Sector Group Address for initial sector SPAY: Sector Group Address for next sector Figure 16 Sector Group Protection Timing Diagram 52 MBM29PDS322TE/BE 10/11 VCC tVCS tVIDR tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period Figure 17 Temporary Sector Group Unprotection Timing Diagram 53 MBM29PDS322TE/BE 10/11 VCC tVCS RESET tVIDR tVLHT tWC tWC SPAX SPAX SPAY Address A6, A3, A2, A0 A1 CE OE tWP TIME-OUT WE Data 60h 60h 40h tOE 01h 60h SPAX: Sector Group Address to be protected SPAY: Next Sector Group Address to be protected TIME-OUT: Time-Out window = 250 s (Min.) Figure 18 Extended Sector Group Protection Timing Diagram 54 MBM29PDS322TE/BE 10/11 VCC tVCS tVACCR tVLHT VACC VIH WP/ACC CE WE tVLHT Program or Erease Command Sequence tVLHT RY/BY Acceleration period Figure 19 Accelerated Program Timing Diagram 55 MBM29PDS322TE/BE 10/11 s FLOW CHARTS EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling Embedded Program Algorithm in program No Verify Data ? Yes Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Figure 20 Embedded ProgramTM Algorithm 56 MBM29PDS322TE/BE 10/11 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling Embedded Erase Algorithm in progress No Data = FFh ? Yes Erasure Completed Chip Erase Command Sequence (Address/Command): 555h/AAh Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h Sector Address /30h Sector Address /30h Sector Address /30h 555h/10h Additional sector erase commands are optional. Figure 21 Embedded EraseTM Algorithm 57 MBM29PDS322TE/BE 10/11 Start Read Byte (DQ7 to DQ0) Addr. = VA Yes DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA VA=Address for programming =Any of the sector address within the sector being erased during sector erase or multiple sector erases operation =Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. DQ7 = Data? * No Fail Yes Pass *: DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Figure 22 Data Polling Algorithm 58 MBM29PDS322TE/BE 10/11 Start Read DQ7 to DQ0 Addr. = VA *1 Read DQ7 to DQ0 Addr. = VA VA=Bank address being executed Embedded Algorithm. Toggle Bit = Toggle? Yes No DQ5 = 1? Yes Read DQ7 to DQ0 Twice Addr. = VA No *1, 2 Toggle Bit = Toggle? Yes No Fail Pass *1: Read toggle bit twice to determine whether or not it is toggling. *2: Recheck toggle bit because it may stop toggling as DQ5 changes to "1". Figure 23 Toggle Bit Algorithm 59 MBM29PDS322TE/BE 10/11 Start ( Setup Sector Group Addr. A20, A19, A18, A17, A16, A15, A14, A13, A12 ) PLSCNT = 1 OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = A3 = A2 = A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 s WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group Addr. = SPA, ( A6 = A3 = A2 =A1 ==VIH )* A0 VIL No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector Group? No Device Failed Remove VID from A9 Write Reset Command Yes Sector Group Protection Completed Figure 24 Sector Group Protection Algorithm 60 MBM29PDS322TE/BE 10/11 Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1: All protected sector groups are unprotected. *2: All previously protected sector groups are protected once again. Figure 25 Temporary Sector Group Unprotection Algorithm 61 MBM29PDS322TE/BE 10/11 Start RESET = VID Wait to 4 s Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Protect Secter Group Write 60h to Secter Address (A6 = A3 = A2 = A0 = VIL, A1 = VIH) Time out 250 s Increment PLSCNT To Verify Sector Group Protection Write 40h to Secter Address (A6 = A3 = A2 = A0 = VIL, A1 = VIH) Read from Sector Group Address (Addr. = SPA, A6 = A3 = A2 = A0 = VIL, A1 = VIH) Setup Next Sector Address No Data = 01h? Yes Protect Other Sector Group? No Remove VID from RESET Write Reset Command Yes No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Device Failed Sector Protection Completed Figure 26 Extended Sector Group Protection Algorithm 62 MBM29PDS322TE/BE 10/11 FAST MODE ALGORITHM Start 555h/AAh 2AAh/55h Set Fast Mode 555h/20h XXXh/A0h Program Address/Program Data In Fast Program Data Polling Verify Data? Yes Increment Address No Last Address? Yes Programming Completed No XXXh/90h Reset Fast Mode XXXh/F0h Figure 27 Embedded ProgramTM Algorithm for Fast Mode 63 MBM29PDS322TE/BE 10/11 s ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29PDS322 T E 10 PBT PACKAGE TYPE PBT =63-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29PDS322 32 Mega-bit (2 M x 16-Bit) CMOS Flash Memory 1.8 V-only Read, Program, and Erase Valid Combinations 10 11 MBM29PDS322TE/BE PBT Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. 64 MBM29PDS322TE/BE 10/11 s PACKAGE DIMENSION 63-pin plastic FBGA (BGA-63P-M01) 11.000.10(.433.004) 1.05 -0.10 +0.15 +.006 (8.80(.346)) (7.20(.283)) (5.60(.220)) 0.80(.031)TYP .041 -.004 (Mounting height) 0.380.10 (.015.004) (Stand off) 8 7 6 7.000.10 (.276.004) (4.00(.157)) (5.60(.220)) 5 4 3 2 1 M L K J HG F E DC B A INDEX BALL 63-O0.450.05 (63-O0.18.002) 0.08(.003) M INDEX AREA 0.10(.004) C 1999 FUJITSU LIMITED B63001S-1C-1 Dimensions in mm (inches). 65 MBM29PDS322TE/BE 10/11 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F0101 (c) FUJITSU LIMITED Printed in Japan |
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