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TQ8016
D0..15 D0..15 Input Buffers 16 x 16 Crosspoint Switch Matrix 64 CONFIGURE (R2) Sixteen 4-Bit Latches 64 (R1) Sixteen 4-Bit Addressable Output Select Latches 4:16 Decoder VCC VEE OA0..3 4 TQ8016 GND Output Buffers O0..15 O0..15
1.3 Gigabit/sec 16x16 Digital ECL Crosspoint Switch
SWITCHING PRODUCTS
RESET LOAD IA0..3 4
The TQ8016 is a 16 x 16 differential digital crosspoint switch capable of handling 1.3 Gbit/s data rate. The high data rate and exceptional signal fidelity is made possible with TriQuint's fully differential Source-Coupled FET Logic (SCFL) standard cells. The symmetrical switching characteristic inherent in differential logic results in low signal skew and crosstalk for maximum signal fidelity. The user can independently configure any switch output to any input, including an input chosen by another output. To configure the switch, the 4-bit output address (OA0..3) is decoded to enable the loading of the 4-bit input selection data (IA0..3) on the rising edge of the LOAD signal. The process is repeated until all desired connections are programmed. By bringing the CONFIGURE signal high, the contents of the Output Select Latches are transferred in parallel to a second row of 4-bit latches (R2), causing the switch reconfiguration. This double row architecture minimizes the time to completely reconfigure the switch since a new set of addresses can be loaded to the Output Select Latches (R1) while the switch is active (transmitting). At the time of reconfiguration, no data drop-out occurs for any output whose input connection does not change. For applications which do not require synchronous configuration of the switch, the LOAD and CONFIGURE inputs may be tied together.
Typical output waveform with all channels driven
Features
* >1.3 Gigabit/sec data rate * Non-blocking architecture * +200 ps delay match (one input to all outputs) * ECL-level data inputs/outputs; CMOS-level control inputs * Low crosstalk * Fully differential data path * Double row of output select latches minimizes reconfiguration time * Available in 132-pin leaded chip carrier
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1
TQ8016
Figure 1. TQ8016 Architecture
16 X 1-BIT MULTIPLEXER
. . . . . .
DATA IN 0 (I0)
16 X 1-BIT MULTIPLEXER
Input Buffers
. . . . . .
DATA OUT 15 (O15) DATA OUT 0 (O0)
DATA IN 15 (I15)
CONFIGURE RESET LOAD 4:16 4 DECODE OUTPUT SELECT ADDRESS (OA0:3)
Configuration Register Program Register
5
4
INPUT ADDRESS (IA0:3)
Table 1. Pin Descriptions
Pin Name
D0-D15 D0-D15 D0-D15 O0-O15 O0-O15 IA0-IA3 OA0-OA3 CONFIGURE
Levels
ECL ECL ECL ECL ECL CMOS CMOS CMOS
Description
Differential Data Inputs Differential Data Inputs Differential Data Inputs Differential Data Outputs Differential Data Outputs Input Address Output Address Switch Reconfiguration
3
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TQ8016
Figure 2. Pinout
VEE NC NC GND D12 D12 GND D13 D13 GND D14 D14 GND D15 D15 GND RESET GND O15 O15 GND O14 O14 GND O13 O13 GND O12 O12 GND NC NC VCC
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121
VCC O11 O11 GND O10 O10 GND O9 O9 GND O8 O8 GND O7 O7 GND NC GND O6 O6 GND O5 O5 GND O4 O4 GND O3 O3 GND O2 O2 VEE
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
TQ8016
Cavity-Down View 132-Pin Ceramic Chip Carrier
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
VEE D11 D11 GND D10 D10 GND D9 D9 GND D8 D8 GND D7 D7 GND NC GND D6 D6 GND D5 D5 GND D4 D4 GND D3 D3 GND D2 D2 VCC
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
Table 1. Pin Descriptions (continued)
Pin Name
RESET
Levels
CMOS
Description
Configures the switch to Broadcast or Pass-Through modes, overwriting existing configurations. Broadcast mode: All output ports are connected to data input port 0. This mode is selected by applying a RESET "high" pulse with CONFIGURE held "low." Pass-through mode: I0 is connected to O0, I1 to O1, and so on. This mode is selected by applying a RESET "high" pulse with CONFIGURE held "high." Loads Input Address Ground Reference Power Supply Power Supply
LOAD GND VEE VCC
CMOS 0 V. -5 V +5 V
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3
SWITCHING PRODUCTS
VCC D1 D1 GND D0 D0 GND OA0 OA1 GND OA2 OA3 GND LOAD CONFIGURE GND NC GND IA0 IA1 GND IA2 IA3 GND O0 O0 GND O1 O1 GND NC NC VEE
TQ8016
Table 2. Absolute Maximum Ratings4
Symbol
TSTOR TJ TC VCC VEE VTT VIN IIN VIN IIN VOUT IOUT PD
Parameter
Storage Temperature Junction Temperature Case Temperature Under Bias Supply Voltage Supply Voltage Load Termination Supply Voltage Voltage Applied to Any ECL Input; Continuous Current Into Any ECL Input; Continuous Voltage Applied to Any TTL/CMOS Input; Continuous Current Into Any TTL/CMOS Input; Continuous Voltage Applied to Any ECL Output Current From Any ECL Output; Continuous Power Dissipation per Output POUT = (GND - VOUT) x IOUT
Absolute Max. Rating
-65 C to +150 C -55 C to +150 C -55 C to +125 C 0 V to +7 V -7 V to 0 V VEE to 0 V VEE -0.5 V to +0.5 V -1.0 mA to +1.0 mA -0.5 V to VCC +0.5 V -1.0 mA to +1.0 mA VEE -0.5 V to +0.5 V -40 mA 50 mW
Notes
1 2 2 3
3
Notes: 1. TC is measured at case top. 2. All voltages specified with respect to GND, defined as 0V. 3. Subject to IOUT and power dissipation limitations. 4. Absolute maximum ratings, as detailed in this table, are the ratings beyond which the device's performance may be impaired and/or permanent damage to the device may occur. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed, singularly or in combination, the operating range specified in the Recommended Operating Conditions table, below. .
Table 3. Recommended Operating Conditions3
Symbol
TC GND VCC VEE VTT RLOAD
Parameter
Case Operating Temperature Ground Reference Voltage Supply Voltage Supply Voltage Load Termination Supply Voltage Output Termination Load Resistance
Min.
0 4.5 -5.5
Typ.
25 0
Max.
85 5.5 -4.5
Units
C V V V V
Notes
1
-2.0 50
2 2
Notes: 1. TC measured at case top. Use of adequate heatsink is required. 2. The VTT and RLOAD combination is subject to maximum output current and power restrictions. 3. Functionality and/or adherence to electrical specifications is not implied whenthe device is subjected to conditions that exceed, singularly or in combination, the operating ranges specified.
3
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TQ8016
Table 4. DC Characteristics1 TC = 0 C to 85 C, VCC = 4.5 V to 5.5 V, VEE = -5.5 V to -4.5 V, GND = 0 V, unless otherwise indicated.
Symbol
VIH VIL IIH IIL VICM VIDIF VIH VIL IIH IIL VOCM VODIF VOH VOL IOH IOL ICC IEE
Parameter
ECL Input Voltage High ECL Input Voltage Low ECL Input Current High ECL Input Current Low ECL Input Common Mode Voltage ECL Input Differential Voltage (P-P) CMOS Input Voltage High CMOS Input Voltage Low CMOS Input Current High CMOS Input Current Low ECL Output Common Mode ECL Output Differential Voltage ECL Output Voltage High ECL Output Voltage Low ECL Output Current High ECL Output Current Low Power Supply Current Power Supply Current
Min
-1100 VTT -30 -1500 400 3.5 0 -100 -1500 600 -1000 VTT 20 0
Typ
Max
-500 -1500 +30 -1100 1200 VCC 1.5 +100 -1100 -600 -1600
Units
mV mV uA uA mV mV V uA uA mV mV mV mV mA mA mA mA V
Test Cond.
Notes
VIH = 0.7 V VIL = -2.0 V
VIH = VCC VIL = 0 V
23 5 15 730
27 8 20 950
2 2
Notes: 1. Test conditions unless otherwise indicated: VTT = -2.0 V, RLOAD = 50 to VTT. 2. Positive current is defined as flowing into the device and negative current as flowing out of the device. ICC typically flows into the device and IEE flows out of the device.
Table 5. AC Characteristics1 - Within recommended operating conditions, unless otherwise indicated.
Symbol
Jitter T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 TR,F Channel Propagation Delay Ch-to-Ch Propagation Delay Skew CONFIG to Data Out (Oi) Delay LOAD Pulse Width CONFIG Pulse Width IAi to LOAD High Setup Time LOAD to IAi Low Hold Time OAi to LOAD High Setup Time LOAD to OAi Low Hold Time Load to CONFIG RESET Pulse Width Output Rise or Fall Time 7 7 0 3 0 3 0 10 250 400 1200 400
Parameter
Maximum Data Rate/Port
Min
Typ
Max
1.3 150 2000 500 5
Units
Gb/s ps pk-pk ps ps ns ns ns ns ns ns ns ns ns ps
Notes
1,2 1
3
Notes: 1. Test conditions: VTT = -2.0 V, RLOAD = 50 to VTT; ECL inputs: VIH = -1.1 V; VIL = -1.5 V; CMOS inputs: VIH = 3.5 V, VIL = 1.5 V; ECL outputs: VOH > -1.0 V, VOL < -1.6 V; ECL inputs rise and fall times < 1 ns; CMOS inputs rise and fall times < 20 ns. A bit error rate of 1E - 13 BER or better for 223 - 1 PRBS pattern, jitter and rise/fall times are guaranteed through characterization. 2. 1.2 Gb/s Non-Return-Zero (NRZ) data equivalent to 600 MHz clock signal. 3. Rise and fall times are measured at the 20% and 80% points of the transition from VOL max to VOL min.
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5
SWITCHING PRODUCTS
TQ8016
Figure 3. Timing Diagram -- Switch Configuration
Output Address Input Address
LOAD T4 T10 CONFIGURE T6 T8 Data In T1 Data Out OA OB OC OD OE Invalid Data Out DA DB DC T9 T7 DD DE DF DG T5
T3 OF OG
Figure 4. Timing Diagram -- Reset
RESET T11 CONFIGURE Output Data Broadcast Pass-through
Notes: 1. LOAD input must remain LOW to insure correct programming of the switch 2. "Broadcast" is defined as data input 0 to all data outputs (0..15). 3. "Pass-through" is defined as data input 0 to data output 0, data input 1 to data output 1, etc.
3
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TQ8016
Figure 5. AC Performance Measurements (Percent Recoverable "Eye" vs. Frequency 16 x 16)
100 90 80 70
Percent (%)
60 50 40 30 20 10 0 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200
Frequency (Mb/s)
Time Domain Voltage (Inner Eye)
Typical Error-Free Area
The graph in Figure 5 shows the typical error-free area of a 223 - 1 Pseudo-Random Bit Stream (PRBS) "eye" pattern. Data is provided for both time and voltage domains of the differential DIN0 to DOUT0 data path for various data rates. An interference pattern was applied to all other inputs in parallel to induce worst-case cross talk. For the time domain, Peak-to-Peak Jitter was measured at the eye crossing. An error-free percentage value was computed using the following formula: (Data_Period - PPJitter) x 100 / Data_Period Voltage values are referenced to an initial inner eye measurement at 400 MBs. Subsequent percentage values were computed using the following formula:
VINNER x 100 / VINNER @ 400 MBs
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7
SWITCHING PRODUCTS
TQ8016
Table 6. Typical Differential Waveform Characteristics (OUT - OUT)
Frequency Fall Time (20% - 80%) Rise Time (20% - 80%) Jitter (peak-to-peak) Time/division Volts/division 1200 Mb/s 195 ps 1200 Mb/s 40 ps 125 ps 250 mV
Figure 5. 1200 Mb/s Data "Eye" Pattern
Time/Div: 150 ps
3
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TQ8016
Figure 6. Mechanical Dimensions Top View
132
1.170 +.006 .950 +.006 .800
Bottom View
PIN 1 INDEX
1
A
A
CERAMIC OR METAL LID
.025
.010 +.0015 BSC
CHIP CAPACITOR, 4 PLACES
Section A-A
DEVICE .125
SEATING PLANE .064
Ordering Information
TQ8016-M
Additional Information
1.3 Gb/s 16x16 ECL Crosspoint Switch
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
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The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997
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9
SWITCHING PRODUCTS

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