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VS6552
VGA Color CMOS Image Sensor Module
FEATURES Small physical size

Ultra low power standby mode SmOP (Small Optical Package) technology featuring integrated lens Class leading low light performance VGA resolution sensor Compatible with STV0974 companion mobile processor High frame rate to minimize image distortion Low EMI link (VisionLink) to STV0974 On-chip 10-bit ADC Automatic dark calibration I2C communications On-chip PLL

VS6552 offers an ultra low power standby mode that consumes less than 15 W. The SmOP lens has been designed to combine class leading low light performance with good depth of field to ensure excellent overall optical performance. The lens is a 2 element moulded plastic design. The output data and qualification clock are transmitted over low noise, low voltage and fully differential links. VS6552 configuration registers are controlled via a private I2C interface to STV0974. APPLICATIONS Mobile phone embedded camera system PDA embedded camera or accessory camera Wireless security camera

Table 1. Technical Specifications
Pixel resolution Pixel size Exposure control Analog gain Dynamic range Signal to noise at 50cd.m2 Supply voltage Power consumption 644 x 484 (VGA) 5.6 m x 5.6 m +81 dB +24 dB (max) 60 dB (Typical) 37 dB (Typical) 2.8 V (analog supply) 1.8 V (digital supply) <75 mW (@30 frame/s) <15 W (standby mode) 10.7mm x 8.7mm x 6mm:SmOP1.5 9.5mm x 8.5mm x 6.1mm :SmOP2 45o HFOV, f# 2.8 14 pad SmOP Socket or flexible circuit
DESCRIPTION The VS6552 is a VGA resolution SmOP sensor module. SmOP technology combines the image sensor and fixed focus lens system in a single module. This approach provides a number of advantages: - SmOP technology is suitable for high volume manufacturing - SmOP can be plugged into a PCB mounted flow soldered socket - SmOP can be mounted close to noisy RF source as differential signalling used to transmit data has good immunity from radio interference. The sensor outputs raw Bayer colorized data to the STV0974 companion mobile processor. STV0974 then performs all color processing and exposure control functions before outputting the data in an appropriate interface format like YCbCr, RGB or JPEG.
Package size
Lens Package type System attach
October 2004
Rev. 2 1/26
VS6552
Table 2. Order Codes
Part Number VS6552V015/T2 VS6552V02C/T2 VS6552V02D/T2 Operating Temperature [ -25; +55 ] C [ -25; +55 ] C [ -25; +55 ] C Package SmOP1.5 SmOP2M SmOP2ME
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VS6552
TABLE OF CONTENT
Overview ........................................................................................................................................... 4 Sensor Overview 4 Signal Description ........................................................................................................................... 5 Functional Description .................................................................................................................... 6 Analog Video Block 6 Digital Video Block 6 Device Operating Modes 7 Power Management 7 Clock and Frame Rate Timing 8 Control and Video Interface Formats 9 Electrical Characteristics ................................................................................................................ 9 DC Electrical Characteristics 10 AC Electrical Characteristics 10 ESD Handling Characteristics 13 Optical specification...................................................................................................................... 13 Defect Categorization .................................................................................................................... 13 Pixel Defects 13 Package Mechanical Data ............................................................................................................. 13 SmOP1.5 Module Outline 13 SmOP2 M Module Outline 13 SmOP2 ME Module Outline 13 Application Information................................................................................................................. 23 Socket 23 EMC and Shielding 23 Revision History............................................................................................................................. 25
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VS6552
1 OVERVIEW
1.1 Sensor Overview The VS6552 VGA image sensor produces raw VGA digital video data at up to 30 frames per second. The image data is digitized using an internal 10-bit column ADC. The resulting 10-bit output data includes embedded codes for synchronization. The data is formatted and transmitted over a fully differential link. The data is accompanied by a qualifying clock that is transmitted over an identical fully differential link. The sensor is fully configurable using an I2C interface. The sensor is optimized for high volume mobile applications 1.1.1 Typical Application - Mobile Application The VS6552 is an image sensor, it should be used in conjunction with the STMicroelectronics STV0974 companion processor. The coprocessor and the sensor together form a complete imaging system. The sensors main function is to convert the viewed scene into a data stream. The companion processor function is to manage the sensor so that it can produce the best possible data and to process the data stream into a form which is easily handled by up stream mobile baseband or MMP chipsets. The sensor supplies high speed clock signal to the processor and provides the embedded control sequences which allow the co processor to synchronize with the frame and line level timings. The processor then performs the color processing on the raw image data from the sensor before supplying the final image data to the host.
Figure 1. Camera System Using STV0974
STV0974
VS6552 MSCL MSDA Pixel Array Digital Logic PCLKP PCLKN PDATAP PDATAN
Microprocessor Interface Logic
SCL SDA DIO[0:13]
VP
VC
ADC
CLK PDN
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VS6552
2 SIGNAL DESCRIPTION
Table 3. Signal Description
Pad Number Power supplies 1 2 3 8 11 System 4 5 Control 6 7 Data 9 10 12 13 Not connected 14 NC Not connected Not connected PCLKN PCLKP PDATAN PDATAP vLVDS output vLVDS output vLVDS output vLVDS output Output qualifying clock Output qualifying clock Serial output data Serial output data MSCL MSDA I I/O Serial communication clock Serial communication data PDN CLK I I Power down controlb System clock input CEXT AGND AVDD GND VDD PWR PWR PWR PWR PWR Connection to capacitora Analog ground Analog power Digital ground Digital power Pad Name I/O Type Description
a.Internally generated voltage that needs to be externally decoupled with a 100 nF, 5 V capacitor b.Signal is active low Note: The physical position of the signals on the package can be found by refering to the pinout information in Chapter 7: Package Mechanical Data.
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VS6552
3 FUNCTIONAL DESCRIPTION
The first sections of this chapter detail the main blocks in the device: Analog video block
3.1 Analog Video Block 3.1.1 Features

ADC: 10-bit A/D converter - SRAM readout Dynamic range 60 dB (typical) SNR 37 dB @ 50 cd.m2 (typical)
Digital video block
The later sections of this chapter describe other functional aspects of the device. Device level operating modes, including suspend, are detailed Figure 2. Analog Video Block SRAM readout X-Address Column ADC Power management
raw sensor data Timing signals
Digital logic
VGA pixel array
Y address
Timing signals
3.1.2 Analogue Block Diagram The analog video block from Figure 4, consists of a VGA resolution pixel array, power management circuitry. The digital block provides all timing signals to drive the analog block. Pixel voltage values are read out and digitized using the address decoders and column ADC 3.2 Digital Video Block 3.2.1 Features

Fixed pattern noise (FPN) data gathering Line and frame statistics gathering On-chip Power-On-Reset cell Single video output format: VGA 640 x 480 H - Scaler function to aid software only viewfinder implementations
3.2.2 Dark Calibration Algorithm VS6552 runs a dark calibration algorithm on the raw image data to control the video offsets caused by dark current. This ensures that a high quality image is output over a range of operating conditions. First frame dark level is correctly calibrated, for subsequent frames the adjustment of the dark level is damped by a leaky integrator function to avoid possible frame to frame flicker.
Frame rate: 30 frame/s max. (VGA) can be reduced down to less than 3 frame/s (VGA) Automatic dark calibration to ensure consistent video level over varying scenes
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VS6552
3.2.3 Image Statistics VS6552 generates image statistics which can be used by STV0974 as an input to an auto exposure controller (AEC), automatic gain controller (AGC) and automatic white balance (AWB). . 3.3 Device Operating Modes 3.3.1 Standby This is the lowest power consumption mode. I2C communications to STV0974 are not supported in this mode. The clock input pad, PLL and the video blocks are powered down. 3.3.2 Sleep Mode Sleep mode preserves the contents of the I2C register map. I2C communications to STV0974 are supported in this mode. The sleep mode is selected via a serial interface command sent by STV0974. The data pads go high at the end of the current frame. At this point the video block and Table 4. VS6552 Power-up Sequence
Design block powered down Mode I2C Standby (PDN low) Sleep Clock active Idle Video Digital PLL & CLK pinsa b Yes Yes No No No Output pins Analog Video data inhibit
PLL power down. The internal video timing is reset to the start of a video frame in preparation for the enabling of active video. The values of the serial interface registers like exposure and gain are preserved. The system clock must remain active to allow communication with the sensor. 3.3.3 Clock Active Mode This mode is similar to `sleep mode' except that the PLL is now powered up to permit a PCLKP/ PCLKN signal to be delivered to STV0974. The PDATAP/PDATAN pads remain inactive. The video block is powered down. 3.3.4 Idle Mode VCAP is generated. The analog video block is now powered up but the array is held in reset and the output PDATAP/PDATAN pads remain high. 3.3.5 Video The VS6552 streams live video to the STV0974.
Yes No No No No
Yes Yes No No No
Yes Yes Yes No No
Yes Yes Yes No No
Yes Yes Yes Yes No
a.PLL (Phase Locked Loop) generates fast system clock for STV0974 b.PLL, PCLKP and PCLKN pins
3.4 Power Management VS6552 requires a dual power supply. The analog circuits are powered by a nominal 2.8 V supply while the digital logic and digital I/O are powered by a nominal 1.8 V supply.
3.4.1 Power-up, Power-down Procedures The power up and power down procedures are detailed in the following Figure 3.
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VS6552
Figure 3. VS6552 Power-up Sequence
Standby VDD (1.8V) AVDD (2.8V) PDN CLK PCLKP/N PDATAP/N Sleep Clock active Idle Streaming
MSDA MSCL
Mode Change: Sleep -> Clock active Mode Change: Clock active -> Idle and enable data qualification clock and general configuration
Mode Command: Idle -> Streaming also enable data output
3.4.2 Active Signals with Unpowered VS6552 All signals going into the VS6552 must be either at a low state or high impedance when power is removed from the device. The exceptions to this rule are the I2C lines which may be at a low or high state and the clock which can be active. 3.5 Clock and Frame Rate Timing
defined in Table 5. The input clock pad accepts up to 26 MHz signals. Table 5. System Input Clock Frequency Range
System clock frequencya Min. (MHz) 6.5 Max. (MHz) 26
3.5.1 Video Frame Rate Control The output frame rate of VS6552 can be reduced by extending the frame length. The extension is achieved by adding 'blank' video lines to act as timing padding. This is advantageous as it does not reduce the pixel readout rate and therefore does not introduce unwanted motion distribution effects to the image. The frame rate can be reduced from the default 30 frame/s at VGA resolution to less than 3 frame/s at VGA resolution. 3.5.2 PLL and Clock Input A PLL IP block is embedded. This block generates all necessary internal clocks from an input range
a.The standard supported input frequencies (in MHz) are as follows: 6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2, 19.44, 26.
3.5.3 Clock Input Type VS6552 can receive the following clock types: Single ended CMOS

Single ended Sine wave Clock can be AC or DC coupled
The clock is fail-safe.
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VS6552
3.6 Control and Video Interface Formats 3.6.1 Overview Data is transferred from VS6552 to STV0974 via a high speed serial link (VisionLink). The serial data link comprises of two pairs of wires. The serial control data is transferred between the VS6552 to STV0974 via a private I2C bus. 3.6.2 VisionLink Physical Layer Data signals (PDATAP and PDATAN) and clock signals (PCLKP and PCLKN) are transferred from VS6552 to STV0974 via 2 pairs of balanced 100 impedance transmission lines. The transmission line pairs and custom transmitters/receivers realize a very low voltage differential (vLVDS) signalling scheme that can transfer information in a potentially noisy environment. As implemented in VS6552, VisionLink supports the transmission of raw Bayer data at VGA resolution up to 30 frame/s. 3.6.3 Serial I2C Control Bus The internal registers in VS6552 can be configured by STV0974 via a private I2C bus. STV0974 is the bus master and VS6552 is the single slave. VS6552 sends and receives commands over this bus at up to 400 kHz.
4 ELECTRICAL CHARACTERISTICS
Table 6. Absolute Maximum Ratings
Symbol VDIG VANA MSCL, MSDA PDN, CLK TSTO Parameter Digital power supply Analog power supply CCI Signals Power Down Control, System Clock Input Storage temperature Values -0.5 to 3.0 -0.5 to 3.6 -0.3 to VDIG + 0.3 -0.3 to VDIG + 0.3 -40 to + 85 Unit V V V V
oC
Note: Caution: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 7. Operating Conditions
Symbol Voltage VDD AVDD Temperature TAF TAN TAO
Note: 1. 2. 3. 4.
ParTyp.ameter
Min.
Typ.
Max.
Unit
Digital power supply voltage Analog power supply voltage
1.7 2.5
-
1.9 3.3
V V
Temperature (functional operating) Temperature (normal operating) Temperature (optimal operating)
-30 -25 +5
-
+70 +55 +30
C C C
Storage temperature: Camera has no permanent degradation Functional operating temperature: Camera is electrically functional Normal operating temperature: Camera produces `acceptable' images Optimum performance temperature: Camera produces optimal optical performance
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VS6552
4.1 DC Electrical Characteristics
Note: Typical values quoted for nominal voltage and temperature. Maximum values quoted for worse case operating conditions unless otherwise specified.
Table 8. Power Supply VDIG, VANA
Typ. Parameter Digital Standby Video, 30fps 1 15 5 20 Analogue NMa 9 <2 15 A mA Max. Typ. Max. Unit
a.Not Measurable - current is below the minimum calibrated measurement capabilities of the test system (1A)
Table 9. System Clock
Symbol Leakage current
a.With DC coupled square wave clock b.With DC 1V9 signal level applied
Parameter
Min.
Typ. 8a
Max. 29b
Unit A
Table 10. I2C Interface - MSDA, MSCL
Symbol VIL VIH VOL IIL IIH f Parameter description Low level input voltage High level input voltage Low level output voltageb,c Low level input current High level input current Operating frequency range 0 0.7 VDIGa Min. Typ. 0.2 VDIG -10 10 400d Max. 0.3 VDIG Unit V V V A A kHz
a.For positive electrostatic discharges above 500 V, a shift of VIH may happen. However, the device remains fully functional even for a stress up to 2000 V included, and VIH<0.9 VDIG. Refer to the STV0974 datasheet for recommendations on MSCL/MSDA usage. b.VOH not valid for CCI c.1 mA drive strength d.For external clock frequencies <19.2MHz Max limit is 200KHz
4.2 AC Electrical Characteristics Table 11. System Clock
Symbol VCL VCH VCAC Parameter description DC coupled square wave (low level) DC coupled square wave (high level) AC coupled sine wave 0.7 VDIG 0.5 1.0 1.2 Min. Typ. Max. 0.3 VDIG Unit V V V
a
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VS6552
Symbol fCLK Parameter description Clock frequency input Min. 6.5 - 1%a Typ. Max. 26 + 1%b Unit MHz
a
a.Nominal frequencies are 6.5 to 26MHz with a 1% center frequency tolerance
Table 12. Timing Characteristics
Symbol tMSCL tLOW tHIGH tSP tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO Ci/o Cin Parameter description MSCL clock frequency Clock pulse width low Clock pulse width high Pulse width of spikes which are suppressed by the input filter Bus free time between transmissions Start hold time Start set-up time Data in hold time Data in set-up time MSCL/MSDA rise time MSCL/MSDA fall time Stop set-up time Input / Output capacitance (MSDA) Input capacitance (MSCL) Min. 0 1.3 0.6 0 1.3 0.6 0.6 0 100 20+0.1Cba 20+0.1 Cb 0.6 8 6 300 300 0.9 50 Max. 400 Unit kHz s s ns s s s s ns ns ns s pF pF
a.Cb = total capacitance on the lines
Figure 4. CCI AC characteristics
stop start
MSDA ...
start
stop
tBUF
tLOW tR
tF
tHD.STA
MSCL
...
tHD.STA
tHD.DAT
tHIGH tSU.DAT
tSU.STA
tSU.STO
Note: The VS6552 maximum I2C frequency of 400 kHz is only valid for external clock frequencies at or above 19.2 MHz. Due to a design issue, for external clock frequencies below 19.2MHz, the maximum guaranteed I2C frequency is limited to 200 kHz.
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VS6552
Table 13. vLVDS Interface AC Electrical Characteristics
Symbol Vod Vcm RO IDR Parameter description Differential voltage swinga,b Common mode voltage (self biasing) Output Impedance Drive current range (internally set by bias circuit) Min. 100 0.8 40 0.5 1.5 Typ. 150 0.9 Max. 200 1.0 140 2 Unit mV V W mA
a.Supplies of VDIG = 1.8 V and VANA = 2.8 V, Temperature = 25 C b.Measured over a 100 Ohm load
Table 14. vLVDS TIming Characteristics
Symbol fPCLKP/ PCLKN tPCLKP/
PCLKN
Parameter PCLKP/PCLKN clock frequency PCLKP/PCLKN clock period PCLKP/PCLKN duty cycle
Min. 8.3 26 1.66 1.66 0.3 0.3 3 1
Typ. -
Max. 120 100 74
Unit MHz ns % ns ns
tLOW tHIGH tRISE tFALL tHD;DAT tSU;DAT
Low period of PCLKP/PCLKN High period of PCLKP/PCLKN Rise time of PDATAP/PDATAN, PCLKP/ PCLKN Fall time of PDATAP/PDATAN, PCLKP/ PCLKN Data hold time Data set-up time
0.5 0.5 -
ns ns ns ns
Figure 5. VisionLink AC timing
tPCLKP/PCLKN
PCLKP/ PCLKN tLOW tRISE tHIGH tFALL
VDIG/2
PDATAP/ PDATAN
VDIG / 2
tSU;DAT
tHD;DAT
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VS6552
4.3 ESD Handling Characteristics Table 15. ESD Handling Limits
Test ESD Human Body Model ESD Machine Model Latch Up Method JESD22 A114A JESD22 A115A JESD78 Criteria 2kV 200V 1.5 * Vddmax, 150mA
6 DEFECT CATEGORIZATION
6.1 Pixel Defects A packaged CMOS image sensor will display visual imperfections caused either by electrical faults or optical blemishes which can be introduced in the product at various stages of the manufacturing process. These impurities can result in pixel defects, that is a pixel whose output is not consistent with the level of incident light falling on the image sensor. The ability to identify and correct these defects is central to both the design requirements and quality certification, via test of STMicroelectronics sensor products. The STMicroelectronics STV0974 co-processor implements defect correction algorithms which screens the presence of these defects in the final images. The defect correction algorithms ensure that the VS6552 sensor in conjunction with the STV0974 co-processor will produce a high quality final image.
5 OPTICAL SPECIFICATION
The small amount of lens relative illumination effects (field darkening) is corrected by the STV0974. Table 16. Optical Specifications
Parameter Effective Focal Length Aperture Horizontal Field of View TV Distortion (pin,cushion & barrel) MTF (Figure 6.) @ 60 cm @ 45 cycle/mm Value 4 mm 0.15 mm F2.8 aperture 45o 2o -3% to 3% - - - On axis: 45 % Horizontal field: 30% Diagonal field: 30%
7 PACKAGE MECHANICAL DATA
7.1 SmOP1.5 Module Outline - Figure 7 - Figure 8 - Figure 9 7.2 SmOP2 M Module Outline - Figure 10 - Figure 11 - Figure 12 7.3 SmOP2 ME Module Outline - Figure 13
Figure 6. MTF Points on the Image Field
on axis
horizontal field
- Figure 14 - Figure 15
diagonal field
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0.40
0 .05
0.80
0.75
8.26
8.66 0.06
3.26
C (20 : 1)
3 draft
0.87 5.70 0.035
B
Note 9 3 1.50 TYP
Notes:
0.15 0.03 1.90 0.15
A
1.40
3.90 0.22
C
CL Lensholder 0.00 0.15 4.05 0.08 Note 10 CL Ceramic 0.00 0.15 5.42 0.08
Sig. Date
CL Lensholder 0.06 B 4.58 0.08
Scale
1. Mass of module 0.50 grammes 2. Volume of Module 278 mm^3 3. 2 max draft angle on all moulded components unless otherwise stated. 4. Surface finish on external moulded surfaces is RA 16 (Charmille 24). 5. Surface finish on base of ceramic is TBD. 6. All gates on moulded parts will be sub flush. 7. All mouldings to be free from visible flash or mismatch. 8. Uniformly distributed load of 20N may be applied to datum surfaces A & B. 9. These numbers denote tool No. and cavity. 10. Edge of ceramic and glue bead will not protrude past edge of lensholder. CL Ceramic 11. Dimensions enclosed thus 0.25 are inspection dimensions. 12. Minimum breaking torque between lensholder and barrel is Note 10 40 Nmm. 13. These 3 depressions contain gates or are used for cavity & 4.05 0.08 tool identification and ejector pin locations. Tolerances, unless otherwise stated Interpret drawing per BS308, 3RD Angle Projection Material
All dimensions in mm Finish
All dimensions in mm
Do Not Scale
STMicroelectronics
Part No.
Linear 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.25 degrees Diameter +0.10/-0.00 Position 0.10 Surface Finish 1.6 microns
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
Drawn Checked Appd. Mech. Appd. Elect. Appd. Prod. Appd. Q.A.
7526498
Consumer & Micro Group - Imaging Division Title SmOP 1.5, Ver 2.22 Low Sheet
3.05 0.19
Profile Camera Outline
5.80 0.22
1 of 3
4.33
14/26
RevNo Revision note ECN No. Date Checked
VS6552
B
See Sheet 2 for details
19/01/04
10.56 0.06
5 8.2
0.60 0.03 Note 13 Note 9
6 8.5
5 7.2
R0 .10
Figure 7. SmOP1.5 Module Outline
Gate Position
B
AX 3.55 M
15
RevNo ECN No. Date Checked
Revision note
A 39 max. (Pyramid) B
B
B2
First Release as 7526498. Previous version of camera was 7487715 Barrel flange increased. Diameter on lens holder increased. Laser weld recesses moved and length was 1.60, 0.30 feature on pin 1 12/05/03 was 0.50 Tolerance added. Pad 1 dimension changed from 0.5 to 0.3mm 19/01/04 Material changed from Noryl HB1525 to Makrolon 2405. 17/02/04 Exclusion Cone corrected was 60 , Now 61
Makrolon: 2405 Colour Black COP: Zeonex E48R COP: Zeonex E48R Makrolon: 2405 Colour Black
Figure 8. SmOP1.5 Module Outline
Note 10
E Glass Coated with IR Filter Material Silicon Ceramic: Alumina Dark Grey 1.4 min.
E (16 : 1) E
D-D (8 : 1)
Pyramid
B
x. ma ne) o 6 3.3 B (C m atu D At
Top of image B2
Cone
61 max. (cone)
Field of View Data. Edges of circular holes in customer's equipment must not intrude into the Cone. Edges of rectangular holes must not protrude into the Pyramid.
50 max. (Pyramid)
D
D
Tolerances, unless otherwise stated
All dimensions in mm
Interpret drawing per BS308, 3RD Angle Projection
Material Sig. Date
2.69 max. at Datum B (Pyramid) Sub flush gate posn See Note 6 2.01 max. at Datum B (Pyramid)
All dimensions in mm Do Not Scale
Scale
Finish
STMicroelectronics
Part No.
Linear 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.25 degrees Diameter +0.10/-0.00 Position 0.10 Surface Finish 1.6 microns
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
Consumer & Micro Group - Imaging Division Title SmOP 1.5, Ver 2.22 Low Sheet
Drawn Checked Appd. Mech. Appd. Elect. Appd. Prod. Appd. Q.A.
7526498
Profile Camera Outline
2 of 3
VS6552
15/26
0
2.65 0.05
4.05 0.05
1.20 0.03 typ
Figure 9. SmOP1.5 Module Outline
0.48 0.22
8.40 0.05 7.10 0.05
7.00 0.05 5.70 0.05
5.60 0.05
4.20 0.05 2.90 0.05
2.80 0.05
5.35 0.05
Tolerances, unless otherwise stated
Material All dimensions in mm Finish
Interpret drawing per BS308, 3RD Angle Projection
0.48 0.22
0.30 0.03
16/26
RevNo Revision note ECN No. Date Checked
VS6552
B
See Sht 2
19/01/04
Underside of module showing connector and test pad layout.
Part Marking in Hatched areas. Refer to Spec TBD for details. Pad material is 0.30 microns gold on 2 microns nickel
1.40 0.05
1.50 0.05 Pad 1
0 B
0
2.35 0.03 typ 2.65 0.03 1.00 0.03
Sig.
Date
All dimensions in mm
Do Not Scale
Scale
STMicroelectronics
Part No.
Linear 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.25 degrees Diameter +0.10/-0.00 Position 0.10 Surface Finish 1.6 microns
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
Consumer & Micro Group - Imaging Division Title SmOP 1.5, Ver 2.22 Low Sheet
Drawn Checked Appd. Mech. Appd. Elect. Appd. Prod. Appd. Q.A.
7526498
Profile Camera Outline
3 of 3
RevNo Revision note Date Initial
B2 Gate Location These cavities may contain glue. Note 9
5.46
See Sheet 3 Note 10
R0.10 R0.10
10
0.80 0.40
7.20
8.50 0.06
R5
0.50
4.25
Figure 10. Module Outline (SmOP 2M)
1.68 0.10
B
4.75 0.52 8.22 at Datum B If no radii 1.50 2.40 C (20 : 1) 0.60 9.50 0.06 8.95
Note 14
A (20 : 1)
Note 13
B (20 : 1) 0.50
+0.1 R0.10 0
2 TYP
2.70 0.10 0.40
Notes: 1. Mass of module: <0.5 grammes. 2. Volume of module: 370.2 mm^3. 3. 2 deg max draft angle on all moulded components unless B otherwise stated. 4. Surface finish on all external moulded surfaces is Charmille 30 MAX. 5. Surfaces shown in silver to be conductively plated. See sheet 2 for plating information. 6. All gates to be sub flush. A 7. All mouldings to be free from flash or mismatch. 8. Uniformly distributed load of 20N to be applied to datum surfaces A & B. 9. These numbers denote tool number and cavity. Text will be subflush with surface. 10.These depressions may be used to indicate lens type, tool number and cavity. 11.Dimensions enclosed thus are inspection dimensions. 12.Breaking torque between lens barrel and holder > 20 Nmm. 13.Corners of the substrate will not protrude past the rectangular footprint of the lens holder. 14.Glue bead will not protrude past edge of substrate.
C
Material
A
Finish
0.50 At Datum A
Drawn
Tolerances, unless otherwise stated
All dimensions in mm
Interpret drawing per BS308, 3RD Angle Projection
DBS
Date
All dimensions in mm
Do Not Scale
All Dimensions 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.5 degrees
18/06/03
Part No.
STMicroelectronics
Position 0.10 Surface Finish 1.6 microns
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
7540020
Consumer & Micro Group - Imaging Division Title SMOP2-M Sheet
OUTLINE DRAWING
6.10 0.10
Scale
1 of 3
VS6552
17/26
2.40
+0.3 0.94 - 0.1
Exclusion Zones. Edges of circular holes in customer's equipment must not intrude into the cone. Edges of rectangular holes must not prodrude into the pyramid. Dimensions shown are maximums.
Note: If an upgrate path from 5.6 micron VGA to 4 micron SVGA is required then the 4 micron SVGA data should be used.
Plating Notes 1. 4 point probe to be used to check resistance of the metalisation. 2. Probe to must not contact the lens mount in the scalloped areas. 3. Probe to contact the cylindrical section of the lens mount between any 2 of the 3 equi-spaced points around the diameter. 4. Plating Options: a.1 micron Copper, 0.1micron MIN Stainless Steel B2 b.1 micron Copper, 0.1micron MIN Nickel Chrome c.1 micron Copper, 0.1micron MIN TBD 5. Resistance to be less than 1 ohm. 6. Contact force to be 2N.
Material All dimensions in mm
Module 5.6 micron VGA 4 micron SVGA
MAX Exclusion Zones Dimensions A B C D 61 50.36 39.06 4 64 53.12 41.1 4.15
E 3.2 3.32
Tolerances, unless otherwise stated
Interpret drawing per BS308, 3RD Angle Projection
Drawn Date Finish Part No.
DBS 18/06/03 7540020
All dimensions in mm
Do Not Scale
All Dimensions 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.5 degrees
STMicroelectronics
Consumer & Micro Group - Imaging Division Title Sheet
Position 0.10 Surface Finish 1.6 microns
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
SMOP2-M OUTLINE DRAWING
See Table Dim E At Datum B
18/26
See Plating Notes 2 and 3 Cone See Table Dim A These cavities may contain glue. Pyramid See Table Dim B B A 5 Cosmetics not guaranteed outside this area. Pyramid Probe points to contact inside dotted lines. Cone Pyramid See Table Dim C SECTION B-B SCALE 5 : 1 See Table Dim D At Datum B Noryl: N110 COP or PC COP or PC Noryl: N110 E Glass with IR filter Material
RevNoB2 Revision note
VS6552
0 12
See Sheet 3
Date Initial
A
"Class A" Surface (Top face of barrel) 120
Figure 11. SmOP2 Module Outline
Scallops may contain US weld marks. Weld will not protrude past cylindrical surface.
Silicon Substrate: Glass/epoxy pre-preg
These surfaces to be plated
B
B
SECTION A-A SCALE 6 : 1
See Table Dim F At Datum B
F 2.4 2.49
Scale
2 of 3
RevNo Revision note Date Initial
B 010404 DBS
See ADCS Revision A for previous history Step in chamfer added. Note 4 corrected. Notes revised to remove TBD. Torque spec changed to 20Nmm. Inspection dimension moved. Surface finish changed to Charmille 30 MAX. Top diameter re-defined. Sheet 2, Note 5, Contact resistance changed to 1 ohm. Sheet 2, Note 3 reworded. Sheet 3, Pad outline note added. 110604 DBS 160604 DBS
B1 B2
Underside of module showing connector and test pad layout. 1 0.03 TYP Pad 14
VDIG CCP CLKP CCP CLKN DGND CCP DATAP CCP DATAN DGND
Figure 12. SmOP2 Module Outline
Test Test Test
1.50 0.03 TYP
Test
0.20 TYP
0.10 TYP Area For Test Pads, Additional Tracking & Part Marking
VCAP
AGND
VANA
XSHUT DOWN
CCISCL
Pad 1 Pad Material is 0.3 microns minimum gold on 5 microns minimum nickel.
EXTCLK
CCISDA
Area for test pads, additional tracks and part marking. No conductive contact or force allowed in this area.
B2 Note: Minimum size shown for pad. Pad spacing will be maintained. Actual pad outlines may be extended. Refer to individual product substrate drawings.
Material
1.10 0.03 2.20 0.03 3.30 0.03 4.40 0.03 5.50 0.03 6.60 0.03
Tolerances, unless otherwise stated
All dimensions in mm
Interpret drawing per BS308, 3RD Angle Projection
2.75 3.85
6.10
Drawn Date
DBS 18/06/03
All dimensions in mm
Do Not Scale
Scale
All Dimensions 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.5 degrees
Finish
STMicroelectronics
Part No.
Position 0.10 Surface Finish 1.6 microns
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
7540020
Consumer & Micro Group - Imaging Division Sheet Title SMOP2-M
OUTLINE DRAWING
3 of 3
VS6552
19/26
8.50 0.06
R0.10 4.25
8 0.15
Figure 13. SmOP2 Module Outline
R0.10
0.80 0.40
0.50
1.68 0.10
0.50 B (20 : 1) C (20 : 1) 0.52 (7.30)
B 4.75
8.95 9.50 0.06 14 0.15 +0.10 R0.10 0
Note 14
A (20 : 1)
2 TYP
2.40
0.40
2.70 0.10
0.50 TYP
Notes: 8.22 at datum B B 1. Mass of module: <0.5 grammes. If no radii 2. Volume of module: 384.7 mm^3. 3. 2 deg max draft angle on all moulded components unless 1.50 otherwise stated. 4. Surface finish on all external moulded surfaces is Charmille 30 MAX. 5. Surfaces shown in silver to be conductively plated. A See sheet 2 for plating information. 6. All gates to be sub flush. 7. All mouldings to be free from flash or mismatch. 8. Uniformly distributed load of 20N to be applied to datum surfaces A & B. 9. These numbers denote tool number and cavity. Text will be subflush with surface. 10.These depressions may be used to indicate lens type, tool number and cavity. 11.Dimensions enclosed thus are inspection dimensions. 12.Breaking torque between lens barrel and holder > 20 Nmm. 13.All translational and rotational placement tolerances are included in this area. 14.Glue bead will not protrude past edge of Lens Holder.
C
A
0.50 at datum A
Tolerances, unless otherwise stated
Material All dimensions in mm
Interpret drawing per BS308, 3RD Angle Projection
Drawn Date Finish Part No.
DBS 30/06/03 7545055
All dimensions in mm
Do Not Scale
Scale
All Dimensions 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.5 degrees Position 0.10 Surface Finish 1.6 microns
STMicroelectronics
Consumer & Micro Group - Imaging Division Title Sheet SMOP2-ME
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
OUTLINE DRAWING
1 of 3
6.10 0.10
20/26
RevNo Revision note Date Initial
VS6552
B4 See Sheet 3 Note 10
6 5.4
7.20
0.30 Note 9 Note 13
Gate Location
R5
120
RevNo Date Initial
B4
Revision note
See Sheet 3 Cone See Table Dim A Pyramid See Table Dim B B Noryl N110 COP or PC COP or PC Noryl N110
See Plating Notes 2 and 3 These cavities may contain glue.
A
A
"Class A" Surface (Top face of barrel)
120
Figure 14. SmOP2 Module Outline
5 Cosmetics not guaranteed outside this area
E Glass with IR filter Material Silicon Substrate: Glass/epoxy pre-preg Pyramid Cone Pyramid See Table Dim C SECTION B-B SCALE 5 : 1 See Table Dim D At Datum B
Scallops may contain US weld marks. Weld will not protrude past cylindrical surface.
These areas to be plated. B B
+0.3 0.94 - 0.1
2.40
Probe point to contact inside dotted lines.
Exclusion Zones. Edges of circular holes in customer's equipment must not intrude into the cone. Edges of rectangular holes must not prodrude into the pyramid. Dimensions shown are maximums. Note: If an upgrate path from 5.6 micron VGA to 4 micron SVGA is required then the 4 micron SVGA data should be used.
SECTION A-A SCALE 5 : 1 Plating Notes 1. 4 point probe to be used to check resistance of the metalisation. 2. Probe to must not contact the lens mount in the scalloped areas. 3. Probe to contact the cylindrical section of the lens mount between any 2 of the 3 equi-spaced points around the diameter. 4. Plating Options: B4 a.1 micron Copper, 0.1micron MIN Stainless Steel b.1 micron Copper, 0.1micron MIN Nickel Chrome c.1 micron Copper, 0.1micron MIN TBD 5. Resistance to be less than 1 ohm. 6. Contact force to be 2N.
Material
Module 5.6 micron VGA 4 micron SVGA
MAX Exclusion Zones Dimensions A B C 61 50.36 39.06 64 53.12 41.1
D 4 4.15
E 3.2 3.32
Tolerances, unless otherwise stated
All dimensions in mm
Interpret drawing per BS308, 3RD Angle Projection
Drawn Date Finish
DBS 30/06/03
Part No.
All dimensions in mm
Do Not Scale
Scale
All Dimensions 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.5 degrees Position 0.10 Surface Finish 1.6 microns
STMicroelectronics
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
7545055
Consumer & Micro Group - Imaging Division Title SMOP2-ME Sheet
OUTLINE DRAWING
See Table Dim E At Datum B See Table Dim F At Datum B F 2.4 2.49 2 of 3
VS6552
21/26
1.10 0.03 2.20 0.03 3.30 0.03 4.40 0.03 5.50 0.03 6.60 0.03
0.20 TYP
VDIG
CCP CLKP
DGND
CCP CLKN
CCP DATAP
CCP DATAN
DGND
6.10
1.50 0.03 TYP
2.75
EXT CLK
VCAP
VANA
CCIS CL
CCIS DA
3.85
AGND
XSHUT DOWN
Area for Part Marking. Pad 1 (Test Duplicate) No Force allowed in this area Note: Minimum size shown for pad. Pad spacing will be maintained. Actual pad outlines may be extended. Refer to individual product substrate drawings. 1.10 2.20 3.30 4.40 5.50 6.60 B4
Material
1 0.03 TYP
22/26
RevNo Revision note Date Initial
VS6552
B B1 B2 040504 110604 160604 B3 B4 DBS DBS DBS DBS
Underside of module showing connector and test pad layout. Surface finish changed to charmille 30 MAX. Top diameter defined. Sheet 2, Note 5, Contact resistance changed to 1 ohm. Sheet 2, Note 3 reworded. Sheet 3, Pad outline note added.
Released into ADCS Notes 4 and 10 corrected. Top edge radius changed from +0.05 to +0.1mm. Notes updated to remove TBD. Torque now aet to 20Nmm. Inspection dimension moved.
230104 010404
DBS
1 0.03 TYP Area For Test Pads & Additional Tracking. 12.10 1.45
DGND CCP CLKN CCP CLKP VDIG
Figure 15. SmOP2 Module Outline
Pad 14 (Test Duplicate)
1.45
Area for Part Marking. Pad Material is 0.3 microns minimum gold on 5 microns minimum nickel.
CCIS DA CCIS CL EXT CLK XSHUT DOWN VANA AGND VCAP
Test Test
CCP DATAN CCP DATAP DGND
Test
Test
Pad 14 1.50 0.03 TYP
Pad 1 Any force applied to the topside of the substrate should be balanced by a counter force directly opposite on the underside of the substrate and vice versa.
Tolerances, unless otherwise stated
All dimensions in mm
Interpret drawing per BS308, 3RD Angle Projection
Drawn
DBS
Date Finish Part No.
All dimensions in mm
Do Not Scale
Scale
All Dimensions 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.07 Angular 0.5 degrees Position 0.10 Surface Finish 1.6 microns
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
30/06/03 7545055
STMicroelectronics
Consumer & Micro Group - Imaging Division Sheet Title SMOP2-ME
OUTLINE DRAWING
3 of 3
VS6552
8 APPLICATION INFORMATION
8.1 Socket ST has developed a low-profile socket for the SmOP 1.5 package, which is suitable for reflow soldering and manual / automatic insertion of the camera module. The socket has been designed to withstand mobile phone grade reliability tests (temperature, shocks, vibration, salt mist). Please contact ST for details on ST P/N XS0015. See Figure 16 for recommended PCB layout and mechanical footprint of the XS0015 socket. 8.2 EMC and Shielding The VS6552 is a low noise device and is highly tolerant of high levels of radio frequency (RF) radiation. However if this device is closely mounted to a sensitive receiver it is recommended that the VS6552 is shielded to prevent reducing the sensitivity or channel masking of the receiver. Recommended maximum field strength: 1kV/m. Maximum radiated power transferred from the VS6552 into a GSM monopole antenna mounted 15 mm away from the VS6552 has peaks of inter-
ference at around -90 dBm. This is dependent on system design and layout. To minimized the coupling between the GSM antenna and the sensor the following guide lines should be observed. Camera should be positioned as far away from the GSM antenna as possible. The distance between the low frequency (below 1GHz) resonant antenna elements and the camera should also be maximized. The VS6552 and its associated decoupling capacitors should NOT be connected together using the antenna reference ground. The ground connections in the sub circuit should be connected either: by a dedicated ground trace network, that is connected by a single point to the main ground of the system
by an internal ground plane, which is entirely covered and single point connected to a protective ground.
The PCLKP and PCLKN lines can be filtered to reduce the induced noise. The protective ground should be flooded around the sensor socket pads to reduce the radiation aperture in the protective ground plane.
23/26
7,3
RECOMMENDED SOLDER
10,5
1,1 1,4
Echelle: 5/1 Matiere: Tolerances Generales: Ra general: Verifie par:
Modif: Piece: Ensemble: Ref: Dessine par: FM
Mise a jour version
par:
1,5
10
24/26
11,7
FM le: 03/11/03
VS6552
Figure 16. SmOP1.5 Socket Mechanical Data
CLEARANCE FOR VACUUM P&P
SMOP 1.5
SOCKET FOR CAMERA MODULE
Le: 04/02/03
VS6552
9 REVISION HISTORY
Table 17. Revision History
Date May 2004 Revision 1 Description of Changes First Release of Product Preview Second Release - Document status changed to datasheet. to reflect the product maturity level. Changes applied in Electrical Characteristics and Package Information with the addition of two packages (SmOP2M and SmOP2ME).
21 October 2004
2
25/26
VS6552
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
26/26

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