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| YTD427 APPLICATION MANUAL IAFE ISDN DSU Analog Front End YTD427 APPLICATION MANUAL CATALOG No. : LSI-6TD427A2 1997.12 b IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. Yamaha assumes no liability for incidental, consequential or special damages or injury that may result from misapplication or improper use or operation of the Products. 4. Yamaha makes no warranty or representation that the Products are subject to intellectual property license from Yamaha or any third party, and Yamaha makes no warranty or representation of non-infringement with respect to the Products. Yamaha speci cally excludes any liability to the Customer or any third party arising from or related to the Products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. Examples of use described herein are merely to indicate the characteristics and performance of Yamaha products. Yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. Yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, tness for a particular use and title. Contents 1 INTRODUCTION 1.1 General Description : 1.2 Features : : : : : : : : ::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::: 3 3 3 2 BLOCK DIAGRAM 3 PIN DESCRIPTIONS 4 FUNCTIONS 5 ELECTRICAL CHARACTERISTICS 5 7 3.1 Pin Assignments : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 3.2 Pin Functions : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 11 13 5.1 5.2 5.3 5.4 Absolute Maximum Ratings : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Recommended Operating Conditions : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : DC Characteristics : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : AC Characteristics : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 13 14 15 17 6 PACKAGE OUTLINE 19 21 APPENDIX A EXMAPLE OF APPLICATIONS A.1 Example of Application Circuits ::::::::::::::::::::::::::::::::::: 21 1 2 CONTENTS Chapter 1 INTRODUCTION 1.1 General Description YTD427 is a communication LSI which provides the ISDN subscriber interface (two-wire metallic time compression multiplexing operation). It is capable of providing the electric characteristics conforming to TTC Standard JT-G961. A DSU (Digital Service Unit) can easily be constructed by combining with YTD426B. 1.2 Features 1. Automatic Gain Control (AGC) function 2. Filter function 3. Peak hold function 4. ADC (Analog Digital Converter) function 5. Low Power Consumption Operation mode 72mW(typ.) 6. CMOS technology 7. 64-pin QFP 8. Single +5 volt supply 3 4 CHAPTER 1. INTRODUCTION Chapter 2 BLOCK DIAGRAM YTD 427 internal block diagram is shown in Figure2.1. ADC Peak Holder Filter AGC U reference point interface (Receive data) YTD426B Digital I/F Figure 2.1: Internal Block Diagram 5 6 CHAPTER 2. BLOCK DIAGRAM Chapter 3 PIN DESCRIPTIONS 3.1 Pin Assignments The pin assignments of YTD427 are shown in Figure 3.1. D3 D4 D5 D6 D7 DV SS DV SS D8 D9 D10 D11 D12 D13 D14 D15 DV DD 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 D2 D1 D0 DV DD DV DD ADCK TEST4 TEST3 TEST2 TEST1 TEST0 RSTN FTHN NC4 DV SS AV SS 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DV DD STRBN RWN TEST6 A0 A1 TEST5 NC3 NC2 NC1 DV SS AV SS SXB SXA SGBP SGB Figure 3.1: YTD427-F (64-pin QFP) Pin Assignments [Top View] VRBS VRB VRT VRTS AV DD AV DD ATEI ATEO SGR AV SS AV SS RXU SGA AV DD AV DD RXS 7 8 3.2 Pin Functions CHAPTER 3. PIN DESCRIPTIONS Pin No. 1 2 3 4 Pin Name SGB I/O 0 0 0 0 SGBP SXA SXB Connect a 0.015F capacitor across the SGB and SGR pins. Connect a 0.015F capacitor across the SGBP and SGR pins. Connected to SXB. Connected to SXA. Function Remarks 5, 48, 58, 59 AVSS 6, 26, 27, 47 DVSS 7 8 9 10 11 12 13 14 15 NC1 NC2 NC3 TEST5 A1 A0 TEST6 RWN STRBN GND Analog ground GND Digital ground IN IN IN IN IN IN IN IN IN Unused Connected to DVSS Unused Connected to DVSS Unused Connected to DVSS Test input 5 Connected to DVSS Address bus bit 1 Connected to ADDRES1 of YTD426B Address bus bit 0 Connected to ADDRES0 of YTD426B Test input 6 Connected to DVSS Read/write signal \H" : Read \L" : Write Connected to RWN of YTD426B Strobe signal \H" : Inactive \L" : Active Connected to STRBN of YTD426B All pins must be joined together. All pins must be joined together. 16, 17, 36, 37 DVDD PWR Digital power supply All pins must be joined together. 3.2. PIN FUNCTIONS 9 I/O Pin No. Pin Name 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN IN IN Data bus bit 15 Connected to AFEDATA15 of YTD426B. Data bus bit 14 Connected to AFEDATA14 of YTD426B. Data bus bit 13 Connected to AFEDATA13 of YTD426B. Data bus bit 12 Connected to AFEDATA12 of YTD426B. Data bus bit 11 Connected to AFEDATA11 of YTD426B. Data bus bit 10 Connected to AFEDATA10 of YTD426B. Data bus bit 9 Connected to AFEDATA9 of YTD426B. Data bus bit 8 Connected to AFEDATA8 of YTD426B. Data bus bit 7 Connected to AFEDATA7 of YTD426B. Data bus bit 6 Connected to AFEDATA6 of YTD426B. Data bus bit 5 Connected to AFEDATA5 of YTD426B. Data bus bit 4 Connected to AFEDATA4 of YTD426B. Data bus bit 3 Connected to AFEDATA3 of YTD426B. Data bus bit 2 Connected to AFEDATA2 of YTD426B. Data bus bit 1 Connected to AFEDATA1 of YTD426B. Data bus bit 0 Connected to AFEDATA0 of YTD426B. Function Remarks 10 Pin No. Pin Name I/O CHAPTER 3. PIN DESCRIPTIONS 38 39 40 41 42 43 44 45 46 49 50 51 52 55 56 57 60 61 64 ADCK TEST4 TEST3N TEST2 TEST1 TEST0 RSTN FTHN NC4 VRBS VRB VRT VRTS ATEI ATEO SGR RXU SGA RXS IN ADC operation clock signalYTD426B. Connected to CLK640K of IN Test input 4 DV . Connected to SS I/O Test input 3 to "H". Usually xed IN Test input 2 DV . Connected to SS IN Test input 1 DV . Connected to SS IN Test input 0 DV . Connected to SS Reset input pin IN \L" : Reset Reset time is 2s(minimum) IN Test input to "H". Usually xed IN Unused to DV . Connected SS OUT ADC reference power supply output (low voltage) IN ADC reference power supply input (low voltage) IN ADC reference power supply input (high voltage) OUT ADC reference power supply output (high voltage) PWR Analog power supply Test signal input Connected to AVSS . input, I/O Test signal to AV output Connected SS . OUT Analog signal reference output IN Receive signal input Connect 0 SGR. a 0.0047F capacitor across SGA and Connect 0 SGR. a 0.0022F capacitor across RXS and IN Function Remarks 53, 54, 62, 63 AVDD All pins must be joined together. Chapter 4 FUNCTIONS Receive Interface Receive pin RXU has a high input impedance. An example of a reference circuit of the receive interface is shown in Figure 4.1. R=3.9k (1%) YTD427 RXU R=1.2k (1%) SGR Figure 4.1: Receive Interface Connection AGC The AGC section adjusts the gain in 0.22 dB step in the range from 0.0 to 56.1 dB at the receive signal center frequency (f=160 kHz) and ampli es the receive signal amplitude to the maximum dynamic range. The lter section is to prevent the ADC and the peak hold section from erroneous operation caused by high-frequency noise. Peak hold is performed during the initial training so that the gain of the AGC section is set to make best communication condition. The ADC section makes an A/D conversion of the received signal and transfers it to YTD426B. The A/D conversion timing is synchronized to the clock (ADCK) provided by YTD426B. The digital section provides the interface to YTD426B. Filter Peak Hold section ADC Digital Interface 11 12 CHAPTER 4. FUNCTIONS Chapter 5 ELECTRICAL CHARACTERISTICS 5.1 Absolute Maximum Ratings (DVSS =AVSS=0.0V Ta=25 ) Supply Voltage (Digital) DVDD 00:3 +7.0 V Supply Voltage (Analog) AVDD 00:3 +7.0 V Input Voltage (Digital) DVIN DVSS 0 0:3 DVDD+0.3 V Input Voltage (Analog) AVIN AVSS 0 0:3 AVDD+0.3 V Output Voltage (Digital) DVOUT DVSS 0 0:3 DVDD+0.3 V Output Voltage (Analog) AVOUT AVSS 0 0:3 AVDD+0.3 V Power Dissipation PD 400 mW Operating Temperature TOP 020 +70 Storage Temperature TST 055 +125 Note 1 The values represent the minimum and maximum voltages that can be applied to the pins without causing damage. It does not guarantee the operation. Applying a voltage exceeding the absolute maximum ratings may cause permanent damage to YTD427. Note 2 Use digital power supply DVDD and analog power supply AVDD under the condition: DVDD = AVDD. Also, insert a C 0.1F across DVDD and DVSS and across AVDD and AVSS to prevent latch up. Note 3 Use digital ground DVSS and analog ground AVSS under the condition: DVSS = AVSS . Note 4 Even though digital power supply DVDD and analog power supply AVDD have the same pin name, they are not connected inside YTD427. Make sure to connect the pins that have the same name. Note 5 Even though digital ground DVSS and analog ground AVSS have the same pin name, they are not connected inside YTD427. Make sure to connect the pins that have the same name. Parameters Symbol Min. Max. Units 13 14 5.2 CHAPTER 5. ELECTRICAL CHARACTERISTICS Recommended Operating Conditions (DVSS =AVSS=0.0V Ta=25 ) Digital Power Supply Voltage DVDD 4.75 5.0 Analog Power Supply Voltage AVDD 4.75 5.0 Digital Input Voltage DVIN DVSS Analog Input Voltage AVIN AVSS Digital Output Voltage DVIN DVSS Analog Output Voltage AVIN AVSS Operating Temperature Range TOP 020 25 External Clock Input Clock Frequency fCP (Note1) 0.64 Clock Frequency Allowable Deviation 1fCP (Note1) 050 Clock Duty tDUTY (Note1) 45 50 High Level Time tWCH (Note1) 400 Low Level Time tWCL (Note1) 400 Rise Time tTLHC (Note1) Fall Time tTHLC (Note1) YTD426 Supply Input Signal High-Level Pulse Width tWDH (Note2) 90 Low-Level Pulse Width tWDL (Note2) 90 Rise Time tTLHD (Note2) Fall Time tTHLD (Note2) Note 1 With respect to ADCK pin. Note 2 With respect to A1, A0, RWN, STRBN, D15 to D0 pins. Parameters Symbol Condition Min. Typ. Max. Units 5.25 5.25 DVDD AVDD DVDD AVDD 70 50 55 20 20 10 10 V V V V V V MHz ppm % ns ns ns ns ns ns ns ns 5.3. DC CHARACTERISTICS 15 5.3 DC Characteristics (DVDD=AVDD=4.75 5.25V, DVSS=AVSS=0.0V, Ta=25 ) High-Level Input VIHC (Note1) 0.7DVDD DVDD V Voltage (CMOS) Low-Level Input VILC (Note1) 0.0 0.3DVDD V Voltage (CMOS) Input Leak ILIC (Note1) 610 A Current (CMOS) (Note2) High-Level VIHT (Note3) 2.0 DVDD V Input Voltage (TTL) Low-Level Input VILT (Note3) 0.0 0.8 V Voltage (TTL) Input Leak ILIT (Note3) 610 A Current (TTL) (Note4) High-Level Output VOHT (Note3) 4.4 V Voltage (TTL) (Note5) Low-Level Output VOLT (Note3) 0.4 V Voltage (TTL) (Note6) Supply Current IDD1 (Note7) 14.4 24.9 mA (Normal) Supply Current IDD4 (Note7) 4.4 7.6 mA (at reset) (Note8) Power Consumption Ptot1 (Note7) 72 131 mW (Normal) Power Consumption Ptot4 (Note7) 22 40 mW (at reset) (Note8) Note1 With respect to ADCK, TEST4, TEST2 to TEST0, RSTN, FTHN, NC4 to NC1 pins. Note2 VIC =DVSS - DVDD Note3 With respect to A1, A0, RWN, STRBN, D15 to D0, TEST3, TEST5, TEST6 pins. Note4 VIT =DVSS - DVDD Note5 IOH =04mA Note6 IOL =12mA Note7 Neither external circuit nor parts Note8 ADCK pin xed to DVSS Parameters Symbol Condition Min. Typ. Max. Units 16 Parameters Symbol Condition ZO (Note1) CHAPTER 5. ELECTRICAL CHARACTERISTICS (DVDD=AVDD=4.75 5.25V, DVSS =AVSS=0.0V, Ta=25 ) Analog Output Allowable 30 Load Impedance Analog Receive Buer Zi1 (Note2) 10 Input Impedance Analog Receive Buer Zi2 (Note3) 100 Input Impedance Reference Resistance RREF (Note4) 1.92 2.40 3.84 Voltage Divider RDIV (Note5) 1.44 1.80 2.88 Resistance Analog Signal Reference VSG (Note6) 0.5AVDD-0.05 0.5AVDD 0.5AVDD+0.05 Voltage ADC High-Level Reference VRT (Note7) 0.7AVDD AVDD Voltage Level Low-Level Reference VRB (Note8) 0.0 0.3AVDD Voltage Level Self-Bias VRT VRTS (Note9) 0.7AVDD-0.1 0.7AVDD 0.7AVDD+0.1 Self-Bias VRB VRBS (Note10) 0.3AVDD-0.1 0.3AVDD 0.3AVDD+0.1 Note1 With respect to SGR, SXA pins. Note2 With respect to RXU pin. Note3 With respect to SXB pin. Note4 Across VRT and VRB pins. VRB=1.5 V Note5 Across VRT and AVDD pins and across VRB and AVSS pins. Note6 SGR pin is open. Note7 With respect to VRT pin. Note8 With respect to VRB pin. Note9 Short VRT pin and VRTS pin Note10 Short VRB pin and VRBS pin Min. Typ. Max. Units k k k k V V V V V M 5.4. AC CHARACTERISTICS 17 5.4 AC Characteristics (DVDD=AVDD=4.75 5.25V, DVSS=AVSS=0.0V, Ta=25 ) Total Harmonic Distortion THD Gain GA AGC Noise Noag DC Oset Voltage Vago Filter Cut O Frequency fc Flatness Ap Max. Conversion Time FPH PH Refresh Time tphr Peak Hold Error Vphe Resolution Res Linearity Error EL ADC Quantization Error Ee Max. Conversion Time FAD Clock Frequency FADCK Parameters Symbol Condition Min. Typ. Max. 1.0 % 43.76 45.76 47.76 dB 6 mVrms 650 mV 213 320 427 kHz 01:0 0.0 1.0 dB 160 200 kHz 60 100 ns 650 mV 8 Bit 61.0 62.0 LSB 01:0 1.0 LSB 1.28 MSPS 640 kHz Units 18 CHAPTER 5. ELECTRICAL CHARACTERISTICS Chapter 6 PACKAGE OUTLINE 18.70 0.40 14.00 48 0.20 33 49 32 0.20 14.00 64 2.60 MAX. (Installation height) 17 0.10 (STAND OFF) 1 16 P-0.80 TYP. 0.20 0.35 0.10 0.10 2.20 (2.35 0.20) 0-10 (1.50 LEAD THICKNESS : 0.15 +0.10 -0.05 0.20) (UNIT) : mm (millimeters) The shape of the molded corner may be slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. Note : The LSIs for surface mount need special consideration on storage and soldering conditions. For detailed information, please contact your nearest Yamaha agent. 19 18.70 0.40 20 CHAPTER 6. PACKAGE OUTLINE Appendix A EXMAPLE OF APPLICATIONS A.1 Example of Application Circuits An example of an application circuit using YTD427 is shown in Figure A.1. YTD426B S/T reference point TTL interface ADDRES0,1 AFEDATA0 15 RWN STRBN CLK64 TAMIRP TAMIRM TAMITP TAMITM 15.36MHz RESET CLK1536 RESET RESET CLKOUT CLK256K CLK192K CLK400 LOOP2A QINFO1C RBHW TESTOUT0 15 NC A0,A1 D0 D15 RWN STRBN ADCK RSTN AV SS x4 10k TEST3 FTHN A YTD427 DV DD x4 0.1u DV SS x4 AV DD AV DD x4 0.1u NC1 4 TEST0,1,2,4,5,6 SGA 0.0047u(10%) RXS 10k 10k 10k 10k 10k 10k 10k 10k 10k x16 10k 10k x2 10k 10k x5 EXID TSMPSEL TSMPAUT TRPSEL MULTI IOSEL BCHIF MASLV TESTIN0 11,13,15,16,17 TESTN18 TESTIN22,23 TESTUDR TMODE0 4 ATEI V DD 1u V SS A 0.0022u(10%) SGB 0.015u(10%) ATEO 0.1u VRBS VRB A SGBP 0.15u(10%) SXA 0.1u VRTS VRT A U reference point SXB SGR RXU 0.33u(10%) 1.2k(1%) A POWMON EXTCLK TBHW RSYNC,TSYNC LPA,LP4B1,LP4B2 BCHSET0,1,2 TESTIN12,14 TESTIN19,20,21,24 3.9k(1%) TRTEPC9.8-0319C TDK 8 7 6 5 4 3 2 1 1u/160V 15(1/2W) KP15N14 KP4N12 UAMITP UAMITM 2SJ278 8(1%) 2SK2315 UAMITMN UAMITPN 2SJ278 8(1%) 0.01u(10%) VRYA15 15(1/2W) KP15N14 (3.3uH) 2SK2315 (3.3uH) TDK NL322522T-3R3J Line activation circuit Figure A.1: Pin Connection Example 21 |
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