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JTMP0360-002S
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
JTMP0360-002S
LSI for LCD Watches
1. Summary
The JTMP0360-002S is a low-power LSI for watches with chronograph functions. This LSI features a chronograph, lap memory, an alarm function, and a built-in LCD driver.
1.1
Feature
* Bar graph chronograph and elapsed time displays * Lap memory (max 10 laps) * Lap/split time selectable * 3.0 V single power supply * Alarm/time signal function * 12/24-hour display selectable
000707EBA1
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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1.2 Block Diagram
SEG1~SEG20
COM1~COM8
BZ
TIMER SELECT
SEGMENT BUFFER
DISPLAY TIMING GENERATOR
BUZZER CONTROLLER
100 ms STOP WATCH
OT4
DISPLAY RAM
DECODER (ID)
INSTRUCTION
OT3
ROW OT2
COLUMN
LAP REGESTAR
SYSTEM CONTROL SIGNAL
DATA RAM
CNT
OT1
T IO21~IO24 IO2
X
Y
IO11~IO14
ION1
Acc
AD
CARRY
Ca
A/S
IN21~IN22
*1
CIN
S
A
IN11~IN14
DOUBLER HALVER BACK UP
TIMMING GENERATOR (TG) NC
*2
31.25 m
500 ms
125 ms
VDD1
VDD2
VDD3
VDDC
FAI1
FAI2
FAI1~FAI4
AC
PC TEST1
TEST2
VDD1
VDD2
C-
VSS
RIN
*1: Anti-chattering circuit *2: Noise Canceller
ROUT
XO
XI
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1.3 Pin Description (60 pins)
Pin Name Power supply pin Oscillator pin Input pin Output pin Display Pin Input/output pin Test pin Voltage doubler/halver pin Symbol VDD1, VDD2, VDD3, VDDC, VSS, VREG XI, XO, ROUT, RIN IN11~14, IN21, IN22, AC BZ COM1~8, SEG1~20 IO11~14, IO21~24 TEST1, TEST2 FAI1~4 No. of Pins 6 4 7 1 28 8 2 4
1.4
Description of Functions
Pin Name Function Connects low-speed clock oscillator crystal
XI, XO ROUT, RIN IN11~IN14 6-bit input pin. When input to the accumulator, only four bits can be read simultaneously. IN21, IN22 IO11~IO14 Input/output ports with output latch IO21~IO24 BZ FAI1~FAI4 VREG TEST1, TEST2 AC VSS VDD1 VDD2 VDD3 VDDC SEG1~20 COM1~8 Mainly for buzzer, alarm, and time signal output For 0.1 F voltage doubler/halver capacitor connection For testing (by Toshiba) at shipping. Fix to LOW. For system setting 0 V (GND) Connects to VSS via 0.1 F capacitor (1.5 V at voltage step-down) 3V Connects to VSS via 0.1 F capacitor (3.0 V at voltage step-down) Connects to VSS via 0.1 F capacitor Outputs segment signals Outputs common signals
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1.5 Pad Layout
SEG10 COM1 COM2 COM3 COM4 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
IN11 IN12 IN13 IN14 IN21 IN22 XI XO AC TEST1 TEST2 FAI3 FAI4 VDD3 RIN TOP VIEW
VDDC
VREG VSS BZ VDD1 VDD2 FAI1 FAI2 IO24 IO23 IO22 IO21 IO14 IO13 IO12 IO11
COM5
COM6
COM7
COM8
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
ORIGIN (0, 0)
Chip size: 3.52 x 3.33 (mm) Chip thickness: 440 30 (m)
SEG11
ROUT
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1.6 Pad Location Table
(m) IN11 IN12 IN13 IN14 IN21 IN22 XI XO AC TEST1 TEST2 FAI3 FAI4 VDD3 RIN ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, 2784) 2624) 2439) 2279) 2119) 1959) 1799) 1639) 1479) 1319) 1159) 966) 806) 646) 403) IO11 IO12 IO13 IO14 IO21 IO22 IO23 IO24 FAI2 FAI1 VDD2 VDD1 BZ VSS VREG ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 3270, 3270, 3270, 3270, 3270, 3270, 3270, 3270, 3270, 3270, 3270, 3270, 3270, 3270, 3270, 435) 595) 755) 915) 1075) 1235) 1395) 1555) 1715) 1875) 2035) 2195) 2355) 2515) 2784)
ROUT COM5 COM6 COM7 COM8 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11
( ( ( ( ( ( ( ( ( ( ( ( ( ( (
444, 654, 864, 1074, 1283, 1443, 1603, 1763, 1923, 2083, 2243, 2403, 2563, 2723, 2883,
168) 168) 168) 168) 168) 168) 168) 168) 168) 168) 168) 168) 168) 168) 168)
VDDC COM4 COM3 COM2 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10
( ( ( ( ( ( ( ( ( ( ( ( ( ( (
2873, 2713, 2528, 2368, 2183, 2023, 1851, 1691, 1531, 1371, 1211, 1051, 891, 731, 571,
3015) 3015) 3015) 3015) 3015) 3015) 3015) 3015) 3015) 3015) 3015) 3015) 3015) 3015) 3015)
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2. Function Specifications
2.1 Display configuration and segment symbols
RECALL
LAP Bar-9
SPLIT Bar-10 Bar-11 Bar-12
BEST
ALM
CHM
Bar-8 Bar-7
h Bar-2 Bar-6 Bar-1 min1 Bar-3 Bar-13 Bar-4 Bar-5 Bar-14 e f
#15
a b f
#16
a b g h
g e c
i d SEC1 #4 #5 #6
d
c
#1
#2
COL1
#3
#7
BAR
#8
COL2
#9
#10
min2
COL3
SEC2 #11 #12 #13 #14
COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 ALM #16-a #16-f #15-a #15-h #15-f BEST SPLIT LAP RECALL SEC1 #5-a #4-b #4-a min1 #3-a #2-b #2-a
COM2 CHM #16-g #16-e #15-b #15-g #15-e Bar-5 Bar-11 Bar-10 #5-b #5-f #4-g #4-f #3-b #3-f #2-g #2-f #1-a #1-f
COM3 #16-b #16-h #16-d #15-c #15-i #15-d Bar-4 Bar-12 Bar-9 #5-g #5-e #4-c BAR #3-g #3-e #2-c COL1 #1-b #1-e
COM4 #16-c #7-a #7-f #6-b #6-a #6-f Bar-3 Bar-13 Bar-8 #5-c #5-d #4-d #4-e #3-c #3-d #2-d #2-e #1-g #1-d
COM5 #7-b #7-g #7-e #6-c #6-g #6-e Bar-2 Bar-14 Bar-7 SEC2 #12-a #11-b #11-a MIN2 #10-a #9-b #9-a #1-c #8-a
COM6 #7-c #14-a #7-d #13-b #13-a #6-d Bar-1 Bar-6 #12-b #12-f #11-g #11-f #10-b #10-f #9-g #9-f #8-b #8-f
COM7 #14-b #14-g #14-f #13-c #13-g #13-f #12-g #12-e #11-c COL3 #10-g #10-e #9-c COL2 #8-g #8-e
COM8 #14-c #14-d #14-e
#13-d #13-e #12-c #12-d #11-d #11-e #10-c #10-d #9-d #9-e #8-c #8-d
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2.2 LCD connection diagram
SEG10 COM1 COM2 COM3 COM4
2 1 2 3 2 1 2 3 3 4 3 4 4 5 4 4 5 6 5 5 6 4 5 6 5 6 6 7 8 8 8 8 7 8 8 7 7 8 7
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
RECALL 1
LAP 1
SPLIT 1
BEST 1
SEG1
1 3 4 5 4 5 6 6 3 2 2 5 3 3 2 2 3 1 4 1 1 2
1 2 2 4 3 4 4 4 4 5 3 4 3 3 2 2 3 3 1 1 2 3 4 1 2 3 4 2 2 3 3 1 1 2 3 1 2
1
1
4 4
5 5 5 6 7 7 8 8 7 8 8 6 7 6 6 7 7 8 5 6 7 8 7 8 8 6 7 6 6 7 7 5 6 7 6 5 5 5
5
5
6 7
COM5
COM6
COM7
COM8
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
Note:
The figures in the display are common numbers. Segment Common
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2.3 Liquid crystal display
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2.4 Liquid crystal drive wave forms
1 Frame VDD3 VDD2 COM1 VDD1 VSS VDD3 VDD2 COM2 VDD1 VSS VDD3 VDD2 VDD1 VSS
1 Frame
COM3
VDD3 VDD2 COM4 VDD1 VSS VDD3 COM5 VDD2 VDD1 VSS VDD3 COM6 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS
COM7
VDD3 COM8 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS 15.6 ms 1.95 ms
SEG
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2.5 Display
2.5.1 TIME mode display
ALM CHM
0
10
20
30
40
50
1
11
21
31
41
51
2
12
22
32
42
52
3
13
23
33
43
53
4
14
24
34
44
54
5
15
25
35
45
55
6
16
26
36
46
56
7
17
27
37
47
57
8
18
28
38
48
58
9
19
29
39
49
59
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2.5.2 CHRONO mode display
LAP ALM CHM
0.0
1.0
2.0
3.0
4.0
0.1
1.1
2.1
3.1
4.1
0.2
1.2
2.2
3.2
4.2
0.3
1.3
2.3
3.3
4.3
0.4
1.4
2.4
3.4
4.4
0.5
1.5
2.5
3.5
4.5
0.6
1.6
2.6
3.6
4.6
0.7
1.7
2.7
3.7
4.7
0.8
1.8
2.8
3.8
4.8
0.9
1.9
2.9
3.9
4.9
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5.0
6.0
7.0
8.0
9.0
5.1
6.1
7.1
8.1
9.1
5.2
6.2
7.2
8.2
9.2
5.3
6.3
7.3
8.3
9.3
5.4
6.4
7.4
8.4
9.4
5.5
6.5
7.5
8.5
9.5
5.6
6.6
7.6
8.6
9.6
5.7
6.7
7.7
8.7
9.7
5.8
6.8
7.8
8.8
9.8
5.9
6.9
7.9
8.9
9.9
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2.5.3 MEMORY RECALL mode display
RECALL LAP ALM CHM
2.5.4 ALARM mode display
(1) Alarm display
ALM CHM
(2)
Time signal display
ALM CHM
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2.6 Mode transition diagram
TIME mode 12/24 H S2 Time-of-day "00" S4 (2 s HOLD) S3 S1 S3 S4 CHRONO mode START/STOP LAP/RESET S1 S2 S1 Chrono (LAP) * (2 s HOLD) START/STOP S4 SPLIT/RESET S2 S1 S1 Chrono (SPLIT) S3 MEMORY RECALL mode Chrono (LAP) LAP1 TOTAL1 S2 S4 Second
TIME SETTING mode
S2 S1 S3 S2 S1 S3
minute
S2 S1 S3 S2 S1 S3
Hour
S2 S3
Day of week
Day of month
Month
S2
S2 RUN1
LAP1 RUN2
S2
LAP2 RUN3
S2 RUN
SPLIT1 RUN S4
S2
SPLIT2 RUN
BEST S4
S4
S1
S1
LAP2 TOTAL2
S2
S1
LAP10 TOTAL10
S2
S1 LAP STOP TOTAL
S2
Chrono (SPLIT) S1 S2 SPLIT1 TOTAL
S1
SPLIT2 TOTAL
S2
S1
SPLIT10 TOTAL
S2
S1 SPLIT STOP S2 TOTAL
S3
S1
ALM OFF CHM OFF ALM ON CHM ON
S1
ALM ON CHM OFF ALM OFF CHM ON
S1
ALARM mode S4 S1
ALARM SETTING mode S2 S1 S3
Alarm S2
Time S4 S1 Minute
minute S4
*1: When LAP or SPLIT are set to STOP, S4 is S1 enabled. In the RUN state, S4 is disabled. Switching between LAP and SPLIT resets S2 S3 LAP or SPLIT and the data stored in MEMORY RECALL mode.
Time signal S3
S4
S2
Note: For S1, S2, S3 and S4, see the corresponding example circuit.
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2.7 Mode description
2.7.1 TIME mode
TIME mode is used to display the current time and make time settings. * Middle row columns #2 and #3 display the month, columns #4 and #5 display the day of the month with unnecessary zeros suppressed. * Upper row columns #15 and #16 display the day of the week. * Lower row column #8 displays AM/PM. * Lower row columns #9 and #10 display the hour, columns #11 and #12 display minutes, and #13 and #14 display seconds. * The ON/OFF states of the time signal and alarm are displayed in the upper right corner. * When the alarm or time signal is set, the alarm or time signal sign in the top row flashes. When the LAP or SPLIT functions are running in CHRONO mode, the LAP or SPLIT signs flash. * Pressing multiple switches simultaneously invalidates the switches pressed. * Pressing a second switch while still pressing the first invalidates both switches. * S2 can be used to switch between a 12-and 24-hour clock. Such switching can only be performed in TIME mode. (a) 12-hour clock
ALM CHM
(b)
24-hour clock
ALM CHM
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2.7.2 TIME SETTING mode
* Access TIME SETTING mode by pressing S4 for two seconds in TIME mode. * Pressing S3 in TIME SETTING mode displays in turn the seconds, the minutes, the hour, the month, the day of the month, the day of the week, then the seconds again. Set each while it is flashing. * In TIME SETTING mode, the ALM/CHM signs turn OFF and the sound is disabled even if they were set ON before entering TIME SETTING mode. When returning from TIME SETTING mode to TIME mode, the ALM/CHM sign returns to the status before the switch to TIME SETTING mode. * In TIME SETTING mode, pressing S4 switches to TIME mode. S4 can be pressed from the second, minute, month, day of the month, or day of the week displays. * If any switch is not pressed for one minute in TIME SETTING mode, the device automatically switches to TIME mode. * Pressing multiple switches simultaneously invalidates the switches pressed. * Pressing a second switch while still pressing the first invalidates both switches. (a) Setting the seconds * Pressing S2 swich seconds display is 0-29, the seconds are simply set to "00". If the seconds display is 30-59, the seconds are simply set to "00" and one minute is incremented. *: S1 is invalid
(b)
Setting the minutes * Use S1 or S2 to set the minutes. Each press of S1 increments the time by one minute. Pressing S2 decrements the time by one minute. Pressing either S1 or S2 for two seconds fast-winds the time at a speed of 4 Hz for as long as the switch is depressed. Pressing another switch during the fast winding immediately cancels the fast winding. To return to fast winding, press S1 or S2 as above after releasing all other switches. The count range is 0~59.
*
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(c) Setting the hour * Use S1 and S2 to set the hour as in "Setting the minutes". Displays the range: For 12-hour clock AM12~11 For 24-hour clock 0~23 PM12~11
(d)
Setting the month * Use S1 or S2 to set the month as in "Setting the minutes". Displays the range: 1~12
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(e) Setting the day of the month * Use S1 and S2 to set the day of the month as in "Setting the minutes". For January, March, May, July, August, October, and December, the range displayed is: 1~31 For April, June, September, and November, the range displayed is: 1~30 For February, the range displayed is: 1~29 (f) Setting the day of the week * Use S1 or S2 to correct the month as in "Correcting the minutes". Displays the range: SU~SA
*: TIME SETTING mode can display some days of the month that do not actually exist (February 30, February 31, April 31, June 31, September 31, November 31). When switching from TIME SETTING mode to TIME mode, the first day of the following month is displayed. (Example) February 30 in TIME SETTING mode, S4 becomes March 1 in TIME mode.
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2.7.3 CHRONO mode
CHRONO mode displays lap and split time. * Middle and lower row columns #1 and #8 display the hour; columns #2 and #3, and #9 and #10 display the minutes ; columns #4 and #5, and #11 and #12 display the seconds; columns #6 and #13 display tenths of seconds ; and columns #7 and #14 display hundredths of seconds. * The middle row displays lap and split time. * Upper row columns #15 and #16 display the lap or split count number. * The lower row displays the RUN time. * Clocking is up to 9 hours, 59 minutes, 59 seconds, 99 hundredths of seconds. * In the RUN state, after 9 hours and 59 minutes, 59 seconds, and 99 hundredths of seconds, the count-up returns to 0, but because of zero suppression, the counting starts from display of a single zero. * Displays the ALM/CHM ON/OFF status. * In CHRONO mode, a switch-push sound is generated when S1 or S2 are pressed. In the case of S4, the sound is generated after S4 is held for two seconds. * To switch between lap and split, depress S4 for two seconds. This resets the lap or split display. (Switching is indicated by the switch-push sound. Lap/split switching also resets the data stored in MEMORY RECALL mode. During the RUN state, S4 is invalid and cannot be used for switching. * The lap/split count number starts from 01. When 99 is reached, the count returns to 00. This cycle is repeated indefinitely. * After an ALL CLEAR in CHRONO mode, the LAP mode reset state is displayed. * If other switches are pressed at the same time as S1, S1 takes precedence. * Pressing switches other than S1 at the same time invalidates the switches pressed. * Pressing a second switch while still pressing the first, unless the first switch is S1, invalidates both switches. (1) LAP mode display (a) Reset state
LAP ALM CHM
* *
In LAP mode, after a reset and in a state other than RUN, the display is as at left. The LAP sign at the top of the display is lit.
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(b) RUN 1 state
LAP
Lap 0
ALM CHM
*
*
Pressing S1 sets the watch to RUN. The RUN state is displayed (zero suppressed) in the lower row. The graphic display in the upper row functions at the same time. As long as lap time is not recorded, the middle row display is blank. *: Once a digit is displayed in this column, the digit will not be zero suppressed. However, pressing S2 (lap) resets and zero suppresses the lower row.
(c)
RUN 2 state
LAP
Lap 1
BEST ALM CHM
*
*
In lap 0, RUN 1 state, pressing S2 displays the lap time in the middle row, and the lap number at the far right of the upper row. Also, pressing S2 in lap 0, RUN 1 state resets the time display in the lower row and starts the count from 0. If lap time is measured when no other lap time is recorded, the lap time recorded is the "best lap" time, and the best lap function is activated.
If another lap time is recorded, it is compared to the current best time. If the lap time is shorter than the current best lap time, the best lap function is activated. If the lap time is longer than the current best lap time, the best lap function is not activated. If the lap time is the same as the current best lap time, the lap time recorded first remains the best lap time. Therefore, where same lap times are recorded, the best lap function is not activated. *: Best lap function The best lap is the fastest lap. When a best lap time occurs, the BEST sign in the top row flashes at 2 Hz, and the best time sound is output. While the best lap time remains displayed in the middle row, the BEST sign in the top row continues flashing.
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(d) RUN 3 state
LAP
Lap 2
ALM CHM
*
Compares the best lap time with the current lap. Because the current lap time is longer, the BEST sign is not lit.
(e)
RUN 3 stop state
LAP ALM CHM
* *
Pressing S1 stops the RUN state. Even if the time to when the count stops is shorter than the best time, that time is ignored because it is not a full lap time.
*: Even if the count is stopped with the BEST sign still flashing, the BEST sign continues to flash. If the count is restarted, the BEST sign continues flashing because the best lap time is displayed in the middle row. *: During best time sound output (during RUN state) * * * If the count is stopped by pressing S1, the S1 switch-push sound takes precedence. If the best time sound is ON, it stops immediately. If the lap is recorded using S2, the S2 switch-push sound takes precedence. If the best time sound is ON, it stops immediately. If the lap is recorded using S2 and that lap time is a best time, the S2 switch-push sound takes precedence. If the best time sound is ON, it stops immediately, then starts again after the S2 switch-push sound ends. If the mode is switched using S3, the switch-push sound is not output. However, the best time sound stops immediately and the device switches to MEMORY RECALL mode. Except for pressing S4 and S1 together, pressing more than one switch at the same time invalidates both switches. Therefore, the best time sound continues.
* *
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(2) SPLIT mode display (a) Reset state
SPLIT ALM CHM
*
Executing a reset in SPLIT mode produces the display shown at left.
(b)
RUN state
Split 0
SPLIT ALM CHM
*
Pressing S1 sets the device to RUN and displays the RUN count in the lower row. The upper row graphic display comes on at the same time. (The lower row RUN count display is zero suppressed.)
(c)
RUN state Split 1
SPLIT ALM CHM
*
Pressing S2 in RUN split 0 state displays the time elapsed as split time in the middle row, and displays the split number at the right end of the upper row.
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(d) RUN state Split 2
SPLIT ALM CHM
*
Split 2 functions the same as RUN split 1. Pressing S2 updates the time displayed in the middle row with the time elapsed from start, which becomes the new split time, and displays the split number at the right end of the upper row.
(e)
RUN stop state
SPLIT ALM CHM
* *
Pressing S1 stops the RUN count. Pressing S2 after stopping the RUN count displays the reset state. *: The RUN time displayed in the lower row in SPLIT mode is not reset when split data is recorded. Once a digit is displayed in this column the digit will not be zero suppressed.
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2.7.4 MEMORY RECALL mode
MEMORY RECALL mode stores and displays the lap or split data recorded in CHRONO mode. * Middle and lower row columns #1 and #8 display the hour; columns #2 and #3, and #9 and #10 display the minutes; columns #4 and #5, and #11 and #12 display the seconds; columns #6 and #13 display tenths of seconds; and columns #7 and #14 display hundredths of seconds. Upper row columns #15 and #16 display the lap or split number. * The upper row displays the lap or split numbers. The middle row displays the data of the lap or split numbers. The lower row display varies according to which of split or lap data is displayed. For lap time, the lower row shows the time elapsed from the start time to the lap number, in accordance with the lap number at that time. For split time, the lower row shows the total time elapsed irrespective of the split number. * This mode does not support a graphic display. * Up to 10 units of data in addition to time data can be stored and displayed. * MEMORY RECALL mode cannot include both lap data and split data. Either lap or split data is displayed immediately before switching out of CHRONO mode. MEMORY RECALL mode can include one but not both. * In CHRONO mode, performing lap/split switching by depressing S4 for two seconds clears the MEMORY RECALL data. If lap is selected for CHRONO mode, the LAP sign is displayed in MEMORY RECALL mode and lap data is displayed. If split is selected for CHRONO mode, the SPLIT sign is displayed in MEMORY RECALL mode and split data is displayed.
* If 10 or fewer units of data are recorded, all the data and stop times are displayed continuously. If over 10
units of data are recorded, only the latest ten units of data are stored and older data is deleted.
* The lap/split numbers start from 01 and continue to 99. After 99, the count returns to 00, 01, 02 up to 99
again, then repeats.
* After switching from MEMORY RECALL mode with lap or split data displayed to another mode, then
returning to MEMORY RECALL mode, MEMORY RECALL mode displays the lap or split data from the lowest number, regardless of the number at the time the previous mode was switched. (As long as you did not start in CHRONO mode or did not switch between lap and split after leaving MEMORY RECALL mode.)
* MEMORY RECALL mode simultaneously displays the ON/OFF status of both ALM/CHM (alarm and
chime).
* Pressing multiple switches simultaneously invalidates the switches pressed. * Pressing a second switch while still pressing the first invalidates both switches.
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(1) LAP mode (a) Lap n
RECALL LAP BEST ALM CHM
*
After lap data is recorded in CHRONO mode, switching to MEMORY RECALL mode displays the data in the middle row starting from the lowest lap number. The lower row displays the total time from the start to the applicable lap number. Where a best lap is stored in memory, the BEST sign is lit while the data of that lap is displayed.
* *
(b)
Lap n + 1
RECALL LAP ALM CHM
* *
Pressing S1 displays the next lap data. Pressing S2 displays the previous lap data. For the applicable lap number, the lower row displays the total time from the start.
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(c) Lap stop
RECALL LAP ALM CHM
*
The data at the point the count was stopped is displayed in the middle row. The lower row displays the total time from start to stop. The upper row shows " " as at left.
(d)
Best lap
RECALL LAP BEST ALM CHM
*
Whatever data is displayed in MEMORY RECALL mode, while S4 is depressed, the best lap time is displayed. (If another switch is pressed while S4 is depressed, the display returns to the lap or stop data displayed before switching to the best lap time display. When S4 is released, the display returns to the lap or stop data displayed before switching to the best lap time display. In the best lap time display, the lap number appears in the upper row. The best lap time is displayed in the middle row, as at left. The best time is the fastest time among all the lap times recorded. Where a lap number n (100 < n) is the same as the best time number n (100 > n), the BEST sign is not lit even though lap number n, which is not the best time, is displayed.
*
*
*
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* When S3 is pressed with LAP mode only selected in CHRONO mode, the display is as at left when MEMORY RECALL mode is entered. The best lap time is as in Figure 2. *: When an ALL CLEAR is executed and reset MEMORY RECALL mode is executed (when switching from split to lap in CHRONO mode), the display is as in Figure 1.
RECALL LAP
Figure 1
RECALL
LAP
BEST
Figure 2
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* When recording lap n in LAP mode and pressing S3 with the count running to switch into MEMORY RECALL mode, the data up to lap n is displayed. (Lap 1 < Lap 2)
Start Lap 1 Lap 2 Switching to MEMORY RECALL mode
A B
(MEMORY RECALL mode display)
RECALL
LAP
BEST
ALM CHM
RECALL
LAP
ALM CHM
S1 A A
S2
S1 B A+B
S2
display
display
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* In CHRONO mode, if you start a lap n, record, then stop and restart, the count starts from the stop time. The data following lap n + 1 continues from the stop time. (The counting from the previous stop time continues until a reset.) *: Lap 1 < Lap 2

Start Lap 1 Stop Restart Lap 2 Stop
A B C D
(MEMORY RECALL mode display when start lap 1 stop.)
RECALL
LAP
BEST
ALM CHM
RECALL
LAP
ALM CHM
S1 A A
S2 S1 B A+B
S2

(MEMORY RECALL mode display when start lap 1 stop restart lap 2 stop.)
RECALL
LAP
BEST
ALM CHM
RECALL
LAP
ALM CHM
RECALL
LAP
ALM CHM
S1 A A
S2 S1 B+C A + B+ C
S2 S1 D A+B+C+D
S2

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(2) Split mode display (a) Split n
RECALL SPLIT ALM CHM
*
When entering MEMORY mode after recording split data in CHRONO mode, data is displayed in the middle row starting from the lowest split number. The lower row displays the total time, irrespective of the split number.
*
(b)
Split n + 1
RECALL SPLIT ALM CHM
*
Each press of S1 displays the next split data. Each press of S2 displays the previous split data. The lower row displays the final (at STOP) total time.
*
(c)
Split stop
RECALL SPLIT ALM CHM
*
As the middle row displays the data for when the count was last stopped, this is the same data as in the lower row. The upper row shows " " as at left.
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* With only the split mode activated in CHRONO mode, pressing S3 to enter MEMORY RECALL mode produces a display as below. Resetting MEMORY RECALL mode (switching from lap to split) also produces a display as below.
RECALL
SPLIT
* When recording split n in SPLIT mode and pressing S3 with the count running to switch into MEMORY RECALL mode, the data up to split n is displayed.

Start Split 1 Split 2 Switch to MEMORY RECALL mode
A B
(Display in MEMORY RECALL mode)
RECALL
SPILT
ALM CHM
RECALL
SPILT
ALM CHM
S1 A A+B
S2
S1 A+B A+B
S2
display
display
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* In CHRONO mode, if you start a split n count, record, then stop and restart, the count from the stop time. The data following split n + 1 continues from the stop time. (The data continues until a reset.)

Start Split 1 Stop Restart Split 2 Stop
A B C D
(MEMORY RECALL mode display when start split 1 stop.)
RECALL
SPLIT
ALM CHM
RECALL
SPLIT
ALM CHM
S1 A A+B
S2 S1 A+B A+B
S2

(MEMORY RECALL mode display when start split 1 stop restart split 2 stop.)
RECALL
SPLIT
ALM CHM
RECALL
SPLIT
ALM CHM
RECALL
SPLIT
ALM CHM
S1 A A+B+C+D
S2 S1 A + B+ C A+B+C+D
S2 S1 A+B+C+D A+B+C+D
S2

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2.7.5 ALARM mode
ALARM mode is used to set and display the alarm and time signal. * In this mode, the graphic display and upper row columns #15 and #16 go OFF. * In MEMORY RECALL mode, press S3 to switch to ALARM mode. * The alarm and time signal ON/OFF states are displayed by the upper right sign. (Lit: ON, unlit: OFF) * In ALARM mode, each press of S1 turns the alarm ON, time signal OFF alarm OFF, time signal ON alarm/time signal ON alarm/time signal OFF alarm ON, time signal OFF... * In ALARM mode, depressing S1 for two seconds sounds a test alarm. While S1 is depressed, the alarm continues sounding. (When the alarm is sounding, pressing another switch turns the alarm sound OFF. If the test alarm is sounding when the preset alarm or time signal are due to come ON, the test alarm tone takes precedence and the set alarm or time signal chime do not sound.) * If the settings for the alarm and time signal are for the same time, the alarm takes precedence. * The ALARM mode does not allow 12-hour/24-hour clock switching. (Such switching is supported only in TIME mode.) The 12-hour and 24-hour clocks conform to TIME mode. * Press S2 to switch between the alarm and time signal displays. * After ALL CLEAR, the alarm display shows "AM12:00" if the 12-hour clock is selected, and "0:00" if the 24-hour clock is selected. After the ALL CLEAR, the time signal display shows "00". * Pressing multiple switches simultaneously invalidates the switches pressed. * Pressing a second switch while still pressing the first invalidates both switches.
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Alarm/time signal (a) Alarm display
ALM CHM
* *
The middle row displays "AL". The bottom row displays the set time-of-day. Press S2 to switch between the alarm and time signal.
(b)
Time signal display
ALM CHM
*
The middle row displays "CH". The bottom row displays the set minutes of the hour.
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2.7.6 ALARM SETTING mode
* Press S4 while the alarm or time signal is displayed to switch to ALARM SETTING mode for the alarm or time signal. * If a switch is not pressed for one minute while in ALARM SETTING mode, the device automatically switches to ALARM mode. * When switching to ALARM SETTING mode from ALARM mode, even if the alarm/time signal are set, the ALM or CHM sign goes OFF and the alarm and chime (time signal) sounds are disabled. * In ALARM SETTING mode, press S4 to switch to ALARM mode. When switching to ALARM mode from ALARM SETTING mode, the alarm is set and the ALM sign is lit. The CHM sign returns to the status prevailing before switching to ALARM SETTING mode. When switching to ALARM mode from ALARM SETTING mode for the time signal, the time signal is set and the CHM sign is lit. The ALM sign returns to the status prevailing before switching to ALARM SETTING mode. * The method of correcting the alarm hour and minutes, and the method of correcting the time signal minutes is the same as for correcting the hour and minutes in TIME SETTING mode. Press S3 to switch between the alarm hours and minutes to be set. * Pressing multiple switches simultaneously invalidates the switches pressed. * Pressing a second switch while still pressing the first invalidates both switches.
2.7.7 ALARM functions
* With the ALM sign lit, when the current time matches the set alarm time, the alarm sounds for 20 seconds. * In ALARM SETTING mode, even if the set alarm time matches the current time, the alarm will not sound. * To stop the alarm sound in any mode except ALARM SETTING mode, press any one of switches S1~S4. * If the alarm sound comes on while you are depressing a switch in any mode except SETTING mode, release the switch then press it again to stop the alarm sounding. * While switching from TIME mode to TIME SETTING mode by depressing S4 for two seconds (in TIME mode), the alarm will sound if the set alarm time matches the current time. However, keep S4 depressed. As soon as the mode is switched, the alarm sound and the ALM sign go off.
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2.7.8 ALL CLEAR
After an ALL CLEAR, TIME mode is selected. The count starts from January 1 (Sunday) AM12 hours, 0 minutes, 0 seconds. After an ALL CLEAR, the display is as below.
2.7.9 ALL segments lit
Immediately after an ALL CLEAR, press S4 (until the display comes ON) to light all segments (the display is as below). Then, to switch from all segments being lit to TIME mode, push any one of S1~S4. *: After an ALL CLEAR, TIME mode starts counting. Therefore, when you return to TIME mode, the time count has advanced.
RECALL
LAP
SPLIT
BEST
ALM CHM
Timing flow chart
ACR S4 1s Disp All lit
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2.7.10 Alarm waveform

0.0625 (s) 0.0625 (s) 0.0625 (s) 0.0625 (s) 4 kHz 0.0625 (s) 0.0625 (s) 1 (s) x 20 0.0625 (s) 0.0625 (s) 0.5 (s)

0.0625 (s) 0.0625 (s)
4 kHz 0.0625 (s) 0.0625 (s)

0.0625 (s)
4 kHz

0.5 (s) 4 kHz 0.5 (s) 1 (s)
2.8
ALL Clear function
When power is applied or when the supply of power is interrupted (e.g. if the battery is changed), the internal state of the IC may become unstable, even though it appears to be operating normally. For this reason it is vital to verify that the crystal oscillation circuit is oscillating normally and stably (at 32 kHz) and then to use the system reset pin to initialize the IC (i.e. clear it) before use. Note that a clear operation using the built-in power-on clear circuit should not be used in this case. Refer to "5. Handling precautions" for details of ALL Clear function.
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3. Electrical specifications
Maximum Ratings
No. 1 2 3 4 5 6 7 8 9 10 11
(Unless otherwise specified, VSS = 0 V, VDD1 = 1.5 V, VDD2 = 3.0 V, VDD3 = 4.5 V, Ta = 25C)
Characteristics Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) VDD1 system input voltage VDD2 system input voltage VDD3 system Input voltage VDD1 system output withstanding voltage VDD2 system output withstanding voltage VDD3 system output withstanding voltage Operating temperature range Storage temperature range Symbol VSS - VDD1 VSS - VDD2 VSS - VDD3 VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 Topr Tstg Rating -0.2~+3.0 -0.2~+5.0 -0.2~+6.5 VSS - 0.2~VDD1 + 0.2 VSS - 0.2~VDD2 + 0.2 VSS - 0.2~VDD3 + 0.2 VSS - 0.2~VDD1 + 0.2 VSS - 0.2~VDD2 + 0.2 VSS - 0.2~VDD3 + 0.2 -10~+60 -40~+125 Unit V V V V V V V V V C C
Recommended Operating Conditions
Characteristics VDD1 system operating voltage range VDD2 system operating voltage range VDD3 system operating voltage range Low-speed clock crystal oscillator frequency High-speed clock CR oscillator frequency Symbol VDD1 VDD2 VDD3 fXT fCR Test Circuit
(Unless otherwise specified, VSS = 0 V, VDD1 = 1.5 V, VDD2 = 3.0 V, VDD3 = 4.5 V, Ta = 25C)
Test Condition Min 1.20 2.40 3.60 Typ. 1.50 3.00 4.50 32.768 400 Max 1.80 3.60 5.40 Unit V V V kHz kHz Test (Note) Diagram 3.6 3.1 3.1 1
VDD1 No load VDD2 No load VDD3 No load XIN, VDD = 3.0 V XOUT RIN, VDD = 3.0 V ROUT R = 100 k
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DC Characteristics
(Unless otherwise specified, VSS = 0 V, VDD1 = 1.5 V, VDD2 = 3.0 V, VDD3 = 4.5 V, Ta = 25C)
Characteristics VDD1 system leak current VDD2 system leak current VDD3 system leak current VDD1 system step-down voltage VDD3 system step-up voltage Oscillation start voltage Oscillation hold voltage CR Oscillator voltage Dependency Low oscillation frequency VTH dependency Low oscillation Frequency VDD2 dependency Low oscillation frequency CG dependency Oscillator output resistance Built-In CD capacitance Symbol IDD1L IDD2L IDD3L VDCO1 VUCO3 VSTA VHOLD VCR IC VDD2 CG ROUTX CD Applic Test -able Pin Circuit VDD1 VDD2 VDD3 VDD1 VDD3 XIN, XOUT XIN, XOUT RIN, ROUT XIN, XOUT XIN, XOUT XIN, XOUT XIN, XOUT XIN, XOUT Test Condition RL = 3 M RL = 3 M VDD2 = 2.4~3.6 V VDD2 = 2.4~3.6 V CG = 5~20 pF Min 1.4 4.3 2.6 2.4 -30 Typ. 20 250 20 Max 1.0 1.0 1.0 30 8 4 Unit A A A V V V V % ppm ppm ppm k pF Test (Note) Diagram 3.4 3.4 3.4 3.5 3.5 3.3 3.3 3.3 3.3 3.3 3.3 5 8 7, 9 6, 9 9
DC Characteristics (Current dissipation)
CPU Block (VDD - VSS system)
Characteristics High-speed operation mode current dissipation Low-speed operation mode current dissipation STOP mode current dissipation Symbol IDD (OPH) IDD (OPL) IDD (STOP) Applic Test -able Pin Circuit Test Condition VDD = 3.0 V fCR = 400 kHz VDD = 3.0 V fXT = 32.768 kHz VDD = 3.0 V fXT = 32.768 kHz Min Typ. 100 2.5 1.0 Max 200 4.0 2.0 Unit A A A Test (Note) Diagram 3.1 3.1 3.1 2 3 4
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DC Characteristics (Pin capacity)
Characteristics Output current "H" Output current "L" Output current "H" Output current "L" Output current "H" Output current "L" Output current "H" Output current "L" Output current "H" Output current "L" Input current "H" Input current "L" Input current "H" Input current "L" Symbol IOH1 IOL1 IOH2 IOL2 IOH3 IOL3 IOH4 IOL4 IOH5 IOL5 IIH1 IIL1 IIH2 IIL2
(Unless otherwise specified, VSS = 0 V, VDD1 = 1.5 V, VDD2 = 3.0 V, VDD3 = 4.5 V, Ta = 25C)
Applicable Pin OUT, IO OUT, IO BZ/DC1 BZ/DC1 SEG, COM SEG, COM SEG, COM SEG, COM SEG, COM SEG, COM AC AC TEST1, TEST2 IN1, IN2 TEST1, TEST2 IN1, IN2 Test Circuit Test Condition VDD2 = 2.5 V VOH1 = 2.0 V VDD2 = 2.5 V VOL1 = 0.5 V VDD2 = 2.5 V VOH2 = 2.0 V VDD2 = 2.5 V VOL2 = 0.5 V For VSS - VDD3 VOH3 = 4.0 V For VSS - VDD3 VOL3 = 0.5 V For VSS - VDD1 VOH4 = 1.0 V For VSS - VDD1 VOL4 = 2.0 V For VSS - VDD2 VOH5 = 2.5 V For VSS - VDD2 VOL5 = 3.5 V VIH1 = 3.0 V VIL1 = 0 V VIH2 = 3.0 V VIL2 = 0 V Min 10 250 80 80 80 30 -1.0 30 -1.0 Typ. 50 50 Max -250 90 -250 -80 -80 -80 75 1.0 75 1.0 Unit A A A A A A A A A A A A A A Test (Note) Diagram 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2
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Note1: The voltage range where the oscillation and step-up voltage are held and the internal circuits operate correctly. Note2: The current consumed in High-Speed mode after all clear. Note3: The current consumed in Low-Speed mode set by the [FXT] instruction after all clear. Note4: The current consumed in OFF mode set by the [STOP] instruction after all clear. Note5: The value of the VSS2 voltage when a stepped voltage is applied to VSS2 and less than 10 seconds is required until a normal waveform is output to 1 output. Note6: CG is calculated by the following equation. Note that T0 = 1000 ms. CG = T (CG = 20 pF) - T (CG = 5 pF) 6 x 10 [ppm] T0
Note7: VDD2 is calculated by the following equation. VDD2 = T (VDD2 = 3.6 V) - T (VDD2 = 2.4 V) 6 x 10 [ppm] T0
Note8: When the mean value t of the periodic anomaly of a 100% sample and the typical anomaly, = (ti - t )2 / (n - 1) IC = 3 Note9: This is a guaranteed design value. The characteristics are checked by an initial sample.
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Test circuits
100 k
XOUT X'tal XIN
FAI2 FAI3 VSS VDD2 VDD1 VDD3 VDDC C1 C2 C3 FAI4 C1~C5 = 0.1 F X'tal Rs < 30 k = C5
CG 15 pF A
Figure 3.1
Measurement of Current Dissipation and Osicillation Frequency
100 k
XOUT X' tal XIN
RIN
ROUT Test Pin
VSS CG 15 pF
VDD1 VDD2 VDD3
A VIH, VIL VOH, VOL
Figure 3.2
Measurement of Input/Output Current
C4
RIN
ROUT
FAI1
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100 k
XOUT X'tal XIN
FAI2 FAI3 VSS VDD2 VDD1 VDD3 VDDC C1 C2 C3 FAI4 C1~C5 = 0.1 F X'tal CI < 30 k = C5
CG 15 pF
Figure 3.3
Measurement of VSTA and VHOLD
100 k
RIN XIN
ROUT
VSS PG
VDD1 VDD2 VDD3 A A A During testing, stop the PG at the GND level.
Figure 3.4
VDD1, VDD2 and VDD3 Leakage Currents
C4
RIN
ROUT
FAI1
Monitor
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100 k
XOUT X'tal XIN
FAI2 FAI3 VSS VDDC C3 VDD2 VDD1 C1 VDCO1 RL V VDD3 FAI4 C2 VUCO3 V C1~C5 = 0.1 F X'tal RS < 30 k = RL = 5 M The input impedance of the voltmeter must be at least 1,000 M C5
CG 15 pF
Figure 3.5
Measurement of VDCO, VUCO
100 k
XOUT X'tal XIN
RIN
RL
ROUT Function checker
VSS CG 15 pF
VDD1
VDD2
VDD3
Figure 3.6
Measurement of VDD1, VDD2 and VDD3 Operating Voltage Ranges
C4
RIN
ROUT
FAI1
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4. Application Circuit
Segment Common LCD
X'tal 32.768 kHz XI 100 k RIN XO
SEG1~SEG20
COM1~COM8 S1 IN21 S2 IN22 S3 IN13
ROUT 0.1 F FAI1 FAI2 FAI3 FAI4 AC BZ JTMP0360-002S IN14
S4
0.1 F
VDDC 0.1 F
VDD1 0.1 F
VDD3 0.1 F
VSS
VDD2
3.0 V
0.1 F
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5. Handling precautions
Described below are precautions for handling the device.
5.1
Reset by AC pin
When the power supply voltage is within the operating voltage and the crystal oscillator is operating, holding the AC pin at High for 2 ms or longer initializes the internal LSI (Figure 5.1). When the AC pin level goes to Low, reset is released, starting execution of the program. The AC pin is internally pulled down. A switch can configure a simple reset circuit. Note that the AC pin incorporates a noise canceller; thus, to assure reset, the AC pin must be held High for at least 2 ms (Figure 5.2). When the crystal oscillator is not operating normally, for example, at power on, the noise canceller does not operate. As a result, the level is not read from the AC pin. While the AC pin is held High, backup is performed to start operation of the crystal oscillator. The AC pin must be held High for 3 seconds until the crystal oscillator operates normally (Figures 5.3 and 5.4). If oscillation does not start after the above operation, an OFF instruction may be executed. In such a case, inputting High to one of the IN11 to IN14 pins while holding the AC pin at High releases the OFF instruction and starts oscillation. Note1: At power on or power cutoff, operation of the internal IC is unstable. An all-clear is required. Note2: To check that the all-clear is complete, confirm that the IC is in initial state, for example, by checking the LCD display. Note3: During backup, the power supply voltage (VDD2) is directly applied to the crystal oscillator. Thus, current dissipation (60 (A typ.) during backup increases more than usual.
5.2
Reset by simultaneous high input to SW pins (IN21, 22, 13, 14)
Simultaneously inputting High to the SW (IN21, 22, 13, 14) pins for at least two seconds performs a reset. However, because a noise canceller is incorporated to prevent erroneous resets, resets are valid when the crystal oscillator is operating normally (Figures 5.5 and 5.6). Backup is performed while a reset signal input to the SW pins via the noise canceller resets the internal system. The power supply voltage (VDD2) is directly applied to the oscillator. Thus, current dissipation (60 (A typ.) during backup increases more than usual (Figure 5.4). Backup is released approximately two seconds after a reset by the SW pins is released. The current value returns to normal.
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The all-clear timing by AC pin and all-clear circuit are shown below.
At least 2 ms are required here to assure reset. 3V AC 0V
1 kHz
Q1
ACR
Reset
Figure 5.1
All-Clear Timing Chart
Noise canceller
1 kHz
D
Q1 SR
D
Q2 SR
ACR
P* R
P* R
1 K AC
30 pF
*: P synchronizes with the rising edge. min: 35.3 k
Figure 5.2
All-Clear Circuit
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Below is a timing chart for backup.
AC pin
3V 0V
Internal reset signal ACR Counter block reset Internal reset signal ACR2 Crystal oscillator starts oscillation (3 s) AC pin level reading (2 ms) CPU block reset 8 ms Internal system reset release and program started
Backup VDDC* 3V 1.5 V 2s
*: Oscillator power supply monitor terminal
Figure 5.3
Backup Timing Chart
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Below is a circuit diagram for the backup circuit.
Buzzer
S S
D P 1 Hz
Q
D P
Q
1.5/3.0 V switching circuit
Crystal oscillator
Noise canceller
1 Hz IN21 BC *1 *1 N*2 Q R
D
Q SR
P*2 R
SWACR
IN22
IN13
KEYRESET
IN14
*2: N synchronizes with the falling edge. P synchronizes with the rising edge. Noise canceller
*1: Anti-chattering circuit
1 kHz
D
Q1 SR
D
Q2 SR
ACR
P*3 R
P*3 R
1 k AC
30 pF
*3: P synchronizes with the rising edge. min: 35.3 k
Figure 5.4
Backup Circuit
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Below are a timing chart for the all-clear and a circuit diagram for the all-clear circuit using simultaneous pressing of the switches.
At least 2 ms are required here to assure reset.
KEYRESET
2 Hz
1 Hz
BCR Q
SR Q
SWACR
Figure 5.5
SW All-Clear Timing Chart
Noise canceller
1 Hz IN21 BC *1 N* R
Q
D
Q SR SWACR
P*
R
IN22
*1
IN13
KEYRESET *: N synchronizes with a falling edge. P synchronizes with a rising edge.
IN14
*1: Anti-chattering circuit
Figure 5.6
SW All-Clear Circuit
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