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10-pin Single PLL PMB 2341 Version 1.0 Specification February 2000
DS 1
Revision History: Current Version: 02.2000 Previous Version:Data Sheet Page (in previous Version) 4-6 Page (in current Version) 4-6 Subjects (major changes since last revision)
Programming of multifunctional output pin (MFO) is changed, i.e. MFO (open drain) is driven to ground for MFO bit equal to 1.
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PMB 2341 preliminary
Confidential Productinfo
Productinfo
General Description
The PMB 2341 is a monolithic, low power, Package high performance phase-locked-loop (PLL) frequency synthesizer. It is primarily designed to be used for very stable low noise LO signals in mobile communication systems such as GSM, PCN (GSM 1800), PCS and PDC. The wide range of divider rations also allows application in modern analog systems.
0.2 0.5 3.0
3.0
5.0
Max. high:1.2 Dimens. in mm
Programmable power down modes High input sensitivity and high input frequencies up to 2.5 GHz Reference frequencies up to 100 MHz. Programmable dual modulus prescaler divide ratio (1:64/65 or 1:32/33). Dividing ratios: A, N, R counter: 0 to 63, 3 to 4095, 3 to 4095, respectively
Ordering Information
Type PMB 2341 Ordering Code Package Mini-TSSOP-10
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Product Info

Features
B6HFC BiCMOS technology 2.7 to 4.5 V operation Low operating power consumption Fast phase detector with switchable polarity charge pump output with programmable current and without dead zone Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs One multi-functional port Very small Mini-TSSOP-10 Package
Specification, February 2000
1
Table of Contents
1 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Stand-by / power down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Programing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Register, Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Special programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Typical Power-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Typical Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 RF Input Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PMB 2341 preliminary
Confidential Product Description
2.1 Overview
The PMB 2341 is a monolithic, low power, high performance phase-locked-loop (PLL) frequency synthesizer. It is primarily designed to be used for very stable low noise LO signals in mobile communication systems such as GSM, PCN (GSM 1800), PCS and PDC. The wide range of divider rations also allows application in modern analog systems.
2.2 Features
B6HFC BiCMOS technology 2.7 to 4.5 V operation Low operating power consumption Programmable power down modes High input sensitivity and high input frequencies up to 2.5 GHz Reference frequencies up to 100 MHz. Programmable dual modulus prescaler divide ratio (1:64/65 or 1:32/33). Dividing ratios: A, N, R counter: 0 to 63, 3 to 4095, 3 to 4095, respectively Fast phase detector with switchable polarity charge pump output with programmable current and without dead zone Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs One multi-functional port Very small Mini-TSSOP-10 Package
2.3 Package outline
1.1 max. 0.15 max.
H
A 0.220.05 0.08
M
0.1 A ABC
0.09
0.5
0.42 +0.15 -0.1 4.9 0.25
M
6 max.
ABC
3 0.1
C
30.1 Index Marking
B
Figure 2-1
Mini-TSSOP-10
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Specification, February 2000
+0.08 0.125 -0.05
0.85 0.1

3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Stand-by / power down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
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3.1 Pin Configuration
VDD
1
10
RI
CP
2
9
EN
GND
3
PM B 2341
8
DA
LO
4
7
CLK
VCC
5
6
M FO
Pin_config.wmf
Figure 3-1
IC Pin Configuration
3.2 Pin Definition and Functions
Pin No. 1 2 3 4 5 Symbol VDD CP GND LO VCC Function Digital CMOS supply voltage. Note: VDD and VCC must be equal! PLL charge pump output Analog / bipolar ground, Charge pump ground and Digital CMOS ground (VSS) Used for bipolar prescaler, charge pump and Digital CMOS RF frequency input AC coupling is required. Analog / bipolar supply and Charge pump supply Used for bipolar prescaler, input buffer and chargepump Note: VDD and VCC must be equal! Multi-functional output (Open-drain) 3-Wire bus input: Clock Clock input of the serial control interface with CMOS Schmitt-Trigger input stage 3-Wire bus input: Data Data input of the serial control interface withCMOS Schmitt-Trigger input stage.The serial data are read into the addressed internal shift register with the positive edge of CLK 3-Wire bus input: Enable Enable input of serial control interface with CMOS Schmitt-Trigger input stage. When EN=H the input signals CLK and DA are disabled. When EN=L the serial control interface is enabled. The received data bits are transmitted into the addressed registers with the positive edge of EN Reference frequency input Input with highly sensitive preamplifier. With small input signals AC coupling must be set up, whereas DC coupling can be used for large input signals
6 7 8
MFO CLK DA
9
EN
10
RI
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3.3 Block diagram
1 PLL VDD
1 2 B it R -C o u n te r D a ta & S h a d o w R e g iste r
R I_ sb y
10 RI
VCC
2 CP
GND P h ase D ete cto r M FO sync load
9 EN
buf_en 6 4 /6 5 3 2 /3 3 M od pll_en
3 GND
1 2 B it N -C o u n te r 6 B it A -C o u n te r D a ta & S h a d o w R e g iste r M o d u lu s C o n tro l
8
S e ria l C o n tro l L o g ic
DA
Presc_sby
p ro g m o d e
N T_ sb y p ll_ stb m o d
4 LO
p re sc
C o n tro l re g iste r
7 CLK
cp p w 0 ,cp p w 1 pdpol
5 VCC
p ll_ e n b u f_ e n
e n a b le lo g ic
P re sc_ sb y R I_ sb y N T_ sb y M FO
6 M FO
Block_diag.wmf
Figure 3-2
Main block diagram
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3.4 Functional Blocks
3.4.1
General information
The PMB2341 consists of a dual band single PLL. The device is designed to work in mobile communication systems and can handle VCO input frequencies up to 2.5 GHz.
3.4.2
PLL
The PLL in the PMB 2341 consists of a high frequency bipolar configurable 32/33 or 64/ 65 dual modulus prescaler, an A- and a N-counter with dual modulus control logic, a reference- (R-) counter, and a phase detector with charge pump output with programmable output current drive capability. The counter and mode settings of the synthesizer are programmed via a serial 3-wire interface. The reference frequency is applied at the RI-input and divided by the PLL's R-counter. Its maximum value is specified to be 100 MHz. The VCO's RF input signal is divided by the bipolar prescaler with a programmable 32/33 or 64/65 divider ratio and the following programmable A/N-counters. For a wide range of divider ratios, both N and R counter can be programmed from 3 to 4095 . The phase and frequency detectors with the charge pumps have a linear operating range without dead zone for very small phase deviations. The operating modes allow the selection of 4 different charge pump output currents, polarity setting of the phase detector, 2 standby modes and the conrol of the multifunctional output port MFO.
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PMB 2341 preliminary
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RI fR (RI:R)
LO fV (LO:M)
CP
P-Channel Tri-State.
N-Channel positive Polarity CP P-Channel Tri-State.
N-Channel negative Polarity
Frequency fV < fR fV lagging
Frequency fV > fR fV leading
Frequency fV = fR lock state
Figure 3-3
Frequency detector output waveforms
Frequency setting / divider ratio calculation: The frequency of an external VCO controlled by the PMB 2341 is given below: f RI M f VCO = [ ( P N ) + A ] ------ = ---- f RI R R with . fVCO: fRI: N: A: P: R: M=P*N+A: Note: frequency of the external VCO reference frequency divide ratio of the N-counter divide ratio of the A-swallow counter divide ratio of the prescaler (33 in case of 32/33 prescaler selected) divide ratio of the R-counter total divide ratio
for continuous frequency steps following condition is necessary [P N + A] P (P - 1) Further restrictions have to be fullfilled: A

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3.4.3
Stand-by / power down conditions
The PMB 2341 device has 2 different stand-by modes to reduce the power consumption. The standby modes allow separate power up and down modes for the PLL itself and for the RI input amplifier circuitry. The selection of a desired power-down mode is done by setting two bits `standby1' and 'standby2' located in the A/N-counter control word (see table 4-1: A/N counter data format). This enables a fast wake-up of the device and programming of a VCO-frequency with only one bus cycle! The encoding of the defined modes can be obtained from table 4-5: standby mode selection bits.
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Specification, February 2000
4
Applications
Contents of this Chapter 4.1 4.2 4.3 Programing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Register, Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Special programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
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4.1 Programing
General information:
Programming of the IC is done via the 3 wire serial data interface consisting of a clock line, data line and an enable line. Data are shifted into the device with every rising CLK edge and are overtaken into internal registers with the rising edge of EN according to the schematic timing diagram shown in Figure 4-1.
CLK DAT EN latch data into internal register
Figure 4-1
Schematic bus signal timing
Depending on the desired functional units to be programmed, several serial data formats exist. A common fact is that all multibit values are ordered in little endian notation in the bitstream meaning their MSB is sent first. Every bus cycle starts with the dedicated data bits followed by at least 1 register address bit and is terminated with two device address bits. In chapter 4.2 Register, Data format the available data formats are explained. The short control data format allows a fast PD-current change. The long control data format allows the programming of 4 different PD-output current modes for the PLL, polarity setting of the PD-output signals, 2 standby modes, test mode select and the prescaler divide ratio. The A/N-counter data format contains the A/N-counter values, the multifunctional output bit and standby mode switch bits. The R-counter data format contains the R-counter values and PLL programming mode switch bit. The PLL is programmed in an asynchronous mode: The serial data is written directly to the data registers of the addressed counter with the enable pulse. As each counter is loading the new starting value after it is decremented to zero", the counters changes therefore their counter values asynchronously to the others.
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4.2 Register, Data format
Note
MSB of all serial data is shifted first!
Table 4-1 A/N counter data format
PLL
Bit-Nr
LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MSB
Bit 0 1 1
caddr0 caddr1 raddr0 n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 standby1 standby2 a0 a1 a2 a3 a4 a5 MFO
Function
chip address A/N register address N-counter
PLL on/off Ri input amp on/off A-counter
multifunc. output port 2 (MFO)
Table 4-2
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Table 4-2 R counter data format
PLL
Bit-Nr LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSB 0 caddr0 1 0 1 caddr1 raddr0 raddr1 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 R-counter R register address chip address Bit Function
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Table 4-3 Control data formats Long control data format PLL Bit-Nr
LSB 0 1 2 3 4 5 6 7 8 9 10
Short control data format PLL Value 0 Bit caddr0 1 caddr1 raddr0 raddr1 raddr2 cpcurr2 cpcurr1 cpcurrtst charge pump current setting charge pump current test mode short control word address Function chip address
Value 0
Bit caddr0
Function chip address
1 0 0 1
caddr1 raddr0 raddr1 raddr2 cpcurr2 cpcurr1 cpcurrtst presc charge pump current setting charge pump current test mode prescaler division ratio required for correct operation phase detector polarity required for correct operation test mode selection long control word address
0 0 0
0
n.a. pdpol
11 12 13 14 15 16 17 18 19
0 1
n.a. n.a. mode2 mode1 not used not used not used not used not used
Table 4-4 Chip address bit Bits
caddr1 1 caddr0
Description 0
This chip address has to be sent to access the PMB2341
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Table 4-5 Standy mode selection bits Bits
standby 1 1 1 0 standby 2
Description 1 0 1
Remarks
0
0
ALLRUN: PLL is powered on. not used: Enabling or disabling of certain identical to ALLrun. bipolar modules is done by turning AMPRUN: on or off its bias currents. PLL is powered off, only RI input preamplifier is powered on. ALLOPP: Both PLL and RI input preamplifier are powered off.
Table 4-6 Port switching bits Bit
MFO
VALUE 1 0
Description
Multifunctional output MFO is driven to ground (VSS) Multifunctional output MFO is driven to VDD
Table 4-7 Charge pump current programming bits cpcurr 1
0 1 0 1 0 1 0 1
Bits cpcurr 2
0 0 1 1 0 0 1 1
cpcurrtst
0 0 0 0 1 1 1 1
CP Current [mA] I
1.2 mA 2.0 mA 2.8 mA 4.0 mA 1.2 mA pump 1 1.2 mA pump 2 0.8 mA pump 1 0.8 mA pump 2
Remark
Table 4-8 Prescaler mode select bit Bit
presc
Value 0 1
Description
32/33 64/65
Table 4-9 Phase detector polarity select bit Bit
pdpol
Value 0 1
Description
negative polarity positive polarity
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Table 4-10 Test mode installation bits Control Bits mode 1 mode 2
1 1
Mode
OPERATE: Normal operation of PLL and RI Buffer in installed mode. MFO pin has programmed level. not used: identical to OPERATE Testmode RCNTOUT: Charge pump is turned off. R-counter output at multifunctional MFO pin. Testmode NCNTOUT: Charge pump is turned off. N-counter output at multifunctional MFOMFO pin.
0 1
1 0
0
0
4.3 Special programming sequences
Fast wake-up programming: When the circuit is connected to the supply voltage all registers are undefined. Due to the fact that each counter is loading its new start value after it is decremented to zero", the start-up time of the counters with the programmed values is too long for some applications. If the device has previously been set to ALLOFF- or AMPRUN-mode (see Table 5) afterwards is turned to operating mode ALLRUN, the counters are starting immediatly with the preprogrammed start values. Therefore for fast startup after standby the following data transfer sequence is recommended:
Table 4-11 Fast Wake Up Data Transfer Sequence Step
1 2 3 4 5 Serial Data Transfer Sequence Long Control Word: 'OPERATE' Set A-/N-Counter: AMPRUN mode Set R-Counter Set A-/N-Counter, AMPRUN mode Set A-/N-Counter, ALLRUN mode
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5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Typical Power-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Typical Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 RF Input Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
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5.1 Absolute Maximum Range
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, due to permanent damage to the device. Table 5-1 Absolute Maximum Ratings # Parameter Symbol min
1 2 3 4 5 6 7 8 9 10 CMOS Supply Voltage Bipolar Supply Voltage Difference between VCC and VDD levels Applied voltage at pins CLK, DA, EN, RI,CP Input voltage (LO) Output current open-drain-stage (MFO) Total power dissipation Ambient temperature Storage temperature ESD integrity VInCMOS_lim VI_Bip_lim IO_OD Ptot_lim TA Tstg VESD -40 -50 t.b.d. -0.3 -0.3 VDD_lim VCC_lim -0.3 -0.3
Limit Values max
5 5 |0.2| VDD + 0.3 Vcc 0.8V 1 t.b.d. 85 125 t.b.d.
Units
Remarks
V V V V V mA mW C C V
with respect to related ground. VCC and VDD are intended to have the same level
5.2 Operational Range
Within the operational range the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed. Table 5-2 Operating Ratings # Parameter Symbol min
1 2 3 4 5 CMOS Supply Voltage Bipolar Supply Voltage Input VCO frequency at LO Input VCO frequency at LO Input frequency at RI VDD VCC LO LO fRI | IO_PP | | IO_CP | VO_CP
Limit Values max 4.5 4.5
2500
Units
L
Remarks
2.7 2.7 250 250 1
V V MHz MHz MHz mA mA V C
VCC and VDD are intended to have the same level Prescaler set to 32/33 mode Prescaler set to 64/65mode
2500 100 0.2 4
6 7 8 9
Output current open-drainstage (MFO) CP-output current of PLL CP-output voltages Ambient temperature
0.5 -40
VCC0.5 85
TA
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5.3 Typical Power-On Time
Time required to turn PLL and/or LO-buffer-chain frominstalled standby-mode to mode ALLRUN. Time is measured from time point when the ENable-signal is sent on 3-wire bus after programming the apropriate data bits.
Table 5-3
Previously installed standby mode (see Table 5) AMPRUN ALLOFF Turn-ONtime Units Remarks see Note 1)
t.b.d 1
s s
NOTE 1: Only the turn-on time from PLL is measured, not the required lock-in time, which strongly depends on the loopfilter, etc.
5.4 Typical Supply current
Table 5-4
Standby mode (see Table 5) CMOSSupply IDD Bipolar Supply ICC Units Test item Test condition
ALLRUN ALLOFF
1.4 0
5.5 0
mA mA
1.1 1.2 see Note 1)
Note 1) : Room temperature, All supplies set to 3.2V, TA = 27 C, fRI = 13MHz, fLO = 1.2GHz, internal fref = 200KHz, PLL locked in mode ALLRUN, charge pump output current set to 4mA. No bus programming activities. Values may vary within 10%.
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5.5 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Supply voltage VCC , VDD, , VCP = 2.7V...4.5V, Ambient temperature Tamb = -40C to 85C except especially mentioned other values Table 5-5 AC/DC Characteristics # Symbol min Limit Values typ max VDD =3.5V VDD = 3.5V VDD = 2.7V *) guaranteed by design 2.4 2.5 Units Test Item Test Conditions
Input Signals (Schmitt-Trigger) DA, CLK, EN when configured as input 1 2 3 4 5 6 H-input voltage H-input voltage L-input voltage Input capacity DC High-input current DC Low-input current VI_ST_H VI_ST_H VI_ST_L CI_ST IST_H IST_L 0 0 1.5V 0.5 VDD VDD VDD 0.5V 5 5 5 V V V pF A A 2.1 2.2 2.3
Output Signals MFO (open drain) 7 8 L-output voltage H-output current VO_OD_L IO_OD_H 0.01 0 0.1V 5 V A 3.1 3.2 IO_OD_L =0.2m
Charge Pump Output Current IO_CP 9 10 11 12 13 14 "1.2 mA" "2 mA" "2.8 mA" "4 mA" "4 mA" "Leakage Current" | IO_CP | | IO_CP | | IO_CP | | IO_CP | | IO_CP | | IO_CP | -20% -20% -20% -20% -20% 1.2 2.0 2.8 4.0 4.6 0.1 +20% +20% +20% +20% +20% 1*) mA mA mA mA mA nA 4.1 4.2 4.3 4.4 4.5 4.6 VCP = 4.5V *) guaranteed by design VCP = 3.2V, VO_CP = VCP/2
Output Tolerance IO_CP with variing voltage at pin CP 15 IO_CP / IO_CP -10% 5.1 VO_CP = 0.5...VCP-0.5V
VDD = 2.7V, Note 1)
Crystal Oscillator Input Signal RI 16 Input voltage at Ri
VI_RI
100
mVrms
6.1
Input at LO; VCC=3.6 V 17 Input voltage at LO
VI_LO
-20 -9
+4 +4
dBm dBm
7.1 7.2
500 - 2500 MHz 250 - 500 MHz
Note 1: fRI=4..30 MHz, VDD=3.6 V measured with PLL in mode RCNTOUT (see Table 4-10) at pin MFO.
Wireless Components
5-4
Specification, February 2000
PMB 2341 preliminary
Confidential Reference
5.6 Serial Control Data Format Timing
tWHCL VIH CLK VIL
tR
tF
tDS
VIH
DA
VIL
tCLE
tECL
VIH
EN
VIL
tWHEN VIH PORT
VIL
tDEP
Figure 5-1
Serial Control Data Format Timing
Table 5-6 Symbol Limit Values min Parameter Clock frequency H-pulsewidth (CLK) Data setup Setup time Clock-Enable Setup time Enable-Clock H-pulsewidth (Enable) Rise, fall time Propagation delay time EN-PORT CLK tWHCL tDS tCLE tECL tWHEN tR , tR tDEP 30 20 20 20 60 10 1 15 MHz ns ns ns ns ns s s max Units
Wireless Components
5-5
Specification, February 2000
PMB 2341 preliminary
Confidential Reference
5.7 RF Input Sensitivity
5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45
Input Power [dBm]
50
Figure 5-2
RF Input Sensitivity
Measured Prescler RF Sensitivity (Vcc=2.7V, 64/65 divider)
300
550
800
Input Frequency [MHz] BASELINE TOPLINE
1050
1300
1550
1800
2050
2300
2550
2800
3050
3300
Wireless Components
5-6
Specification, February 2000

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