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HD66773R
262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels
REJxxxxxxx-xxxxZ Rev.1.20 Jun.21.2003
Block Diagram .................................................................................................... 6 PAD Arrangement .............................................................................................. 7 PAD Coordinate.................................................................................................. 8 Pin Function ........................................................................................................ 10 Block Function.................................................................................................... 15
1. 2. 3. 4. 5. 7. 8. 9. System Interface ............................................................................................................... 15 Bit Operation .................................................................................................................... 15 Address Counter (AC) ...................................................................................................... 16 Hardware-dither circuit..................................................................................................... 16 Graphics RAM (GRAM) .................................................................................................. 16 LCD drive power supply................................................................................................... 16 Oscillation Circuit (OSC) ................................................................................................. 16 LCD Driver Circuit........................................................................................................... 16
GRAM Address MAP......................................................................................... 17
Gram Address and display position on the panel (SS = "0")....................................................... 17 The relationship between GRAM data and display data (SS ="0")............................................. 18 Gram Address and display position on the panel (SS = "1", BGR = "1")................................... 20 The relationship between GRAM data and display data (SS ="1")............................................. 21
Instructions ......................................................................................................... 23
Outline ......................................................................................................................................... 23 Instructions .................................................................................................................................. 25 Index .......................................................................................................................................... 25 Status Read .................................................................................................................................. 25 Start Oscillation (R00h)............................................................................................................... 25 Driver Output Control (R01h) ..................................................................................................... 26 LCD Driving Waveform Control (R02h) .................................................................................... 28 Power Control 1 (R03h) Power Control 2 (R04h)....................................................................... 29 Power Control 3 (R0Ch) Power Control 4 (R0Dh) Power Control 5 (R0Eh) ............................. 31 Entry Mode (R05h) Compare Register (R06h)............................................................................ 36 Display Control 1 (R07h) ............................................................................................................ 38 Frame Cycle Control (R0Bh) ...................................................................................................... 40
Rev.1.10, Jun.21.2003, page 1 of 133
HD66773R Gate Scan Position (R0Fh) .......................................................................................................... 43 Vertical Scroll Control (R11h) .................................................................................................... 44 1st-Screen Drive Position (R14h) 2nd-Screen Drive Position (R15h) ........................................ 44 Horizontal RAM Address Position (R16h) Vertical RAM Address Position (R17h).................. 45 RAM Write Data Mask (R20h) ................................................................................................... 46 RAM Address Set (R21h) ........................................................................................................... 46 Write Data to GRAM (R22h) ...................................................................................................... 47 GRAM data and liquid crystal output level ................................................................................. 49 Read Data from GRAM (R22h) .................................................................................................. 50 GRAM read sequence.................................................................................................................. 51
Instruction List .................................................................................................... 53 Reset Function .................................................................................................... 54
Initial state of output pin.............................................................................................................. 55
System Interface.................................................................................................. 56
18-bit interface ............................................................................................................................ 57 16-bit interface ............................................................................................................................ 58 9-bit interface .............................................................................................................................. 59 Data transmission synchronization in 9-bit bus interface mode .................................................. 60 8-bit interface .............................................................................................................................. 61 Data transmission synchronization in 8-bit bus interface mode .................................................. 62 Serial Peripheral interface (SPI) .................................................................................................. 63
High-Speed Burst RAM Write Function ............................................................ 67
Conditions on using high-speed RAM write mode ..................................................................... 69 High-Speed RAM Write with Window Address ......................................................................... 70
Window Address Function ................................................................................. 72 Graphics Operation Function.............................................................................. 73
Write-data Mask Function ........................................................................................................... 74 Graphics Operation Processing ................................................................................................... 75
Scan Mode Setting .............................................................................................. 83 -Correction Function ......................................................................................... 84
Configuration of Grayscale Amplifier......................................................................................... 85 -Correction Register................................................................................................................... 87 Ladder resistors and 8-to-1 selector............................................................................................. 88 Variable resistor .......................................................................................................................... 88 Relationship between RAM data and output level ...................................................................... 94
8-color Display Mode ......................................................................................... 95 Instruction Setting Flow...................................................................................... 97
Rev.1.10, Jun.21.2003, page 2 of 133
HD66773R
Power Supply Setting Flow ................................................................................ 99 Oscillation Circuit............................................................................................... 100 n-raster-row Inversion AC Drive ........................................................................ 101 Interlaced Drive .................................................................................................. 102 AC Timing ......................................................................................................... 104 Frame-Frequency Adjustment Function ............................................................. 105
Relationship between Liquid Crystal Drive Duty and Frame Frequency .................................... 105
Screen -split Drive Function ............................................................................... 106
Conditions on Setting the 1st/2nd Screen Drive Position Register.............................................. 107
Internal Configuration of Power Generation Circuit .......................................... 109 Specification of External Elements Connected to HD66773R ........................... 111 Pattern Diagram for Voltage Setting................................................................... 112 Absolute Maximum Ratings ............................................................................... 113 Electric Characteristics ....................................................................................... 114
DC Characteristics....................................................................................................................... 114 AC Characteristics....................................................................................................................... 115 68system Bus Interface Timing Characteristics .......................................................................... 116 80-system Bus Interface Timing Characteristics ......................................................................... 118 Serial Peripheral Interface timing characteristics ........................................................................ 120 Reset Timing Characteristics....................................................................................................... 120 Notes to Electrical Characteristics............................................................................................... 121 Referential data............................................................................................................................ 123 Timing characteristics diagram ................................................................................................... 128
Rev.1.10, Jun.21.2003, page 3 of 133
HD66773R
Description
The HD66773R is a controller driver LSI compliant to 132RGB x 176-dot graphics display on TFT LCD panel in 262,144 colors. The HD66773R's bit-operation functions, 18-bit high-speed bus interface, and high-speed RAM-write function enable efficient data transfer and high-speed update of graphics RAM data. The HD66773R operates with low voltage up to 2.2V for power supply. The HD66773R incorporates TFT gate-drive and source-drive circuits, a step-up circuit to generate LCD drive voltage, and power supply circuits such as breeder resistor and voltage follower for LCD drive, which enable a configuration of LCD module only with external elements such as capacitors and resistors. The HD66773R supports 8-colordisplay and standby modes, which enable precise power control by software. These features make this LSI the best solution for medium or small sized portable products such as digital cellular phones, bi-directional pagers, or small PDA, which support WWW browser, where long life battery is major concern.
Rev.1.10, Jun.21.2003, page 4 of 133
HD66773R
Features
* * * * * Single chip controller/driver for 262,144-color, 132RGB x 176-dot graphics display on TFT LCD 18-/16-/9-/8-bit high-speed bus interfaces and a Serial Peripheral Interface (SPI) High-speed burst-RAM write function Window address function enabling data write in a rectangular RAM-address area Internal bit-operation for graphics Bit-unit write-data mask function Pixel-unit logical operation / conditional rewrite function Abundant color-display control function: 262,144-color display (max.) with gamma adjustment function Line-unit vertical bi-directional scrolling display function Architecture with low power consumption Low-voltage operation: Vcc = 2.2 ~ 3.3 V Internal reference voltage power supply: Vci = 2.5 ~ 3.3 V Standby mode and other power-save functions: Partial LCD drive: 2-screen display at arbitrary two positions Internal power supply circuit Internal equalizing function Compliant to Cst/Cadd structures Internal power supply circuits Step-up circuit: 5 ~ 9-time scale, polarity inversion Power supply for TFT common electrode: Compliant to Vcom n-raster-row AC drive AC drive: Vgoff n-raster-row AC drive with Cadd structure Vcom (Vgoff) amplitude adjustment: 22-scale internal electronic volume adjustment Output power-supply voltage Voltages for power supply for Vcom amplitude = 6V (max.), TFT common electrode: VcomH-GND = VREG1OUT (max.), VcomL-GND = 1.0V ~ -Vci+0.5V (max.) Internal RAM capacity: 46,464 bytes LCD drive circuit with 396-output source signal and 176-output gate signal n-raster-row inversion drive: polarity inversion by arbitrary number of lines. Internal oscillation and hardware reset Changeable source and gate shift directions Compliant to COG with single chip, incorporating gates arranged on both sides.
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Rev.1.10, Jun.21.2003, page 5 of 133
HD66773R
Block Diagram
Vcc GND Index Register (IR) Control Register (CR)
Source driver Latch circuit M A/C circuit
RVcc
Latch circuit Latch circuit
IM3-1, IM0/ID CS* RS E/WR*/SCL RW/RD* DB0/SDI, DB1/SD0, to DB17 RESET TEST1 TEST2 TS7-0 MTEST1 MTEST2 TESTV1 18
7 System Interface 18 bit 16 bit 9 bit 8 bit Serial peripheral
16
Address Counter (AC)
S1 to S396
18 Bit 18 Dithering Operation Circuit 16 16 Read data latch Write data latch 64 16 Gamma adjusting circuit 16 V0-31
(SPI)
Graphic RAM (GRAM) 46,464 bytes
Grayscale voltage generator
VGS VTESTS V0P V0N V31P V31N VM0NI
OSC1 OSC2
Scan data generating circuit
CPG
Timing generator
Gate driver circuit
CGND AGND DCTEST
G1 to G176
LCD drive level generating circuit
Rev.1.10, Jun.21.2003, page 6 of 133
VREG1OUT VREG2OUT Vci1 C11+ C12+ C11- C12DDVDH Vci2 C21+ C23+ C21- C23VGH Vci3 C31+ C31VGL Vci4 C41+ C41VCL VgoffH VgoffL VgoffOUT Vgoff VcomR VcomH VcomL Vcom1 Vcom2 TESTA1 TESTA2 TESTA3 TESTA4
Vci
HD66773R
PAD Arrangement
GTEST1 G G3 G5 G7
No.786
No.743
G79 G81 G83 G85
No.1 DUMMY1 No.2
Vcom1 Vcom1 DUMMYR1 DUMMYR2 RESET1* DUMMY2 1.6mm DUMMY3 DUMMY4 VGH VGH Vci3 C23+ C23+ C23C23C22+ C22+ C22C22C21+ C21+ C21C21C41+ C41+ C41C41C31+ C31+ C31C31VGL VGL VGL VGL CGND CGND CGND VccDUM1 IM0/ID GNDDUM1 IM1 VccDUM2 IM2 VccDUM3 IM3 GNDDUM2 DUMMY5 DUMMY6 RESET2* GNDDUM3 TEST1 TEST2 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 GNDDUM4 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI GNDDUM5 RW/RD* E/WR*/SCL RS CS* TESTV1 GNDDUM6 MTEST1 MTEST2 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND RVcc RVcc RVcc RVcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vci Vci Vci Vci Vci Vci Vci4 OSC1 OSC2 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 DCTEST DUMMY7 DUMMY8 DUMMY9 DUMMY10 DUMMY11 DUMMY12 VGS VGS CGND CGND CGND V0P V0N VMONI VMONI V31P V31N VcomL TESTA4 TESTA1 VcomR VREG1OUT TESTA2 DUMMY13 VTESTS DUMMY14 DUMMY15 VcomH VCL VCL Vci1 Vci1 Vci1 Vci1 REGP DUMMY16 Vci2 DDVDH DDVDH Vci3 C11C11C11C11C11+ C11+ C11+ C11+ C12C12C12C12C12+ C12+ C12+ C12+ Vgoff VgoffOUT VgoffH VgoffL TESTA3 VREG2OUT DUMMY17
DUMMY18 1.6mm DUMMY19
DUMMY39
No.742
Min 38um pich 44pin
Short-circuit within the chip G87 G89 G91 G93
No.741
-Au bump size: (1) 80 mx80 m Corner dummy: No.1,No195,No.239,No.742 (2) 54 mx100 m Input side No.2 to No.194 (3) 36 mx70 m Laced liquid crystal output side: No.196 to No.238 No.240 to No.741 No.743 to No.786 -Au bump pitch: Refer to Pad Coordinate -Au bump height: 15 m(typ.) Numbers in figure 2 refer to numbers in Pad coordinate Alignment Mark (1) Assignment: 2places Coordinate (X, Y) = (10135,935)
Min 38um pich 45pin
G169 G171 G173 G175 DUMMY38 DUMMY37 DUMMY36 DUMMY35 DUMMY34 DUMMY33 DUMMY32 DUMMY31 S1 S2 S3 S4
-Chip size: 20.69mmx2.47mm -Chip thickness: 400 m(typ.) -Pad Coordinate: Pad Center -Coordinate Origin: Chip center
Min 76um pich 8pin
No.697 No.696
HD667B73
TypeCode
No.689 No.688
(2-a) Coordinate (X, Y) = (-10119, 1100)
HD667B73 Laced Top View
Min 80um pich 193pin
Y X
(2-b) Coordinate (X, Y) = (10119,1100)
(3-a) Coordinate (X, Y) = (-10029, 1100)

Min 38um pich 396pin
S393 S394 S395 S396 DUMMY30 DUMMY29 DUMMY28 DUMMY27 DUMMY26 DUMMY25 DUMMY24 GTEST2 G176 G174 G172 G170
Min 76um pich 7pin
(3-b) Coordinate (X, Y) = (10029, 1100)
No.293 No.292
No.286 No.285
Min 38um pich 46pin
G94 G92 G90 G88
RESET3* DUMMY20 DUMMY21 Vcom2 Vcom2
No.194
DUMMY22
G2 G4 G6 G8
Min 38um pich 43pin
G80 G82 G84 G86
No.240
DUMMY23
No.195 No.196 No.238
No.239
Rev.1.10, Jun.21.2003, page 7 of 133
HD66773R
PAD Coordinate
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pad name DUMMY1 Vcom1 Vcom1 DUMMYR1 DUMMYR2 RESET1* DUMMY2 DUMMY3 DUMMY4 VGH VGH Vci3 C23+ C23+ C23C23C22+ C22+ C22C22C21+ C21+ C21C21C41+ C41+ C41C41C31+ C31+ C31C31VGL VGL VGL VGL CGND CGND CGND VccDUM1 IM0/ID GNDDUM1 IM1 VccDUM2 IM2 VccDUM3 IM3 GNDDUM2 DUMMY5 DUMMY6 RESET2* GNDDUM3 TEST1 TEST2 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 GNDDUM4 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI GNDDUM5 RW/RD* E/WR*/SCL RS CS* TESTV1 GNDDUM6 MTEST1 MTEST2 AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND RVcc RVcc RVcc RVcc Vcc Vcc X -10209 -10041 -9961 -9859 -9768 -9650 -9116 -8582 -8048 -7947 -7867 -7765 -7685 -7605 -7525 -7445 -7365 -7284 -7204 -7124 -7044 -6964 -6884 -6803 -6723 -6643 -6563 -6483 -6403 -6323 -6242 -6162 -6029 -5949 -5869 -5789 -5687 -5607 -5527 -5447 -5356 -5237 -5146 -5028 -4936 -4818 -4727 -4608 -4528 -4448 -4357 -4238 -4147 -4067 -3987 -3907 -3826 -3746 -3666 -3586 -3506 -3426 -3346 -3227 -3136 -3056 -2976 -2895 -2815 -2735 -2655 -2575 -2495 -2376 -2285 -2205 -2125 -2045 -1964 -1846 -1755 -1675 -1525 -1445 -1343 -1263 -1161 -1081 -948 -868 -767 -687 -585 -505 -372 -292 -212 -131 -51 29 Y -1099 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 pad name Vcc Vcc Vcc Vcc Vcc Vcc Vci Vci Vci Vci Vci Vci Vci4 OSC1 OSC2 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 DCTEST DUMMY7 DUMMY8 DUMMY9 DUMMY10 DUMMY11 DUMMY12 VGS VGS CGND CGND CGND V0P V0N VMONI VMONI V31P V31N VcomL TESTA4 TESTA1 VcomR VREG1OUT TESTA2 DUMMY13 VTESTS DUMMY14 DUMMY15 VcomH VCL VCL Vci1 Vci1 Vci1 Vci1 REGP DUMMY16 Vci2 DDVDH DDVDH Vci3 C11C11C11C11C11+ C11+ C11+ C11+ C12C12C12C12C12+ C12+ C12+ C12+ Vgoff VgoffOUT VgoffH VgoffL TESTA3 VREG2OUT DUMMY17 DUMMY18 DUMMY19 RESET3* DUMMY20 DUMMY21 Vcom2 Vcom2 DUMMY22 G2 G4 G6 G8 G10 X 109 189 269 349 430 510 590 670 750 830 911 991 1129 1257 1337 1418 1498 1578 1658 1738 1818 1898 1979 2059 2177 2257 2337 2418 2498 2578 2685 2765 2872 2952 3032 3139 3219 3299 3380 3460 3540 3657 3737 3854 3934 4014 4094 4201 4308 4415 4495 4602 4740 4820 4959 5039 5119 5199 5343 5450 5557 5695 5776 5909 6047 6127 6207 6287 6368 6448 6528 6608 6688 6768 6848 6929 7009 7089 7169 7249 7388 7468 7601 7681 7814 7947 8048 8582 9116 9650 9768 9859 9961 10041 10209 10214 10104 10214 10104 10214 Y -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1089 -1099 -801 -763 -725 -687 -649
No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 pad name G12 G14 G16 G18 G20 G22 G24 G26 G28 G30 G32 G34 G36 G38 G40 G42 G44 G46 G48 G50 G52 G54 G56 G58 G60 G62 G64 G66 G68 G70 G72 G74 G76 G78 G80 G82 G84 G86 DUMMY23 G88 G90 G92 G94 G96 G98 G100 G102 G104 G106 G108 G110 G112 G114 G116 G118 G120 G122 G124 G126 G128 G130 G132 G134 G136 G138 G140 G142 G144 G146 G148 G150 G152 G154 G156 G158 G160 G162 G164 G166 G168 G170 G172 G174 G176 GTEST2 DUMMY24 DUMMY25 DUMMY26 DUMMY27 DUMMY28 DUMMY29 DUMMY30 S396 S395 S394 S393 S392 S391 S390 S389 X 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10104 10214 10209 9919 9881 9843 9805 9766 9728 9690 9652 9614 9576 9538 9499 9461 9423 9385 9347 9309 9270 9232 9194 9156 9118 9080 9042 9003 8965 8927 8889 8851 8813 8775 8736 8698 8660 8622 8584 8546 8507 8469 8431 8393 8355 8317 8279 8240 8164 8088 8012 7935 7859 7783 7706 7630 7554 7516 7477 7439 7401 7363 7325 7287 Y -610 -572 -534 -496 -458 -420 -382 -343 -305 -267 -229 -191 -153 -114 -76 -38 0 38 76 114 153 191 229 267 305 343 382 420 458 496 534 572 610 649 687 725 763 801 1099 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 1104 1104 1104 1104 1104 1104 1104 1104 994 1104 994 1104 994 1104 994 1104 No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 pad name S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 X 7249 7210 7172 7134 7096 7058 7020 6981 6943 6905 6867 6829 6791 6753 6714 6676 6638 6600 6562 6524 6486 6447 6409 6371 6333 6295 6257 6218 6180 6142 6104 6066 6028 5990 5951 5913 5875 5837 5799 5761 5723 5684 5646 5608 5570 5532 5494 5455 5417 5379 5341 5303 5265 5227 5188 5150 5112 5074 5036 4998 4960 4921 4883 4845 4807 4769 4731 4692 4654 4616 4578 4540 4502 4464 4425 4387 4349 4311 4273 4235 4197 4158 4120 4082 4044 4006 3968 3929 3891 3853 3815 3777 3739 3701 3662 3624 3586 3548 3510 3472 Y 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104
Rev.1.10, Jun.21.2003, page 8 of 133
HD66773R
No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 pad name S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 X 3434 3395 3357 3319 3281 3243 3205 3166 3128 3090 3052 3014 2976 2938 2899 2861 2823 2785 2747 2709 2671 2632 2594 2556 2518 2480 2442 2403 2365 2327 2289 2251 2213 2175 2136 2098 2060 2022 1984 1946 1908 1869 1831 1793 1755 1717 1679 1640 1602 1564 1526 1488 1450 1412 1373 1335 1297 1259 1221 1183 1145 1106 1068 1030 992 954 916 877 839 801 763 725 687 649 610 572 534 496 458 420 382 343 305 267 229 191 153 114 76 38 -38 -76 -114 -153 -191 -229 -267 -305 -343 -382 Y 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 1104 994 1104 994 1104 994 1104 994 1104 994 No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 pad name S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 X -420 -458 -496 -534 -572 -610 -649 -687 -725 -763 -801 -839 -877 -916 -954 -992 -1030 -1068 -1106 -1145 -1183 -1221 -1259 -1297 -1335 -1373 -1412 -1450 -1488 -1526 -1564 -1602 -1640 -1679 -1717 -1755 -1793 -1831 -1869 -1908 -1946 -1984 -2022 -2060 -2098 -2136 -2175 -2213 -2251 -2289 -2327 -2365 -2403 -2442 -2480 -2518 -2556 -2594 -2632 -2671 -2709 -2747 -2785 -2823 -2861 -2899 -2938 -2976 -3014 -3052 -3090 -3128 -3166 -3205 -3243 -3281 -3319 -3357 -3395 -3434 -3472 -3510 -3548 -3586 -3624 -3662 -3701 -3739 -3777 -3815 -3853 -3891 -3929 -3968 -4006 -4044 -4082 -4120 -4158 -4197 Y 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994
No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 pad name S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 DUMMY31 DUMMY32 DUMMY33 DUMMY34 DUMMY35 DUMMY36 DUMMY37 DUMMY38 G175 G173 G171 G169 X -4235 -4273 -4311 -4349 -4387 -4425 -4464 -4502 -4540 -4578 -4616 -4654 -4692 -4731 -4769 -4807 -4845 -4883 -4921 -4960 -4998 -5036 -5074 -5112 -5150 -5188 -5227 -5265 -5303 -5341 -5379 -5417 -5455 -5494 -5532 -5570 -5608 -5646 -5684 -5723 -5761 -5799 -5837 -5875 -5913 -5951 -5990 -6028 -6066 -6104 -6142 -6180 -6218 -6257 -6295 -6333 -6371 -6409 -6447 -6486 -6524 -6562 -6600 -6638 -6676 -6714 -6753 -6791 -6829 -6867 -6905 -6943 -6981 -7020 -7058 -7096 -7134 -7172 -7210 -7249 -7287 -7325 -7363 -7401 -7439 -7477 -7516 -7554 -7630 -7706 -7783 -7859 -7935 -8012 -8088 -8164 -8240 -8279 -8317 -8355 Y 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 1104 1104 1104 1104 1104 1104 1104 1104 994 1104 994 No. 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 pad name G167 G165 G163 G161 G159 G157 G155 G153 G151 G149 G147 G145 G143 G141 G139 G137 G135 G133 G131 G129 G127 G125 G123 G121 G119 G117 G115 G113 G111 G109 G107 G105 G103 G101 G99 G97 G95 G93 G91 G89 G87 DUMMY39 G85 G83 G81 G79 G77 G75 G73 G71 G69 G67 G65 G63 G61 G59 G57 G55 G53 G51 G49 G47 G45 G43 G41 G39 G37 G35 G33 G31 G29 G27 G25 G23 G21 G19 G17 G15 G13 G11 G9 G7 G5 G3 G1 GTEST1 X -8393 -8431 -8469 -8507 -8546 -8584 -8622 -8660 -8698 -8736 -8775 -8813 -8851 -8889 -8927 -8965 -9003 -9042 -9080 -9118 -9156 -9194 -9232 -9270 -9309 -9347 -9385 -9423 -9461 -9499 -9538 -9576 -9614 -9652 -9690 -9728 -9766 -9805 -9843 -9881 -9919 -10209 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10104 -10214 -10214 Y 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 994 1104 1099 801 763 725 687 649 610 572 534 496 458 420 382 343 305 267 229 191 153 114 76 38 0 -38 -76 -114 -153 -191 -229 -267 -305 -343 -382 -420 -458 -496 -534 -572 -610 -649 -687 -725 -763 -801 -877
X -10135 10135 -10119 10119 -10029 10029
Y 935 935 1100 1100 1100 1100
Rev.1.10, Jun.21.2003, page 9 of 133
HD66773R
Pin Function
Signals IM3-1, IM0/ID Number of Pins 4 I/O Connected to I GND or VCC Functions Select the mode interfacing with MPU.
IM3 GND GND GND GND GND GND Vcc Vcc Vcc Vcc Vcc IM2 GND GND GND GND Vcc Vcc GND GND GND GND Vcc IM1 GND GND Vcc Vcc GND Vcc GND GND Vcc Vcc * IM0 GND Vcc GND Vcc ID * GND Vcc GND Vcc * MPU interfacing mode 68-system 16-bit interface 68-system 8-bit interface 80-system 16-bit interface 80-system 8-bit interface Serial Peripheral Interface Setting disabled 68-system 18-bit interface 68-system 9-bit interface 80-system 18-bit interface 80-system 9-bit interface Setting disabled DB17-0 DB17-9 DB17-0 DB17-9 DB pins DB17-10,DB8-1 DB17-10 DB17-10,DB8-1 DB17-10 DB17-10,DB8-1
In Serial Peripheral Interface mode, IMO/ID pin is used for ID setting for the device code. CS* 1 I MPU Chip selection signal. Low: Select HD66773R and accessible High: Not select HD66773R and inaccessible Must be fixed to GND when not used. RS 1 I MPU Register selection signal. Low: Index/status High: Control Must be fixed to Vcc or GND in SPI mode. ENABLE signal to activate data read/write operation in 68-system bus interface. Write strobe signal in 80-system bus interface, write data at low. Synchronizing clock signal in SPI mode. Read/write selection signal in 68-system bus interface. Low: Write, High: Read Read strobe signal in 80-system bus interface, read data at low. Must be fixed to Vcc or GND in SPI mode. 18-bit bi-directional data bus. 8-bit bus interface: DB17-10 9-bit bus interface: DB17-9 16-bit bus interface: DB17-10, 8-1 18-bit bus interface: DB17-0 The pins not used for data transfer must be fixed to Vcc or GND. Serial data input pin (SDI) to input on the rising edge of SCL signal in SPI mode.
E/WR*/SCL
1
I
MPU
RW/RD*
1
I
MPU
DB0/SDI
1
I/O MPU
Rev.1.10, Jun.21.2003, page 10 of 133
HD66773R
Signals DB1/SDO Number of Pins 1 I/O Connected to I/O MPU Functions 18-bit bi-directional data bus. 8-bit bus interface: DB17-10 9-bit bus interface: DB17-9 16-bit bus interface: DB17-10, 8-1 18-bit bus interface: DB17-0 The pins not used for data transfer must be fixed to Vcc or GND. Serial data output pin (SDO) to output on the falling edge of SCL signal in SPI mode. 18-bit bi-directional data bus. 8-bit bus interface: DB17-10 9-bit bus interface: DB17-9 16-bit bus interface: DB17-10, 8-1 18-bit bus interface: DB17-0 The pins not used for data transfer must be fixed to Vcc or GND. Connect to an external resistor for R-C oscillation. When supplying clocks externally, supply with OSC1, and leave OSC2 open. Reset pin. Initialize the LSI at low. Power-on reset required when turning on the power supply. Supply with either one of RESET1,2,3, and leave the unused pins open. Test pin. Must be fixed to GND level. Test pin. Must be fixed to GND level. Logic Vcc: +2.2V ~ +3.3V Logic-side ground, GND: 0V Vcc power supply for internal RAM. Supply same electric potential as Vcc. Analogue-side ground, AGND: 0 V Output GND level. Opposing GND for external elements (capacitors, diodes).
DB2-DB17
16
I/O MPU
OSC1, OSC2
2
I/O
Oscillationresistor MPU or Reset generating circuit GND GND Power supply Power supply Power supply Opposing GND for external elements Vcc or power supply Vcc or power supply
RESET1* RESET2* RESET3* TEST1 TEST2 Vcc, GND RVcc AGND CGND
3
I
1 1 2 1 1 1
I I O
Vci
1
I
Power supply for analogue circuits. Connect to an external power supply of 2.5V ~ 3.3V.
Vci1
1
I/O
DDVDH
1
I/O
Vci2
1
I
VGH
1
I/O
Output internal reference voltage with amplitude between Vci and GND. Reference voltage for step-up circuit1. Connect to an external power supply of 2.75V or lower, when internal reference voltage is not used. Stabilizing Output Vci1 after stepped-up 2~3 times by step-up circuit 1. The Capacitor or step-up scale is determined with internal register setting. Connect open to a stabilizing capacitor. When step-up circuit 1 is not used, leave open. DDVDH or Reference voltage for step-up circuit 2. Connect to DDVDH. power Connect to an external power supply of 5.5V or lower, when supply DDVDH is not used. Stabilizing Output voltage with amplitude between VGH and GND after Capacitor or stepped-up 2~4 times by step-up circuit 2. The step-up scale is power determined with internal register setting. Connect to a stabilizing supply capacitor. When step-up circuit 2 is not used, connect to an external power supply of 16.5V or lower.
Rev.1.10, Jun.21.2003, page 11 of 133
HD66773R
Signals Vci3 Number of Pins 1 I/O Connected to I VGH or DDVDH or power supply Stabilizing Capacitor or power supply Vcc or Vci1 or power supply Stabilizing Capacitor or power supply Functions Reference voltage for step-up circuit 3. Connect to VGH or DDVDH. Connect to an external power supply of 16.5V or lower, when internal power supply is not used. Output voltage with amplitude between VGH and GND after multiplied by -1 by step-up circuit 3. Connect to a stabilizing capacitor. When step-up circuit 3 is not used, connect to an external power supply of -16.5V or more. Reference voltage for a step-up circuit 4. Connect to Vci or an external power supply between 2.5 ~ 3.3 V.
VGL
1
I/O
Vci4
1
I
VCL
1
I/O
VREG1OUT
1
I/O
VREG2OUT
1
I/O
C11+ ~ C23+, 10 C11 - ~ C23 C31+, C312 *\
*\
C41+, C41-
2
*\
Vcom1 Vcom2
2
O
VcomR
1
I
Output voltage with amplitude between Vci4 and GND after multiplied by -1 by step-up circuit 4. Connect to a stabilizing capacitor. Power supply for generating VcomL. When using an external power supply, connect to an external power supply of -3.3V or more if VcomL is negative voltage. When VcomL is GND or more, halt step-up circuit 4 and connect it to GND. Stabilizing Generate from internally generated reference voltage with Capacitor or amplitude Vci-GND and output a reference voltage for VREG1 power with amplitude DDVDH-GND. The step-up scale for output supply voltage is determined with internal register setting. Connect to a stabilizing capacitor. This is a reference voltage for generating Vcom. Connect to an external power supply of DDVDH or lower when step-up circuit 1 is not used. Stabilizing Generate from internally generated reference voltage with Capacitor or amplitude Vci-GND and output a reference voltage for VREG2 power with amplitude GND-VGL. The step-up scale for output voltage is supply determined with internal register setting. Connect to a stabilizing capacitor. This is a reference voltage for generating VgoffOUT. Connect to an external power supply of VGL or more when step-up circuit 2 is not used. Step-up Connect to a step-up capacitor if necessary depending on step-up capacitor scale. When internal step-up circuit is not used, leave open. Step-up Connect to a step-up capacitor for generating the VGL level from capacitor the Vci3 and GND levels. When internal step-up circuit is not used, leave open. Step-up Connect to a step-up capacitor for generating the VCL level from capacitor the Vci4 and GND levels. When internal step-up circuit is not used, leave open. TFT Power supply for TFT common electrode. Output the same common voltage level as VcomL during display off, and output the level electrode with amplitude VcomH-VcomL during display on. The AC cycle is changeable with liquid crystal drive AC control register (R02). Connect to a TFT common electrode. Variable VcomH reference voltage. When VcomH is externally adjusted, resistor or halt the internal adjuster of VcomH with register setting and place open a variable resistor between VREG1OUT and GND. When VcomH is not externally adjusted, leave it open and adjust VcomH with internal register setting.
Rev.1.10, Jun.21.2003, page 12 of 133
HD66773R
Signals VcomH VcomL Number of Pins 1 1 I/O Connected to O O Stabilizing Capacitor Stabilizing Capacitor or open Functions
VgoffOUT
1
O
Vgoff
1
I
VgoffH
1
O
VgoffL
1
O
V0P V31P V0N V31N VGS
2
I/O
2
I/O
1
I
S1-S396
396
O
G1-176 GTEST1-2
176 2
O O
Vcom high level generated during Vcom AC drive. Connect to a stabilizing capacitor. The Vcom level without Vcom AC drive, and Vcom low level with Vcom AC drive. The voltage can be adjusted with internal register setting. Connect to a stabilizing capacitor. VcomL output is halted when VCOMG bit is LOW, and in this case, stabilizing capacitor is not necessary. Vgoff or Output power supply for gate drive. Internal register setting Open enables AC drive in synchronization with Vcom. Make an appropriate setting for the structure of hold capacitor of TFT display. Output the amplitude VcomH-VcomL in reference to VgoffL with AC drive. VgoffOUT or TFT gate off level. Negative voltage. Connect to VgoffOUT or power otherwise, connect to external voltage power supply of VGL or supply more. Stabilizing VgoffOUT high level with Vgoff AC drive. Connect to a stabilizing Capacitor or capacitor. The Vgoff output is halted when CAD bit is LOW. In this case, no stabilizing capacitor is necessary. open Stabilizing VgoffOUT without Vgoff AC drive, and VgoffOUT low level with Capacitor Vgoff AC drive. The voltage can be adjusted with internal register setting. Connect to a stabilizing capacitor. Stabilizing Output from positive-polarity internal operational amplifier when Capacitor the internal operational amplifier is turned on. Connect to a stabilizing capacitor. Stabilizing Output from negative-polarity internal operational amplifier when Capacitor the internal operational amplifier is turned on. Connect to a stabilizing capacitor. GND or Reference voltage for grayscale voltage generating circuit. Place external a variable resistor externally when adjusting a level for each resistor panel. LCD Source output signal. The shift direction of segment signal is changeable with SS bit: SS = 0, RAM address 0000 is output from S1. SS = 1, it is output from S396. S1, S4, S7, ... display red (R), S2, S5, S8, ... display green (G), and S3, S6, S9, ... display blue (B) (SS = 0). LCD Gate output signal. Output VGH level to select a gate line, and output Vgoff level not to select a gate line. LCD or Dummy gate output signal. Output the VGH level to select a gate Open line, and output the Vgoff level not to select a gate line when CAD bit is High. Output the Vgoff level not to select a gate line when CAD bit is Low. Leave open when not used. Stabilizing Capacitor or Open Stabilizing Capacitor or Open Stabilizing Capacitor or Open A test pin for the VcomH output. Leave it open or connect to a stabilizing capacitor if necessary depending on the quality of display. A test pin for the VcomL output. Leave it open or connect to a stabilizing capacitor if necessary depending on the quality of display. A test pin for the Vgoff output. Leave it open or connect to a stabilizing capacitor if necessary depending on the quality of display.
TESTA1
1
I/O
TESTA2
1
I/O
TESTA3
1
I/O
Rev.1.10, Jun.21.2003, page 13 of 133
HD66773R
Signals TESTA4 Number of Pins 1 I/O Connected to I/O Stabilizing Capacitor or Open GND Open Open Open Open GND Open Open Dummy Functions A test pin for the VcomL output. Leave it open or connect to a stabilizing capacitor if necessary depending on the quality of display. A test pin. Must be connected to GND. Test pins. Leave open. A test pin. Leave open. A test pin. Leave open. A test pin. Leave open. A test pin. Must be connected to GND. A test pin for VREG1OUT. Leave open. Test outputs. Leave open. Dummy pads. Connected to nowhere.
DCTEST MTEST1 MTEST2 VTESTS TS0-TS7 VMONI TESTV1 REGP
1 2 1 8 1 1 1
I O I/O O O I I/O O *\
DUMMY1, 22, 4 23, 39 DUMMY2-21, 35 DUMMY24-38
Rev.1.10, Jun.21.2003, page 14 of 133
HD66773R
Block Function
1. System Interface
The HD66773R incorporates three kinds of high-speed system interfaces: 68-system and 80-system interfaces with 18-/16-/9-/8-bit bus, and Serial Peripheral Interface (SPI). The interfacing mode is selected with IM3-0 pins. The HD66773R has three 16-bit registers: index register (IR), write data register (WDR), and read data register (RDR). The IR stores the information of each control register and the index information of GRAM. The WDR temporarily stores data before written to the control register or GRAM. The RDR temporarily stores the data, which is read from GRAM. Data written into GRAM from the MPU is first written into the WDR and then is automatically written into GRAM by internal operation. Since data are read through the RDR from GRAM, the data read out first are invalid and the ensuing data are read out normally. The execution time for the instructions other than oscillation start is 0-clock cycle, which enables instructions to be written consecutively. Register Selection (8/9/16/18 Parallel Interface)
80-system WR* 0 1 0 1 RD* 1 0 1 0 68-system R/W 0 1 0 1 RS 0 0 1 1 Operation Write index into IR Read internal status Write to control register and GRAM through WDR Read from GRAM through RDR
Register Selection (Serial Peripheral Interface)
Start byte R/W Bits 0 1 0 1 RS Bits 0 0 1 1 Operations Write index into IR Read internal status Write to control register and GRAM through WDR Read from GRAM through RDR
2.
Bit Operation
The HD66773R supports write data mask function to write bit data selectively to GRAM and logical arithmetical operation to perform logical arithmetical operation and conditional rewrite on GRAM display data and then rewrite the data to GRAM. These functions significantly reduce the load on the graphicsprocessing software in the microcomputer, and enable high-speed overwrite of GRAM display data. For details, see "Graphics Operation Function".
Rev.1.10, Jun.21.2003, page 15 of 133
HD66773R 3. Address Counter (AC)
The address counter (AC) assigns addresses to GRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing data into GRAM, the AC is automatically updated plus or minus 1. The AC is not updated when the data are read from GRAM. Window address function enables data write only in the rectangular area of GRAM specified by window addresses. 4. Hardware-dither circuit
The hardware-dither circuit converts 18-bit one-pixel data to 16-bit data with hardware-dither conversion. 5. Graphics RAM (GRAM)
GRAM is graphics RAM that stores bit-pattern data of 132 x 176 bytes with 16 bits per pixel. 6. Gray scale power supply voltage generating circuit
The grayscale voltage generation circuit generates liquid crystal drive voltage according to the grayscale level set with the -adjustment register, enabling 262,144-color display with 18 bits per pixel. For details, see the "-adjustment Register" section. 7. LCD drive power supply
The LCD drive power supply generates LCD drive voltage levels, VOP, VON, V31P, V31N, VGH, VGL, VgoffOUT, and Vcom. 8. Oscillation Circuit (OSC)
The HD66773R can provide R-C oscillation simply by placing an external oscillation-resistor between OSC1 and OSC2 pins. An appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can be supplied externally. Since R-C oscillation is halted during standby mode, current consumption will be reduced. For details, see "Oscillation Circuit". 9. LCD Driver Circuit
The LCD driver circuit of HD66773R consists of a 396-output source driver (S1 ~ S396) and a 176-output gate driver (G1 ~ G176). Display pattern data are latched when 396-bit data arrive. The latched data controls source driver and generates drive waveforms. The gate driver, which operates display scan, selects either VGH or Vgoff level to output. The shift direction of outputting 396-bit data from source driver outputs is changeable with the SS bit. The shift direction of gate driver scan is changeable with the GS bit. The scan mode of gate driver is changeable with SM bit. Select an appropriate shift direction and scan mode for an assembly.
Rev.1.10, Jun.21.2003, page 16 of 133
HD66773R
GRAM Address MAP
Gram Address and display position on the panel (SS = "0")
S386 S387
S388 S389
S390
S391 S392
S393 S394
DB DB 0 17
S395
S10
S1
S2
S3 S4
S5
S6 S7
S8
GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20
GS=1 G176 G175 G174 G173 G172 G171 G170 G169 G168 G167 G166 G165 G164 G163 G162 G161 G160 G159 G158 G157
DB 17
DB 0
DB 17
DB DB 0 17
S9
DB 0
DB 17
S12
S11
S/G pin
DB 0
DB 17
DB DB 0 17
DB 0
DB 17
"0100"H
"0000"H "0001"H "0101"H "0200"H "0201"H "0300"H "0301"H "0400"H "0401"H
"0002"H "0003"H "0102"H "0103"H "0202"H "0203"H "0302"H "0303"H "0402"H "0403"H "0502"H "0503"H "0602"H "0603"H "0702"H "0703"H "0802"H "0803"H "0902"H "0903"H "0A02"H "0A03"H "0B02"H "0B03"H "0C02"H "0C03"H "0D02"H "0D03"H "0E02"H "0E03"H "0F02"H "0F03"H "1002"H "1003"H "1102"H "1103"H "1202"H "1203"H "1302"H "1303"H
"0080"H "0180"H "0280"H "0380"H "0480"H "0580"H "0680"H "0780"H "0880"H "0980"H "0A80"H "0B80"H "0C80"H "0D80"H "0E80"H "0F80"H "1080"H "1180"H "1280"H "1380"H
"0081"H "0082"H
"0083"H
"0181"H "0182"H "0183"H "0281"H "0282"H "0283"H "0381"H "0382"H "0383"H "0481"H "0482"H "0483"H "0581 H "0582"H "0681"H "0682"H "0781"H "0782"H "0881"H "0882"H "0583"H "0683"H "0783"H "0883"H
"0500"H "0501 H "0600"H "0601"H "0700"H "0701"H "0800"H "0801"H "0900"H "0901"H "0A00"H "0A01"H "0B00"H "0B01"H "0C00"H "0C01"H "0D00"H "0D01"H "0E00"H "0E01"H "0F00"H "0F01"H "1000"H "1001"H "1100"H "1101"H "1200"H "1201"H "1300"H "1301"H
"0981"H "0982"H "0983"H "0A81"H "0A82"H "0A83"H "0B81"H "0B82"H "0B83"H "0C81"H "0C82"H "0C83"H "0D81"H "0D82"H "0D83"H "0E81"H "0E82"H "0E83"H "0F81"H "0F82"H "0F83"H "1081"H "1082"H "1083"H "1181"H "1182"H "1183"H "1281"H "1282"H "1283"H "1381"H "1382"H "1383"H
G169 G170 G171 G172 G173 G174 G175 G176
G8 G7 G6 G5 G4 G3 G2 G1
"A800"H "A801"H "A900"H "A901"H
"A802"H "A902"H
"A803"H
"A880"H "A980"H "AA80"H "AB80"H "AC80"H "AD80"H "AE80"H "AF80"H
"A903"H "AA00"H "AA01"H "AA02"H "AA03"H "AB00"H "AB01"H "AB02"H "AB03"H "AC00"H "AC01"H "AC02"H "AC03"H "AD00"H "AD01"H "AD02"H "AD03"H "AE00"H "AE01"H "AE02"H "AE03"H "AF00"H "AF01"H "AF02"H "AF03"H
"A881"H "A882"H "A883"H "A981"H "A982"H "A983"H "AA81"H "AA82"H "AA83"H "AB81"H "AB82"H "AB83"H "AC81"H "AC82"H "AC83"H "AD81"H "AD82"H "AD83"H "AE81"H "AE82"H "AE83"H "AF81"H "AF82"H "AF83"H
Rev.1.10, Jun.21.2003, page 17 of 133
S396
DB 0
S385
HD66773R The relationship between GRAM data and display data (SS ="0") The following figures illustrate the relationship between GRAM data and display data in each interface mode.
18-bit interface & hard dithering mode
IF Data
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB DB 9 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
DB 0
Dither process circuit
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
GRAM data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
262,144 colors expansion circuit
Output pins
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
Note: n = lower eight bit of address (0 to 132)
16-bit interface
IF Data
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB DB 10 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
GRAM data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
262,144 colors expansion circuit
Output pins
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 1)
S (3n + 2)
S (3n + 3)
Note: n = lower eight bit of address (0 to 132)
Rev.1.10, Jun.21.2003, page 18 of 133
HD66773R
9-bit interface & hard dither mode First transfer
IF Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 9 17 DB 16
Second transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9
Dither process circuit
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
GRAM data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
262,144 colors expansion circuit
Output pins
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 1)
S (3n + 2)
S (3n + 3) Note: n = lower eight bit of address (0 to 132)
8-bit interface / SPI First transfer
IF Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB DB 10 17 DB 16
Second transfer
DB DB 15 14 DB 13 DB DB 12 11 DB 10
GRAM data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
262,144 colors expansion circuit
Output pins
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 1)
S (3n + 2)
S (3n + 3) Note: n = lower eight bite of address (0 to 132)
Rev.1.10, Jun.21.2003, page 19 of 133
HD66773R Gram Address and display position on the panel (SS = "1", BGR = "1")
S391 S392
S393 S394
DB DB 17 0
S390
S395
S386 S387
S1 S2
S3 S4
S5 S6
GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20
GS=1 G176 G175 G174 G173 G172 G171 G170 G169 G168 G167 G166 G165 G164 G163 G162 G161 G160 G159 G158 G157
DB 0
DB 17
DB 0
DB DB 17 0
S7 S8
S/G pin
DB 17
DB 0
DB 17
DB 0
S388 S389
S385
DB DB 17 0
DB 17
DB 0
DB 17
"0083"H "0183"H "0283"H "0383"H "0483"H
"0082"H "0182"H "0282"H "0382"H "0482"H
"0081"H "0080"H "0181"H "0180"H "0281"H "0280"H "0381"H "0380"H "0481"H "0480"H "0581 H "0580"H "0681"H "0680"H "0781"H "0780"H
"0003"H "0103"H "0203"H "0303"H "0403"H "0503"H "0603"H "0703"H "0803"H "0903"H
"0002"H "0102"H "0202"H "0302"H "0402"H
"0001"H "0101"H "0201"H "0301"H "0401"H
"0000"H "0100"H "0200"H "0300"H "0400"H "0500"H "0600"H "0700"H "0800"H "0900"H "0A00"H
"0583"H "0582"H "0683"H "0682"H "0783"H "0883"H "0782"H
"0502"H "0501 H "0602"H "0601"H "0702"H "0802"H "0902"H "0701"H "0801"H "0901"H
"0882"H "0881"H "0880"H "0983"H "0982"H "0981"H "0980"H "0A83"H "0A82"H "0A81"H "0A80"H "0B83"H "0B82"H "0B81"H "0B80"H "0C83"H "0C82"H "0C81"H "0C80"H "0D83"H "0D82"H "0D81"H "0D80"H "0E83"H "0E82"H "0E81"H "0E80"H "0F83"H "0F82"H "0F81"H "0F80"H "1083"H "1183"H "1283"H "1383"H "1082"H "1182"H "1282"H "1382"H "1081"H "1080"H "1181"H "1180"H "1281"H "1280"H "1381"H "1380"H
"0A03"H "0A02"H "0A01"H
"0B03"H "0B02"H "0B01"H "0B00"H "0C03"H "0C02"H "0C01"H "0C00"H "0D03"H "0D02"H "0D01"H "0D00"H "0E03"H "0E02"H "0E01"H "0F03"H "0F02"H "0F01"H "1003"H "1103"H "1203"H "1303"H "1002"H "1102"H "1202"H "1302"H "1001"H "1101"H "1201"H "1301"H "0E00"H "0F00"H "1000"H "1100"H "1200"H "1300"H
G169 G170 G171 G172 G173 G174 G175 G176
G8 G7 G6 G5 G4 G3 G2 G1
"A883"H "A882"H "A983"H "A982"H "AA83"H "AA82"H
"A881"H "A880"H "A981"H "A980"H "AA81"H "AA80"H
"A803"H "A802"H "A903"H "A902"H
"A801"H "A901"H
"A800"H "A900"H
"AA03"H "AA02"H "AA01"H "AA00"H "AB03"H "AB02"H "AB01"H "AB00"H "AC03"H "AC02"H "AC01"H "AC00"H "AD03"H "AD02"H "AD01"H "AD00"H "AE03"H "AE02"H "AE01"H "AE00"H "AF03"H "AF02"H "AF01"H "AF00"H
"AB83"H "AB82"H "AB81"H "AB80"H "AC83"H "AC82"H "AC81"H "AC80"H "AD83"H "AD82"H "AD81"H "AD80"H "AE83"H "AE82"H "AF83"H "AF82"H "AE81"H "AE80"H "AF81"H "AF80"H
Rev.1.10, Jun.21.2003, page 20 of 133
S396
S9 S10
S12
S11
HD66773R The relationship between GRAM data and display data (SS ="1") The following figures illustrate the relationship between GRAM data and display data in each interface mode.
18-bit interface & hard dither mode
IF Data
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB DB 9 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
DB 0
Dither process circuit
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
GRAM data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
262,144 colors expansion circuit
Output pins
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (396 -3n)
S (395 -3n)
S (394 - 3n) Note: n = lower eight bite of address (0 to 132)
16-bit interface
IF Data
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB DB 10 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
GRAM data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
262,144 colors expansion circuit
Output pins
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (396 -3n)
S (395 -3n)
S (394 - 3n) Note: n = lower eight bite of address (0 to 132)
Rev.1.10, Jun.21.2003, page 21 of 133
HD66773R
9-bit interface & hardware dither mode First transfer
IF Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 9 17 DB 16
Second transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9
Dither process circuit
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
GRAM data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
260,000 colors expansion circuit
Output pins
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (396 - 3n)
S (395 - 3n)
S (394 - 3n) Note: n = lower eight bite of address (0 to 131)
8-bit interface / SPI First transfer
IF Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB DB 10 17 DB 16
Second transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10
GRAM data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
260,000 colors expansion circuit
Output pins
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (396 - 3n)
S (395 - 3n)
S (394 - 3n) Note: n = lower eight bite of address (0 to 131)
Rev.1.10, Jun.21.2003, page 22 of 133
HD66773R
Instructions
Outline The HD66773R adapts 18-bit bus architecture that enables high-speed interfacing with a high-performance microcomputer. Data sent from external (18/16/9/8 bits) are stored temporarily in the instruction register (IR) and the data register (DR) to store control information before internal operation starts. Since internal operation is decided according to the signal sent from the microcomputer, register selection signal (RS), read/write signal (R/W), and internal 16-bit data bus signal (DB15 to DB0) are called instruction. GRAM is accessed through internal 18-bit data bus. There are eight categories of instructions: 1. 2. 3. 4. 5. 6. 7. 8. Specify index Read status Control display Control power management Process graphics data Set internal GRAM addresses Transfer data to and from internal GRAM Set grayscale level for internal grayscale -adjustment
Normally, the 7th instruction to write data to be displayed is executed the most frequently. The address of internal GRAM is updated automatically after data are written to internal GRAM. With window address function, this reduces the amount of data transmission to minimum and thereby lightens the load on the program in the microcomputer. Since instructions are executed in 0 cycle, it is possible to write instructions consecutively. As the following figure shows, the assignment to the 16 instruction bits (IB15-0) varies according to the interface to be used. An instruction must adopt the data format for each interface.
Rev.1.10, Jun.21.2003, page 23 of 133
HD66773R
18-bit interface
DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 9 8 DB 7 DB DB 6 5 DB 4 DB 3 DB 2 DB 1 DB 0
Instr uction bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
16-bit interface
DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB DB 6 5 DB 4 DB 3 DB 2 DB 1
Instr uction bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
9-bit interface
DB 17 DB 16
First transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 9 17 DB 16
Second transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9
Instruction bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
8-bit interface/SPI First transfer
DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16
Second transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10
Instruction bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction bit assignment
Rev.1.10, Jun.21.2003, page 24 of 133
HD66773R Instructions The following are detail explanations of instructions with illustrations of instruction bits (IB15-0) assigned to each interface. Index The index instruction specifies a index (R00h to R3Bh) of control registers and RAM control, that is accessed. It sets the register number from 0000000 to 11111111 in binary form. Do not try to access to the register to which instruction is not assigned.
R/W W RS 0 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 ID6 IB5 ID5 IB4 ID4 IB3 ID3 IB2 ID2 IB1 ID1 IB0 ID0
Status Read The status read instruction reads the internal status of the HD66773R. L7-0: Indicate the position of raster-row driving liquid crystal.
R/W R
RS 0
IB15 IB14 IB13 IB12 IB11 IB10 IB9 L7 L6 L5 L4 L3 L2 L1
IB8 L0
IB7 0
IB6 0
IB5 0
IB4 0
IB3 0
IB2 0
IB1 0
IB0 0
Start Oscillation (R00h) The start oscillation instruction restarts the oscillator in a halt state during standby mode. After executing this instruction, wait at least 10 ms for stabilizing oscillation before issuing a next instruction. For details, see the "Standby Mode" section. "0773"H is read out, if this register is forced to read out.
R/W W
RS 0
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0 1
0 0 0 0 0 1 1 1 0 1 1 1 0 0 1
R
1
1
Rev.1.10, Jun.21.2003, page 25 of 133
HD66773R Driver Output Control (R01h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 SM GS
IB8 SS
IB7 0
IB6 0
IB5 0
IB4
IB3
IB2
IB1
IB0
NL4 NL3 NL2 NL1 NL0
GS: Select the shift direction of outputs from the gate driver. The scan order by the gate driver is changeable in accordance to the scan mode of gate driver. Select an optimum shift direction for the assembly. SM: Set the scan order by the gate driver. Select an optimum scan order for the assembly. For details, see "Scan Mode Setting". SS: Select the shift direction of outputs from the source driver. When SS = 0, the shift direction of outputs is from S1 to S396. When SS = 1, the shift direction of outputs is from S396 to S1. In addition to the shift direction, setting for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins. To assign R, G, B dots to the source driver pins interchangeably from S1, set SS = 0, BGR = 0. To assign R, G, B dots to the source driver pins interchangeably from S396, set SS = 1, BGR = 1.
Rev.1.10, Jun.21.2003, page 26 of 133
HD66773R NL4-0: Specify the number of LCD drive raster-rows. The number of drive raster-rows is adjusted by 8 multiple raster-rows. The mapping of addresses to GRAM is independent of this setting. Select the number of raster-rows so that the display size covers the size of a panel. NL bits NL4 NL3 NL2 NL1 NL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Display Size Setting disabled 396 x 16 dots 396 x 24 dots 396 x 32 dots 396 x 40 dots 396 x 48 dots 396 x 56 dots 396 x 64 dots 396 x 72 dots 396 x 80 dots 396 x 88 dots 396 x 96 dots 396 x 104 dots 396 x 112 dots 396 x 120 dots 396 x 128 dots 396 x 136 dots 396 x 144 dots 396 x 152 dots 396 x 160 dots 396 x 168 dots 396 x 176 dots
Number of LCD Driver Lines
Gate Driver Used Setting disabled G1 to G16 G1 to G24 G1 to G32 G1 to G40 G1 to G48 G1 to G56 G1 to G64 G1 to G72 G1 to G80 G1 to G88 G1 to G96 G1 to G104 G1 to G112 G1 to G120 G1 to G128 G1 to G136 G1 to G144 G1 to G152 G1 to G160 G1 to G168 G1 to G176
Setting disabled 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176
Note 1) A blanking period which lasts 8H, where all gate lines output Vgoff level, will be inserted after driving all gate lines.
Rev.1.10, Jun.21.2003, page 27 of 133
HD66773R LCD Driving Waveform Control (R02h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 FLD1 FLD0 B/C IB8 EOR IB7 0 IB6 0 IB5 IB4 IB3 IB2 IB1 IB0
NW5 NW4 NW3 NW2 NW1 NW0
FLD1-0: Specify the number of fields during n-field interlaced drive. For details, see "Interlaced Drive". FLD Bits
FLD1 0 0 1 1 FLD0 0 1 0 1 Number of Fields Setting disabled 1 field Setting disabled 3 fields
B/C: When B/C =0, a field AC waveform is generated. Alternation occurs every frame to drive liquid crystal. When B/C=1, alternation occurs every n raster-rows according to the settings in EOR and NW5-0 bits of the LCD driving waveform control register. For details, see "n-raster-row Inversion AC Drive". EOR: When EOR = 1 and a C-pattern waveform is generated (B/C =1), an odd/even frame select signal and an n-raster-row inversion signal are AC-driven. This instruction is available when liquid crystal AC drive is not made depending on the combination of numbers of LCD drive raster-rows and the value of "n" of n-raster-row inversion AC drive. For details, see "n-raster-row inversion AC drive". NW5-0: Specify n, the number of raster-rows from 1 to 64 to alternate every n+1 raster-rows when Cpattern waveform is generated (B/C = 1).
Rev.1.10, Jun.21.2003, page 28 of 133
HD66773R Power Control 1 (R03h) Power Control 2 (R04h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
BT2 BT1 BT0
DC2 DC1 DC0
AP2 AP1 AP0
SLP STB
W
1
CAD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BT2-0: Change the step-up scale of the step-up circuit. Adjust the scale according to the voltage. Smaller scale consumes lesser current.
BT2 0 0 0 0 1 1 1 1 BT1 0 0 1 1 0 0 1 1 BT0 0 1 0 1 0 1 0 1 DDVDH Output 2 x Vci1 2 x Vci1 3 x Vci1 3 x Vci1 2 x Vci1 2 x Vci1 Step-up disabled Setting disabled VGH Output 3 x Vci2 4 x Vci2 3 x Vci2 2 x Vci2 Vci1 + 2 x Vci2 Vci1 + 3 x Vci2 3 x Vci2 Setting disabled Note* VGH = Vci1 x 6 VGH = Vci1 x 8 VGH = Vci1 x 9 VGH = Vci1 x 6 VGH = Vci1 x 5 VGH = Vci1 x 7 VGH = Vci2 x 3 Setting disabled Capacitor connect pin DDVDH, VGH, VGL, VCL, C11, C21, C22, C31, C41 DDVDH, VGH, VGL, VCL, C11, C21, C22, C23, C31, C41 DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, C31, C41 DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, C31, C41 DDVDH, VGH, VGL, VCL, C11, C21, C22, C31, C41 DDVDH, VGH, VGL, VCL, C11, C21, C22, C23, C31, C41 DDVDH, VGH, VGL, VCL, C21, C22, C31, C41
Note*) The VGH is stepped-up from Vci1, which is the voltage level when DDVDH and Vci2 is short-circuited. The VGH must be set to satisfy VDDVDH 5.5 V and VGH 16.5 V.
Rev.1.10, Jun.21.2003, page 29 of 133
HD66773R DC2-0: Select the operating frequency for the step-up circuit. The higher step-up frequency enhances the drive capacity of step-up circuit as well as the display quality, while the current consumption will increase. Adjust the frequency taking both the display quality and the current consumption into consideration.
DC2 0 0 0 0 1 1 1 1 DC1 0 0 1 1 0 0 1 1 DC0 0 1 0 1 0 1 0 1 Step-up Cycle of Step-up Circuit 1 DCCLK /16 DCCLK / 32 DCCLK / 64 DCCLK / 32 DCCLK / 16 DCCLK / 32 DCCLK / 64 DCCLK / 64 Step-up Cycle in Step-up Circuits 2/3/4 DCCLK / 64 DCCLK / 64 DCCLK / 64 DCCLK / 256 DCCLK / 128 DCCLK / 128 DCCLK / 128 DCCLK / 256
AP2-0: Adjust the amount of fixed current from the fixed current source in the operational amplifier circuit in the liquid crystal drive power supply. When the amount of fixed current is set large, the liquid crystal drive capacity is enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. During non-display operation, set AP2-0 = "000" to halt the operation of operational amplifier and step-up circuit to further reduce current consumption.
AP2 0 0 0 0 1 1 1 1 AP1 0 0 1 1 0 0 1 1 AP0 0 1 0 1 0 1 0 1 Amount of Current in Operational Amplifier Halt operational amplifier and step-up circuit Small Small or medium Medium Medium or large Large Setting disabled Setting disabled
SLP: When SLP = 1, the HD66773R enters into the sleep mode. In the sleep mode, internal display operation is halted except the R-C oscillator to reduce current consumption. No change is made to the GRAM data or instructions during the sleep mode, but it is retained. STB: When STB = 1, the HD66773R enters into the standby mode. In the standby mode, display operation is completely halted, and all internal operation including the internal R-C oscillator and reception of external clock pulse, is halted. For details, see "Standby Mode". Only instructions to access R03h including the standby bit and to start oscillation are accepted during the standby mode. CAD: Make an appropriate setting for the structure of TFT panel holding capacitor. Set CAD = "0" for Cst structure. Set CAD = "1" for Cadd structure.
Rev.1.10, Jun.21.2003, page 30 of 133
HD66773R Power Control 3 (R0Ch) Power Control 4 (R0Dh) Power Control 5 (R0Eh)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 0 0
IB8 0
IB7 0
IB6 0
IB5 0
IB4 0
IB3 0
IB2
VC2
IB1
VC1
IB0
VC0
W
1
0
0
0
VRL3 VRL2 VRL1 VRL0
0
0
0
PON VRH3 VRH2 VRH1 VRH0
W
1
0
0
VCO VDV4 VDV3 VDV2 VDV1 VDV0 MG
0
0
0
VCM4 VCM3 VCM2 VCM1 VCM0
VC2-0: Adjust reference voltage for VREG1OUT, VREG2OUT, and Vci1 to the level of Vci multiples. When VC2-0 = "111", internal reference voltage generation is halted and an arbitrary level of voltage can be applied through Vci1.
VC2 0 0 0 0 1 1 1 1 VC1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 0 1 0 1 VREG1OUT (reference, Vci1 output , REGP output voltage) Vci 0.92 x Vci 0.87 x Vci 0.83 x Vci 0.76 x Vci 0.73 x Vci 0.68 x Vci Vci1: Hi-Z REGP: GND
Note) Leave REGP open so that the voltage as specified above is output.
Rev.1.10, Jun.21.2003, page 31 of 133
HD66773R VRL3-0: Set the amplifying scale of VREG2OUT voltage (the reference voltage for Vgoff). The output from Vci voltage adjustment circuit can be amplified by -1.5 ~ -6.5 times.
VRL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VRL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VRL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VRL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VREG2OUT Voltage Vci x -1.5 Vci x- 2.0 Vci x - 2.5 Vci x - 3.0 Vci x- 3.5 Vci x - 4.0 Vci x - 4.5 Halt Vci x - 5.0 Vci x - 5.5 Vci x - 6.0 Vci x - 6.5 Setting inhibited Setting inhibited Setting inhibited Halt
Note) Adjust Vci and VRL3-0 so that the VREG2OUT voltage is -16.0 V or more.
PON: Start operation of step-up circuit 3. To halt operation, set PON = 0. To start operation, set PON = 1.
Rev.1.10, Jun.21.2003, page 32 of 133
HD66773R VRH3-0: Set the amplifying scale of VLOUT1 voltage (the reference voltage for VCOM and grayscale voltage). The output from Vciout output amplifier can be amplified by 1.33 ~ 2.775 times.
VRH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VRH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VRH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VRH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VREG1OUT Voltage REGP x 1.33 REGP x 1.45 REGP x 1.55 REGP x 1.65 REGP x 1.75 REGP x 1.80 REGP x 1.85 Halt REGP x 1.900 REGP x 2.175 REGP x 2.325 REGP x 2.475 REGP x 2.625 REGP x 2.700 REGP x 2.775 Halt
Note) Adjust VC2-0 and VRH3-0 so that the VREG1OUT voltage is 5.0 V or less.
VCOMG: When VCOMG = 1, VcomL outputs a negative voltage up to -5V. When VCOMG = 0, the VcomL voltage is GND and negative-polarity amplifier is halted to reduce power consumption. When VCOMG = "0", the setting in VDV4-0 is made invalid. In this case, make adjustment for the AC amplitudes of Vcom and Vgoff with VCM4-0, VocomH settings.
Rev.1.10, Jun.21.2003, page 33 of 133
HD66773R VDV4-0: Set the AC amplitude of Vcom and Vgoff during Vcom AC drive. The amplitude can be specified within the range of VREG1OUT x 0.6 ~ 1.23. When VCOMG = 0, this setting is invalid.
VDV4 0 0 0 : 0 0 0 0 1 1 1 1 1 1 1 1 1 VDV3 0 0 0 : 1 1 1 1 0 0 0 0 0 0 0 0 1 VDV2 0 0 0 : 1 1 1 1 0 0 0 0 1 1 1 1 * VDV1 0 0 1 : 0 0 1 1 0 0 1 1 0 0 1 1 * VDV0 0 1 0 : 0 1 0 1 0 1 0 1 0 1 0 1 * VREG1OUT x 0.96 VREG1OUT x 0.99 VREG1OUT x 1.02 Setting disabled VREG1OUT x 1.05 VREG1OUT x 1.08 VREG1OUT x 1.11 VREG1OUT x 1.14 VREG1OUT x 1.17 VREG1OUT x 1.20 VREG1OUT x 1.23 Setting disabled Vcom Amplitude VREG1OUT x 0.60 VREG1OUT x 0.63 VREG1OUT x 0.66
Note) Adjust VREG1OUT and VDV4-0 so that the Vcom and Vgoff amplitudes are 6.0 V or less.
Rev.1.10, Jun.21.2003, page 34 of 133
HD66773R VCM4-0: Set the VcomH voltage (The higher voltage during Vcom AC drive). The amplitude can be specified within the range of VREG1OUT x 0.4 ~ 0.98. When VCM4-0 = "1111", the internal volume adjustment operation is halted, and the VcomH voltage can be adjust by placing an external resistor at VcomR.
VCM4 0 0 0 : 0 0 0 0 1 1 1 : 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 : 1 1 1 1 VCM3 0 0 0 : 1 1 1 1 0 0 0 : 0 0 1 1 VCM2 0 0 0 : 0 0 1 1 0 0 1 : 0 1 0 1 VCM1 0 0 1 : 0 1 0 1 0 1 0 : VREG1OUT x 0.94 VREG1OUT x 0.96 VREG1OUT x 0.98 Halt internal volume. Adjust by an external variable resistor VcomR. VCM0 0 1 0 : VREG1OUT x 0.64 VREG1OUT x 0.66 VREG1OUT x 0.68 Halt internal volume. Adjust by an external variable resistor VcomR. VREG1OUT x 0.70 VREG1OUT x 0.72 VREG1OUT x 0.74 VcomH Voltage VREG1OUT x 0.40 VREG1OUT x 0.42 VREG1OUT x 0.44
Note) Adjust VREG1OUT and VCM4-0 so that the VcomH voltage is the VDH level or less.
1 CL1 FLM
VGH
2
3
1
2
3
VGH Vgoff
GTEST1,2
Vgoff
GTEST1, 2 Output Timing Chart
Rev.1.10, Jun.21.2003, page 35 of 133
HD66773R Entry Mode (R05h) Compare Register (R06h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 DIT 0 0 BGR 0 0 HWM IB8 0 IB7 0 IB6 0 IB5 IB4 IB3 AM IB2 IB1 IB0
I/D1 I/D0
LG2 LG1 LG0
W
1
CP15 CP14 CP13 CP12 CP11 CP10 CP9
CP8
CP7 CP6 CP5
CP4
CP3
CP2
CP1
CP0
The HD66773R modifies write data sent from the microcomputer before writing to GRAM. This enables high-speed GRAM data update, and reduces the load on the microcomputer software. For details, see "Graphics Operation Function". HWM: When HWM=1, data are written to GRAM in high speed. In high-speed write mode, 4 words are written to GRAM in a single operation after executing 4 RAM write operations. If RAM write is terminated before it is executed 4 times, the last data will not be written. Make sure that RAM write is executed 4 times. For this reason, the lower 2 bits must be set to "0" when setting the RAM address. For details, "High-Speed RAM Write Mode". I/D1-0: The address counter is automatically incremented by 1, after data are written to GRAM when I/D10 = "1". The address counter is automatically decremented by 1, after data are written to GRAM when I/D1-0 = "0". The setting for the increment or decrement of the address counter can be made independently for each upper and lower bits of the address. The transition direction of the address when data are written to GRAM is set with AM bits. AM: Set the direction in which the address counter is updated automatically after data are written to GRAM. When AM = "0", the address counter is updated in the horizontal direction. When AM = "1", the address counter is updated in the vertical direction. When window addresses are specified, data are written to the GRAM area specified by the window address in the manner specified with I/D1-0, AM bits. DIT: Hardware-dither mode when DIT = "1". Use hardware-dither mode with 18/9-bit interface modes.
I/D1-0="00"
Horizontal: decrement Vertical: decrement
0000h
I/D1-0="01"
Horizontal: increment Vertical: decrement
0000h
I/D1-0="10"
Horizontal: decrement Vertical: increment
0000h
I/D1-0="11"
Horizontal: increment Vertical: increment
0000h
AM="0" Horizontal
AF83h 0000h 0000h AF83h 0000h AF83h 0000h AF83h
AM="1" Vertical
AF83h AF83h AF83h AF83h
Note: When the window address is set, data are written only in the window address area on GRAM.
Address transition direction
Rev.1.10, Jun.21.2003, page 36 of 133
HD66773R LG2-0: Rewrite data to GRAM after comparing the data that are written by the microcomputer to GRAM with the values in the compare registers (CP17-0) and performing a logical operation. For details, see "Graphics Operation function". CP15-0: Set the value for the compare register, with which the data read out from GRAM or data written to GRAM by the microcomputer are compared. This function is not available with 18/19-bit interface modes. In 18/19-bit interface modes, make sure LG2-0 = "000". BGR: Reverse the order from R, G, B to B, G, R for GRAM data. When setting BGR = 1, CP15-0 and WM15-0 bits will be automatically changed to the same effect.
18 bit
Write data (Note 1) 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0
RGB- BGR conversion (BGR)
Logical/compare operation (LG2 - 0)
Logical Operatioin on GRAM write data LG2-0 = "000" : Replace LG2-0 = "001" : OR LG2-0 = "010" : AND LG2-0 = "011" : EOR
Compare (Compare W/R data with compare register) LG2-0 = "100": READ data correspond LG2-0 = "101": READ data not correspond LG2-0 = "110": Write data correspond LG2-0 = "111": Write data not correspond
Write data mask* (WM15 - 0) (Note 2)
Wrte data mask (WM15-0)
GRAM
Note 1) The logical and compare operations are effective in 8-/16-bit interace modes. Otherwise, set LG2-0 = "000". The bit assignment is different for each interface mode. Note 2) Write data mask (WM15-0) is set with the RAM write data mask register. The write data mask is available in 8-/16-bit interace modes.
Rev.1.10, Jun.21.2003, page 37 of 133
HD66773R Display Control 1 (R07h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 PT1 IB8 IB7 0 IB6 0 IB5 IB4 IB3 CL IB2 REV IB1 D1 IB0 D0
PT0 VLE2 VLE1 SPT
GON DTE
PT1-0: Specify the kind of source output when non-display area is driven in the partial display mode. For details, see "Screen-split drive function". VLE2-1: When VLE1 = 1, the first screen is scrolled in the vertical direction. When VLE2 = 1, the second screen is scrolled in the vertical direction. The first and second screens cannot be scrolled simultaneously. This function is not available with external display interface mode. VLE Bits
VLE2 0 0 1 1 VLE1 0 1 0 1 Image on 2nd Screen Stationary Stationary Scrolled Setting disabled Image on 1st Screen Stationary Scrolled Stationary Setting disabled
CL: When CL = 1, 8-color display mode is selected. For details, see "8-Color Display Mode". CL Bit
CL 0 1 Colors 65,536 8
SPT: When SPT = 1, liquid crystal is driven with 2 split screens. For details, see "Screen Split Drive Function".
Rev.1.10, Jun.21.2003, page 38 of 133
HD66773R REV: When REV = 1, a reverse display is shown. Inverting the grayscale levels allows the display of same data on both normally white and normally black panels. The source output level is as follows. Combination with partial display
Source output level non-display area REV GRAM data 16'h0000 0 16'hFFFF 16'h0000 1 16'hFFFF V31 V0 V0 V0 V31 V31 V31 V0 GND GND Hi-z Hi-z Display area
VCOM ="L" VCOM ="H"
PT1-0 = (0.*)
VCOM="L" VCOM="H"
PT1-0= (1.0)
VCOM ="L" VCOM ="H"
PT1-0 = (1.1)
VCOM ="L" VCOM ="H"
V31
V0 V31 V0 GND GND Hi-z Hi-z
Combination with D1-0 bits
Source output level REV GRAM data 16'h0000 0 16'hFFFF 16'h0000 1 16'hFFFF V31 V0 V0 V0 V31 V31 V31 V0 GND GND GND GND D1-0 = (1.1)
VCOM ="L" VCOM ="H"
D1-0 = (1.0)
VCOM ="L" VCOM ="H"
D1-0 = (0.1)
VCOM ="L" VCOM ="H"
D1-0 = (0.0)
VCOM ="L" VCOM ="H"
V31
V0 V31 V0 GND GND GND GND
GON: When GON = 0, the gate-off level is VGH. D1-0: The graphics display is on when D1 = 1, and off when D1 = 0. When setting D1 = 0, the data are retained in GRAM. This means the graphics is instantly redisplayed when setting D1 to 1. When D1 is 0 (i.e., the display is off) all the source outputs are set to the GND level. This reduces the charged/discharged current during liquid crystal AC drive. When D1-0 = 01, the HD66773R continues internal display operation, even while the external display is off. When D1-0 = 00, both internal and external display operation are halted. In combination with GON and DTE bits, D1-0 bits control ON/OFF of display. For details, see "Instruction Setting Flow".
Rev.1.10, Jun.21.2003, page 39 of 133
HD66773R
HD66773R Internal Display Operation Halt Operate Operate Operate Operate
GON 0 0 1 1 1
DTE 0 0 0 0 1
D1 0 0 0 1 1
D0 0 1 1 1 1
Source output GND GND GND Grayscale level output Grayscale level output
Gate output VGH VGH VGOFF VGOFF Gate selective line: VGH, Gate non-selective line: VGOFF
Note 1) GRAM write operation from the microcomputer is irrelevant to the setting in D1-0. Note 2) In the standby mode, D1-0 = "00. The setting in the register D1-0 is retained.
Frame Cycle Control (R0Bh)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 IB2 IB1 IB0
NO1 NO0 SDT1 SDT0 EQ1 EQ0 DIV1 DIV0
RTN3 RTN2 RTN1 RTN0
RTN3-0: Set the 1H (1 raster-row) period. RTN Bits and Clock Cycles
RTN3 0 0 0 RTN2 0 0 0 RTN1 0 0 1 : 1 1 1 1 1 1 0 1 RTN0 0 1 0 Clock Cycles per Raster-row 16 clocks 17 clocks 18 clocks : 30 clocks 31 clocks
Rev.1.10, Jun.21.2003, page 40 of 133
HD66773R DIV1-0: Set the division ratio of clocks for internal operations (DIV1-0). Internal operations are in synchronization with the clock, the frequency of which is divided according to the DIV1-0 setting. When changing the number of drive raster-rows, adjust the frame frequency too. For details, see "Frame Frequency Adjustment Function".
DIV1 0 0 1 1 DIV0 0 1 0 1 Division Ratio 1 2 4 8 Internal Operating Clock Frequency fosc / 1 fosc / 2 fosc / 4 fosc / 8
fosc = R-C oscillation frequency
Formula for the frame frequency fosc Frame frequency Clock cycles per raster-row x division ratio x (Line + 8) fosc: R-C oscillation frequency Line: number of drive raster-rows (NL bit) Division ratio: DIV bit Clock cycles per raster-row: RTN bit [Hz]
EQ1-0: Set the period for equalization, where Vcom output becomes Hi-z.
EQ1 0 0 1 1 EQ0 0 1 0 1 Equalizing period Not equalized 1 clock 2 clocks 3 clocks
Note) Equalizing is valid while VcomL is 0V or more. Otherwise, set EQ = "00"
Rev.1.10, Jun.21.2003, page 41 of 133
HD66773R SDT1-0: Determine the amount of delay for the source output from the falling edge of the gate output.
SDT1 0 0 1 1 SDT0 0 1 0 1 Delay Time for Source Signal 1 clock 2 clocks 3 clocks 4 clocks
1H period
1H period
Gn Sn EQ
Delay amount of the source output Equalizing period
NO1-0: Specify the amount of non-overlap time for the gate output.
NO1 0 0 1 1 NO0 0 1 0 1 0 clock 4 clocks 6 clocks 8 clocks Non-overlap time
1H period
1H period
Gn Gn+1
Non-overlap period
Rev.1.10, Jun.21.2003, page 42 of 133
HD66773R Gate Scan Position (R0Fh)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0
IB9 0
IB8 0
IB7 IB6 0 0
IB5 0
IB4
IB3
IB2
IB1
IB0
SCN4 SCN3 SCN2 SCN1 SCN0
SCN4-0: Specify the position where the gate scan starts.
Scan Start Position SCN4 0 0 0 . . 1 1 SCN3 0 0 0 . . 0 0 SCN2 0 0 0 . . 1 1 SCN1 0 0 1 . . 0 0 SCN0 0 1 0 . . 0 1 GS = 0 G1 G9 G17 . . G161 G169 GS = 1 G176 G168 G160 . . G17 G9
G1 G17
G1
G57
G176 GS=0 NL=10011 SCN4-0=00010
G176 GS=0 NL=01110 SCN4-0=00111 Note: Set NL so that the gate scan end position does not exceed G176.
Rev.1.10, Jun.21.2003, page 43 of 133
HD66773R Vertical Scroll Control (R11h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0
VL7-0: Specify the number of raster-rows to be scrolled and control smooth scrolling in the vertical direction. The number of raster-rows is specified between 0 to 176, the raster-rows of the specified number are scrolled during display. When the 176th raster-row is displayed, the scrolling display starts afresh from the 1st raster-row. The number of raster-rows to be scrolled (VL7-0) can be specified when the first screen vertical scroll enable bit VLE1 = 1 or the second screen vertical scroll enable bit VLE2 = 1. The number of raster-rows is fixed (not changeable) when VLE2-1 = 00.
VL7 0 0 0 . . 1 1 VL6 0 0 0 . . 1 1 VL5 0 0 0 . . 1 1 VL4 0 0 0 . . 0 0 VL3 0 0 0 . . 1 1 VL2 0 0 0 . . 1 1 VL1 0 0 1 . . 1 1 VL0 0 1 0 . . 0 1 Amount of Scrolling (Number of raster-row) 0 raster-row 1 raster-row 2 raster-rows . . 174 raster-rows 175 raster-rows
Note: When setting the number of raster-rows for scrolling, it must be 175 ("AF"h) or less.
1st-Screen Drive Position (R14h) 2nd-Screen Drive Position (R15h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
W
1
SS17-10: Specify the start position for driving the first screen by line. The liquid crystal is driven by from the gate driver of "the set value + 1". SE17-10: Specify the end position for driving the first screen by line. The liquid crystal is driven by to the gate driver of "the set value + 1". For instance, when SS17-10 = "07"H and SE17-10 = "10"H, the liquid crystal is driven from G8 to G17, and black display is driven from G1 to G7, and G18 thereafter. Make sure that SS17-10 SE17-10 "AF"H. For details, see "Screen-split Drive Function". SS27-20: Specify the start position for driving the second screen by line. The liquid crystal is driven by from the gate driver of "the set value + 1". The second screen is driven when SPT = 1.
Rev.1.10, Jun.21.2003, page 44 of 133
HD66773R SE27-20: Specify the end position for driving the second screen by line. The liquid crystal is driven by to the gate driver of "the set value + 1". For instance, when SPT = 1, and SS27-20 = "20"H, SE27-20 = "4F"H, the liquid crystal is driven from 33 to G80. Make sure that SS17-10 SE17-10 < SS27-20 SE27-20 "AEF"H. For details, see "Screen-split Drive Function". Horizontal RAM Address Position (R16h) Vertical RAM Address Position (R17h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
W
1
VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
HSA7-0/HEA7-0: Specify the start/end positions of the window-address range by address in the horizontal direction. Data are written to GRAM within the area determined by the addresses specified by HEA7-0 and HSA7-0. These addresses must be set before RAM write. In setting these bits, make sure that "00"h HSA7-0 HEA7-0 "83"h. VSA7-0/VEA7-0: Specify the start/end positions of the window-address range by address in the vertical direction. Data are written to GRAM within the area determined by the addresses specified by VEA7-0 and VSA7-0. These addresses must be set before RAM write. In setting these bits, make sure that "00"h VSA7-0 VEA7-0 "AF"h.
HSA
0000h
HEA
VSA
Window Address setting range "00"h "00"h HSA7-0 VSA7-0 HEA7-0 VEA7-0 "83"h "AF"h
Window Address
VEA
GRAM Address Space AF83h
Note 1) The window address area should be set within the GRAM address space. Note 2) In the high speed write mode, data are written to GRAM every 4 word. Some window address setting may require insurtion of dummy write. See "High Speed Burst RAM write". Note 3) The address set must be within the window address area. In the high speed write mode, set within the area including dummy write area.
Rev.1.10, Jun.21.2003, page 45 of 133
HD66773R RAM Write Data Mask (R20h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 WM WM WM WM WM WM WM WM WM WM WM WM 15 12 11 10 9 8 5 4 7 6 14 13
IB3
IB2
IB1
IB0
WM WM WM WM 3 2 1 0
WM15-0: Write-mask the data when written to GRAM by bit. The write-mask function is available with 8/16-bit interface modes. For example, if WM15 = 1, the data in WD15 bit is write-masked so that it is not written to GRAM. The rest of WM14-0 bits also write-mask the data in the corresponding WD bits when these bits are set to "1". For details, see "Graphics Operation Function". RAM Address Set (R21h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 AD 15 AD 14 AD 13 AD 12 AD 11 AD 10 IB9 AD 9 IB8 AD 8 IB7 IB6 AD 7 AD 6 IB5 AD 5 IB4 AD 4 IB3 IB2 AD 3 AD 2 IB1 AD 1 IB0 AD 0
AD15-0: Make a GRAM address initial setting in the address counter (AC). After GRAM data are written, the address counter is automatically updated according to the settings with AM, I/D bits and the setting for a new GRAM address is not required in the address counter. Therefore, data are written consecutively without resetting the address. The address counter is not automatically updated when data are read out from GRAM. GRAM address setting can not be made during the standby mode. An address set should be made within the area specified with the window address. GRAM Address Range
AD15-AD0 "0000"H - "0083"H "0100"H - "0183"H "0200"H - "0283"H "0300"H - "0383"H : "AC00"H - "AC83"H "AD00"H - "AD83"H "AE00"H - "AE83"H "AF00"H - "AF83"H GRAM Setting Bitmap data for G1 Bitmap data for G2 Bitmap data for G3 Bitmap data for G4 : Bitmap data for G173 Bitmap data for G174 Bitmap data for G175 Bitmap data for G176
Rev.1.10, Jun.21.2003, page 46 of 133
HD66773R Write Data to GRAM (R22h)
R/W W RS 1
RAM write data (WD17-0) The pin assignment for DB17-0 varies for each interface (see below).
PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9
When RGB-I/F
PD8 WD 8
PD7 WD 7
PD6 WD 6
PD5 WD 5
PD4 WD 4
PD3
PD2
PD1 WD 1
PD0 WD 0
WD 17
WD WD 16 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD WD 2 3
WD17-0: All data are expanded into 18 bits internally before being written to GRAM. Each interface has its own way of expanding data to 18 bits. The grayscale level is selected according to GRAM data. The address is automatically updated according to the setting with the AM and I/D bits after data are written to GRAM. During the standby mode, no access is allowed to GRAM. When the 9 or 18 bit interface mode is selected, set DIT = "1" to activate the internal hardware-dither circuit before writing to GRAM.
18-bit interface
Input pin
262,144 colors available
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB DB 9 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
DB 0
Dither process circuit
HD HD HD HD HD HD HD 17 16 15 14 13 12 11 Shrinking WD WD WD WD WD 15 14 13 12 11
HD HD HD HD HD HD HD HD HD HD HD 10 9 8 7 6 5 4 3 2 1 0 Shrinking
GRAM write data
WD WD WD WD WD WD WD WD WD WD WD 0 10 9 8 7 6 5 4 3 2 1
RGB assignment
R4
R3
R2
R1
R0
G5
G4
G3 G2 1 pixel
G1
G0
B4
B3
B2
B1
B0
Note: Write data into GAM after setting DIT = "1".
Rev.1.10, Jun.21.2003, page 47 of 133
HD66773R
16-bit interface
Input pin
65,536 Colors available DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB DB 6 5 DB 4 DB 3 DB 2 DB 1
GRAM write data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RGB assignment
R4
R3
R2
R1
R0
G5
G4 G3
G2
G1
G0
B4
B3
B2
B1
B0
1 pixel
9-bit Interface
262,144 Colors available
First transfer (Upper)
Input pin DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17
Second transfer (Lower)
DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9
Dither process circuit
HD HD HD HD HD HD HD 17 16 15 14 13 12 11 Shr inking WD WD WD WD WD 15 14 13 12 11
HD HD HD HD HD HD HD HD HD HD HD 10 9 8 7 6 5 4 3 2 1 0 Shr inking
GRAM write data
WD WD WD WD WD WD WD WD WD WD WD 0 10 9 8 7 6 5 4 3 2 1
RGB assignment
R4
R3
R2
R1 R0
G5
G4 G3
G2
G1 G0
B4
B3
B2
B1
B0
1 pixel Note :Write data to GRAM after setting DIT = "1".
8-bit Interface
65,536 Colors available
First transfer (Upper)
Input pin DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 17
Second transfer (Lower)
DB DB 16 15 DB 14 DB 13 DB 12 DB 11 DB 10
GRAM write data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 15 14 13 12 11 10 0 9 8 7 6 5 4 3 2 1
RGB assignment
R4
R3
R2
R1 R0
G5
G4
G3
G2
G1 G0
B4
B3
B2
B1
B0
1 pixel
Rev.1.10, Jun.21.2003, page 48 of 133
HD66773R GRAM data and liquid crystal output level
GRAM Data Setting G 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 R/B 00000 00001 00010 00011 00100 00101 00110 00111 -
Selected grayscale Negative V0 V0 - V1 V1 V1 -V2 V2 V2 - V3 V3 V3 - V4 V4 V4 - V5 V5 V5 - V6 V6 V6 - V7 V7 V7 - V8 Positive
GRAM Data Setting G 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 R/B 01000 01001 01010 01011 01100 01101 01110 01111 -
Selected grayscale Negative V8 V8 - V9 V9 V9 -V10 V10 Positive V23 V23 - V22 V22 V22 - V21 V21
V31
V31 - V30
V30
V30 - V29
V29
V29 - V28 V2 8 V28 - V27 V27 V27 - V26 V26 V26 - V25 V25 V25 - V24 V24 V24 - V23
V10 - V11 V21 - V20 V11 V20
V11 - V12 V20 - V19 V12 V19
V12 - V13 V19 - V18 V13 V18
V13 - V14 V18 - V17 V14 V17
V14 - V15 V17 - V16 V15 V16
V15 - V16 V16 - V15
GRAM Data Setting G 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 R/B 10000 10001 10010 10011 10100 10101 10110 10111 -
Selected grayscale Negative V16 Positive V15
GRAM Data Setting G 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 R/B 11000 11001 11010 11011 11100 11101 11110 11111 -
Selected grayscale Negative V24 Positive V7
V16 - V17 V15 - V14 V17 V14
V24 - V25 V7 - V6 V25 V6
V17 -V18 V14 - V13 V18 V13
V25 -V26 V6 - V5 V26 V5
V18 - V19 V13 - V12 V19 V12
V26 - V27 V5 - V4 V27 V4
V19 - V20 V12 - V11 V20 V11
V27 - V28 V4 - V3 V28 V3
V20 - V21 V11 - V10 V21 V10
V28 - V29 V3 - V2 V29 V2
V21 - V22 V10 - V9 V22 V9
V29 - V30 V2 - V1 V30 V1
V22 - V23 V9 - V8 V23 V8
V30 - V31 V1 - V0 V31 V31 V0 V0
V23 - V24 V8 - V7
Rev.1.10, Jun.21.2003, page 49 of 133
HD66773R Read Data from GRAM (R22h)
R/W R RS 1
RAM Read data (RD17-0) The pin assignment for DB17-0 varies for each interface (see below).
RD15-0: Read 16-bit data from GRAM. The bit assignment for the data to be read out from GRAM is different according to the interface. When data are read out from GRAM to the microcomputer, the first word read immediately after GRAM address set are latched in the internal read-data latch, and the data in the data bus (DB17-0) are nullified. The second word is read as a valid data. When the HD66773R performs an internal bit processing, such as logical operation, it uses the data latched in the read-data latch, and completes it by single read out operation. The data are expanded internally into 18 bits before going through the logical operation. GRAM data read and logical operation are available with 8-/16-bit interface mode. If 9-/18-bit interface modes are selected, this function is not available.
16-bit interface
GRAM data R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Read data
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
Output pin
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
8-bit interface / Interface SPI
GRAM Data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
1 pixel
Read data RD 15 RD 14 RD 13 RD 12 RD 11 RD 10 RD 9 RD 8 RD 7 RD 6 RD 5 RD 4 RD 3 RD 2 RD 1 RD 0
Output pins
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
First transfer (Upper)
Second transfer (lower)
Rev.1.10, Jun.21.2003, page 50 of 133
HD66773R GRAM read sequence
Set I/D, AM, HSA/HSE, VSA/VEA bits
Set I/D, AM, HSA/HSE, VSA/VEA bits
Address: N set
Address: N set
First word
Dummy read (invalid data) GRAM => Read data latch
First word
Dummy read (invalid data) GRAM => Read data latch
Second word
Read (data in address "N") Read data latch => DB17-10 DB8-1
Second word
Write (data in address "N") DB17-10 => GRAM DB8-1
Address: M set
Automatic address update: N+
First word
Dummy read (invalid data) GRAM => Read data latch
First word
Dummy read (invalid data) GRAM => Read data latch
Second word
Read (data in address "M") Read data latch => DB17-10 DB8-1
Second word
Write (data in address "N") DB17-10 => GRAM DB8-1
i) Read data to microcomputer
ii) Logical arithmetic operation inside HD66773R
Rev.1.10, Jun.21.2003, page 51 of 133
HD66773R Gamma Control (R30h to R3Bh)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 PKP 10 PKP 30 PKP 50 PRP 10 PKN 10 PKN 30 PKN 50 PRN 40 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 PKP 00 PKP 20 PKP 40 PRP 00 PKN 00 PKN 20 PKN 40 PRN 00
R30 R31 R32 R33 R34 R35 R36 R37
R3A R3B
W W W W W W W W W W
1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PKP PKP 12 11
Table 29
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PKP PKP 02 01 PKP PKP 22 21 PKP PKP 42 41 PRP PRP 02 01 PKN PKN 02 01 PKN PKN 22 21 PKN 42 PKN 41
PKP PKP 32 31 PKP PKP 52 51 PRP PRP 12 11 PKN PKN 12 11 PKN PKN 32 31 PKN PKN 52 51 PRN PRN 42 41
PRN PRN 02 01
VRP VRP VRP VRP VRP 14 13 12 11 10 VRN VRN VRN VRN VRN 14 13 12 11 10
VRP VRP VRP VRP 03 02 01 00 VRN VRN VRN VRN 03 02 01 00
PKP52-00: Gamma fine adjustment register for the positive polarity output PRP12-00: Gradient adjustment register for the positive polarity output VRP14-00: Amplitude adjustment register for the positive polarity output PKN52-00: Gamma fine adjustment register for the negative polarity output PRN12-00: Gradient adjustment register for the negative polarity output VRN14-00: Amplitude adjustment register for the negative polarity output. For details, see "Gamma Adjustment Function".
Rev.1.10, Jun.21.2003, page 52 of 133
HD66773R
Register Register No. R Index SR Status read Oscillation Start R00h Device code read
R/W RS
0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 PT1 PT0 VLE2 VLE1 SPT 0 0 GON DTE CL REV D1 1 CP15 CP14 CP13 CP12 CP11 CP10 CP9 CP8 CP7 CP6 CP5 CP4 CP3 CP2 CP1 1 DIT 0 0 BGR 0 0 HWM 0 0 0 I/D1 I/D0 AM LG2 LG1 1 CAD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 BT2 BT1 BT0 DC2 DC1 DC0 AP2 AP1 AP0 SLP STB 1 0 0 0 0 FLD1 FLD0 B/C EOR 0 0 NW5 NW4 NW3 NW2 NW1 NW0
Set liquid crystal drive AC waveform (B/C), the number of fields in interlaced drive (FLD1-0), the EOR output (EOR) during C-pattern AC drive, and the number of lines for AC drive "n" (NW5-0). Set tandby mode (STB), LCD power supply ON (AP2-0), sleep mode (SLP), step-up cycle (DC2-0), and step-up output scale (BT3-0).
0 0 1 1 1 0 0 0 0 0 SM GS SS 0 0 0 NL4 NL3 NL2 NL1
IB15 * L7 * 0
IB14 * L6 * 0
IB13 * L5 * 0
Upper Code IB12 IB11 * * L4 L3 * * 0 0 IB10 * L2 * 1 IB9 * L1 * 1 IB8 * L0 * 1 IB7 * 0 * 0 IB6 ID6 0 * 1 IB5 ID5 0 * 1 Lower Code IB4 IB3 IB2 ID4 ID3 ID2 0 0 0 * * * 1 0 0 IB1 ID1 0 * 1 Instructions IB0 ID0 Set index register values. 0 Read out drive line position (L7-0). 1 Start oscillation diring standby. 1 Read out "0773H". Set the gate driver shift direction (GS), source drive shift direction (SS), NL0 and the position of drive line(NL4-0).
Instruction List
R01h
Driver output control
R02h
LCD drive AC control
R03h
Power control (1)
R04h
Power control (2)
Set the structure of holding capacity (CAD).
Set logical operation (LG2-0), AC counter mode (AM), LG0 increment/decrement (I/D1-0), high-speed write mode (HWM), BGR mode, hard-dither mode(DIT).
R05h
Entry mode
Rev.1.10, Jun.21.2003, page 53 of 133
CP0 Set compare registers (CP15-0). Set disply ON (DI1-0), reverse display (REV), display colors (CL), D0 DISPTMG ENABLE (DTE), gate output on (GON), screen split control (SPT), vertical scroll (VLE2-1), and source output state (PT1-0). 0 0 0 0 1 0 0 VCOMG VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 VCM4 VCM3 VCM2 VCM1 VCM0 1 0 0 0 0 VRL3 VRL2 VRL1 VRL0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VC2 VC1 1 NO1 NO0 SDT1 SDT0 EQ1 EQ0 DIV1 DIV0 0 0 0 0 Set 1H period (RTN3-0), operational clock division ratio (DIV1-0), RTN3 RTN2 RTN1 RTN0 Equalize period (EQ1-0), source output delay (SDT1-0), and gete output non-overlap (NO1-0). VC0 Set the Vci adjustment factor (VC2-0).
VREGOUT1 voltage (VRH3-0), and amplifying scale of VREGOUT2 voltage (VRL3-0).
R06h
Compare register
R07h
Display control
R0Bh
Frame cycle control
R0Ch
Power control (3)
R0Dh
Power control (4)
PON VRH3 VRH2 VRH1 VRH0 Start operation of step-up circuit 3 (PON), specify the amplifying scale of
R0Eh
Power control (5)
Set the Vcom H voltage (VCM4-0), the amplitude of Vgoff AC (VDV4-0), and the Vcom voltage (VCOMG). Set the scan start position of gate driver (SCN4-0). Set the screen scroll amount (VL7-0). Set the start /end positions (SS17-10, SE17-10) of the first screen drive. Set the start /end positions (SS27-20, SE27-20) of the second screen drive.
R0Fh R11h R14h R15h R16h R17h R20h R21h
0 VL7 SS17 SS27 HSA7 VSA7 WM7
0 VL6 SS16 SS26 HSA6 VSA6 WM6
0 VL5 SS15 SS25 HSA5 VSA5 WM5
SCN1 VL1 SS11 SS21 HSA1 VSA1 WM1
SCN0 VL0 SS10 SS20 HSA0 VSA0 WM0
R22h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCN4 SCN3 SCN2 VL4 VL3 VL2 SS14 SS13 SS12 SS24 SS23 SS22 HSA4 HSA3 HSA2 VSA4 VSA3 VSA2 WM4 WM3 WM2 AD7-0 (Lower) Write Data (Lower) Read Data (Lower) 0 0 0 0 0 0 0 0 VRP03 VRN03 PKP02 PKP22 PKP42 PRP02 PKN02 PKN22 PKN42 PRN02 VRP02 VRN02 PKP01 PKP21 PKP41 PRP01 PKN01 PKN21 PKN41 PRN01 VRP01 VRN01 PKP00 PKP20 PKP40 PRP00 PKN00 PKN20 PKN40 PRN00 VRP00 VRN00
RAM address start/end positions (HSA7-0, HEA7-0) in holizontal direction. RAM address start/end positions (VSA7-0, VEA7-0) in vertical direction. Set write data mask (WM15-0) for RAM write. Initialize Address Counter with RAM address. Write data to RAM. Read data to RAM. Gamma control. Gamma control. Gamma control. Gamma control. Gamma control. Gamma control. Gamma control. Gamma control. Gamma control. Gamma control.
R30h R31h R32h R33h R34h R35h R36h R37h R3Ah R3Bh
Gate scan starting position vertical scroll control First display drive position Second display drive position Horizontal RAM address position Vertical RAM address position RAM write data mask RAM address set RAM data write RAM data read control (1) control (2) control (3) control (4) control (5) control (6) control (7) control (8) control (9) control (10)
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 1 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 1 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 1 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 1 WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8 AD15-8 (Upper) 1 Write Data (Upper) 1 Read Data (Upper) 1 1 0 0 0 0 0 PKP12 PKP11 PKP10 1 0 0 0 0 0 PKP32 PKP31 PKP30 1 0 0 0 0 0 PKP52 PKP51 PKP50 1 0 0 0 0 0 PRP12 PRP11 PRP10 1 0 0 0 0 0 PKN12 PKN11 PKN10 1 0 0 0 0 0 PKN32 PKN31 PKN30 1 0 0 0 0 0 PKN52 PKN51 PKN50 1 0 0 0 0 0 PRN12 PRN11 PRN10 1 0 0 0 VRP14 VRP13 PRP 12 VRP11 VRP10 1 0 0 0 VRN14 VRN13 VRN 12 VRN11 VRN10
Note1) "*" is "Don't care". Note2) High-speed write mode is available only with RAM write.
HD66773R Reset Function The HD66773R makes internal initial settings with RESET input. During the RESET, the HD66773R is in a busy state, and no instructions from the MPU and access to GRAM are accepted. The time required for the RESET input is at least 1ms. In case of power-on reset, wait at least 10ms after the power is turned on until the R-C oscillation frequency becomes stabilized. While waiting, do not make initial settings for the instruction set, nor access to GRAM. Initial State of Instructions a. b. c. d. e. f. g. h. Start oscillation Driver output control (NL4-0 = "10101", SS = "0", CS = "0") Liquid crystal AC drive control (FLD1-0 = "01", B/C = "0", EOR = "0", NW5-0 = "00000") Power control 1 (BT2-0 = "000", DC2-0 = "000", AP2-0 = "000": liquid crystal power supply off, SLP = "0", STB = "0" : Standby mode off) Power control 2 (CAD = "0") Entry mode set (DIT = "0", BGR = "0", HWM = "0", I/D1-0 = "11": Increment by 1, AM = "0": Horizontal direction, LG2-0 = "000": Replace mode) Compare register (CP15-0 : "0000 0000 0000 0000") Display control (PT1-0 = "00", VLE2-1 = "00": No vertical scroll, SPT = "0", GON = "0", DTE = "0", CL = "0": 262,144 colors, REV = "0", D1-0 = "00": Display OFF) Power control 3 (VC2-0 = "000") Power control 4 (VRL3-0 = "0000", PON = "0", VRH3-0 = "0000") Power control 5 (VDV4-0 = "00000", VCOMG = "0", VCM4-0 = "00000") Frame cycle control (NO1-0 = "00", SDT1-0 = "00", EQ1-0 = "00" : No equalization, DIV1-0 = "00": clock/1, RTN3-0 = "0000" : 16 clocks in 1H period) Gate scan starting position (SCN4-0 = "00000") Vertical scroll (VL7-0 = "00000000") 1st split-screen (SE17-10 = "11111111", SS17-10 = "00000000") 2nd split-screen (SE27-20 = "11111111", SS27-20 = "00000000") Horizontal RAM address position (HEA7-0 = "10000011", HSA7-0 = "00000000") Vertical RAM address position (VEA7-0 = "10101111", VSA7-0 = "00000000") RAM write data mask (WM15-0 = "0000"H: No mask) RAM address set (AD15-0 = "0000"H) control (PKP02-00 = "000", PKP12-10 = "000", PKP22-20 = "000", PKP32-30 = "000", PKP42-40 = "000", PKP52-50 = "000", PRP02-00 = "000", PRP12-10 = "000") (PKN02-00 = "000", PKN12-10 = "000", PKN22-20 = "000", PKN32-30 = "000", PKN42-40 = "000", PKN52-50 = "000", PRN02-00 = "000", PRN12-10 = "000") (VRP14-10 = "00000", VRP03-00 = "0000", VRN14-10 = "00000", VRN12-10 = "000")
i. j. k. l. m. n. o. p. q. r. s. t. u.
GRAM Data Initialization The data in GRAM are not initialized with the RESET input. Initialize through software during the display OFF (D1-0 = "00").
Rev.1.10, Jun.21.2003, page 54 of 133
HD66773R Initial state of output pin a. Liquid crystal driver output pins (source outputs): Output GND level Liquid crystal driver output pins (gate outputs): Output VGH level Oscillator output pin (OSC2): Output oscillation signal
b.
Rev.1.10, Jun.21.2003, page 55 of 133
HD66773R System Interface A system interface is selected among the following interfaces with the IM3-0 pin setting. The system interface enables instruction setting and RAM access.
IM3 0 0 0 0 0 0 1 1 1 1 1 IM2 0 0 0 0 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 0 0 1 1 * IM0 0 1 0 1 * * 0 1 0 1 * MPU-Interface Mode DB Pin
68-system 16-bit interface 68-system 8-bit interface 80-system 16-bit interface 80-system 8-bit interface Serial Peripheral Interface (SPI) Setting inhibited 68-system 18-bit interface 68-system 9-bit interface 80-system 18-bit interface 80-system 9-bit interface Setting inhibited
DB17 to 10, 8-to-1 DB17 to 10 DB17 to 10, 8-to-1 DB17 to 10 DB1 to 0 DB17-0 DB17-9 DB17-0 DB17-9
Rev.1.10, Jun.21.2003, page 56 of 133
HD66773R 18-bit interface 68-system 18-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to Vcc/GND/GND/GND levels respectively. 80-system 18-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to Vcc/GND/Vcc/GND levels respectively. The data transfer through 18-bit mode is effective only for write mode, and not effective for read operation.
18-bit bus interface
CSn* A1 MPU HWR* (RD*) D31 - 0 18 CS* RS WR* (RD*) DB17 - 10 HD66773R
Data format for 18-bit bus interface
Instruction
Input DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 DB 9 DB DB DB DB DB DB DB DB 8 7 6 5 4 3 2 1 DB 0
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 9 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
DB 0
Dither process circuit
HD HD HD HD HD HD HD 17 16 15 14 13 12 11 Shrinking
HD HD HD HD HD HD HD HD HD HD HD 10 9 8 7 6 5 4 3 2 1 0 Shrinking
GRAM write data
R4
R3 R2
R1
R0
G5
G4
G3 G2 1 pixel
G1
G0
B4 B3
B2
B1
B0
Note: 262,144 colocs available with 18-bit system interface by setting DIT bit to "1".
Rev.1.10, Jun.21.2003, page 57 of 133
HD66773R 16-bit interface 68-system 16-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to GND/GND/GND/GND levels respectively. 80-system 16-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to GND/GND/Vcc/GND levels respectively.
16-bit interface
CSn* A1 H8/2245 HWR* (RD*) D15 - 0 16 GND CS* RS WR* (RD*) DB17 - 10, 8-1 DB9, 0 HD66773R
Data format for 16-bit interface Instruction
Input
DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB 1 8 7 6 5 4 3 2
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM Data Write
Input
DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB 8 7 6 5 4 3 2 1
GRAM write data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 15 14 13 12 11 10 0 9 8 7 6 5 4 3 2 1
R,G,B assignment
R4
R3 R2
R1
R0
G5
G4
G3 G2 1 pixel
G1
G0
B4
B3
B2
B1
B0
Note: 65,536-color real display with 16-bit system interface. Do not set DIT bit to "1".
Rev.1.10, Jun.21.2003, page 58 of 133
HD66773R 9-bit interface 68-system 9-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to Vcc/GND/GND/Vcc levels respectively throughDB17-9 pins. 80-system 9-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to Vcc/GND/Vcc/Vcc levels respectively throughDB17-9 pins. The 16-bit instruction is divided into 2 8-bit data and upper 8-bit data is transferred first. The LSB is not used for each upper/lower-bit data transfer. The 18-bit RAM data is also divided into 2 9-bit data and upper 9-bit data is transferred first. The unused pins DB8-0 must be fixed to either "Vcc" or "GND". The upper-byte write is also required when writing index registers. The data transfer through 9-bit mode is effective only for write mode, and not effective for read operation.
9-bit bus interface
CSn* A1 H8/2245 HWR* (RD*) D15 - 0 9 9 GND CS* RS WR* (RD*) DB17 - 9 DB8-0 HD66773R
Data format for 9-bit bus interface
Instruction
Input First transfer (upper) DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 Second transfer (lower) DB DB DB DB DB 9 17 16 15 14 DB DB DB DB DB 13 12 11 10 9
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
Input
First transfer (upper) DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
Second transfer (lower) DB DB DB DB DB 9 17 16 15 14 DB DB DB DB DB 13 12 11 10 9
Dither process HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD circuit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Shrinking Shrinking
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
R,G,B assignment
R4
R3 R2
R1
G3 G2 G1 G0 B4 B3 B2 B1 B0 1 pixel Note: 262,144 colocs available with 9-bit system interface by setting DIT bit to "1".
R0
G5
G4
Rev.1.10, Jun.21.2003, page 59 of 133
HD66773R Data transmission synchronization in 9-bit bus interface mode The HD66773R supports the data transmission synchronizing function, which resets the upper/lower counter that counts the number of transmission of upper/lower 9-bit data in the 9-bit bus interface mode. When a discrepancy occurs in the transmission of upper/lower 9-bit data due to effects from noise and so on, the "00" H instruction is written 4 times consecutively to forcibly reset the upper/lower counter so that data transmission restarts with an upper 9-bit transmission. Periodical execution of the synchronization allows the system recovery from the excursion.
RS RD WR DB17 to DB9
Upper or Lower
"00"H (1)
"00"H (2)
"00"H (3)
"00"H (4)
Upper
Lower
9-bit transfer synchronization
Rev.1.10, Jun.21.2003, page 60 of 133
HD66773R 8-bit interface 68-system 8-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to GND/GND/GND/Vcc levels respectively throughDB17-10 pins. 80-system 8-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to GND/GND/Vcc/Vcc levels respectively throughDB17-10 pins. The 16-bit instruction is divided into 2 8-bit data and upper 8-bit data is transferred first. The LSB is not used for each upper/lower-bit data transfer. The 16-bit RAM data is also divided into 2 8-bit data and upper 9-bit data is transferred first. The unused pins DB9-0 must be fixed to either "Vcc" or "GND". The upper-byte write is also required when writing index registers.
8-bit bus interface
CSn* A1 H8/2245 HWR* (RD*) D15 - 0 8 10 CS* RS WR* (RD*) HD66773R
DB17 - 10 DB9 - 0
GND
Data format for 8-bit bus interface
First transfer (Upper)
Instruction
Input DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
Second transfer (Lowe ) r
DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
First transfer (Upper)
Input DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
Second transfer (Lowe ) r
DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
GRAM write data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R,G,B assignment
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
1 pixel
Note: 65,536-color real display with 8-bit system interface. Do not set DIT bit to "1".
Rev.1.10, Jun.21.2003, page 61 of 133
HD66773R Data transmission synchronization in 8-bit bus interface mode The HD66773R supports the data transmission synchronizing function, which resets the upper/lower counter that counts the number of transmission of upper/lower 8-bit data in the 8-bit bus interface mode. When a discrepancy occurs in the transmission of upper/lower 8-bit data due to effects from noise and so on, the "00" H instruction is written 4 times consecutively to forcibly reset the upper/lower counter so that data transmission restarts with an upper 8-bit transmission. Periodical execution of the synchronization allows the system recovery from the excursion.
RS RD WR DB17 to DB10
Upper or Lower
"00"H (1)
"00"H (2)
"00"H (3)
"00"H (4)
Upper
Lower
8-bit transfer synchronization
Rev.1.10, Jun.21.2003, page 62 of 133
HD66773R Serial Peripheral interface (SPI) The Serial Peripheral Interface (SPI) becomes operable by setting IM3/2/1 pins to GND/Vcc/GND levels respectively. The SPI is available through the chip select line (CS*), serial transfer clock line (SCL), serial data input (SDI), and serial data output (SDO). In the SPI mode, the IM0/ID pin functions as ID pin. In the SPI mode, the unused DB15-2 pins must be fixed at either Vcc or GND level. The HD66773R recognizes the start of data transfer at the falling edge of CS* input to initiate the transfer of a start byte. It recognizes the end of data transfer at the rising edge of CS* input. The HD66773R is selected when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit device identification code assigned to the HD66773R are compared and the both 6-bit data correspond. When selected, the HD66773R starts taking in the subsequent data string. The setting for the least significant bit of the identification code is made with the ID pin. The five upper bits of the identification code must be 01110. Two different chip addresses must be assigned to the HD66789 because the seventh bit of the start byte is assigned to a register select bit (RS). When RS = 0, index register write or status read is executed. When RS = 1, instruction write or RAM read/write is executed. The eighth bit of the start byte is to specify read or write (R/W bit). The data are received when the R/W bit is 0, and are transmitted when the R/W bit is 1. In the SPI mode, the data are written to GRAM after the two-byte data transmission. The data are expanded into 18 bits by adding one bit (the same data as the MSB of RB) next to the LSB of RB data. After receiving the start byte, the HD66773R starts data transmission/reception by byte. The data transmission adopts the format which the MSB is first transmitted. All HD66773R instructions consist of 16 bits and they are executed internally after two bytes are transmitted with the MSB first (DB15 to 0). The data to be written to RAM are expanded into 18-bit data. After the start byte is received, the upper eight bits of the instruction are always fetched as the first byte, and the lower eight bits of the instruction are always fetched as the second byte. The 4-byte data that are read from RAM right after the start byte are made invalid. The HD66773R reads as valid data from the 5th-byte data. Start Byte Format
Transmitted bits Start byte format S Transmission start 1 2 3 4 5 6 7 RS 1 0 ID 8 R/W
Device ID code 0 1 1
Note 1) ID bit is selected with the IM0/ID pin.
RS and R/W Bit Function
RS 0 0 1 1 R/W 0 1 0 1 Function Set index register Read status Write instruction or RAM data Read instruction or RAM data
Rev.1.10, Jun.21.2003, page 63 of 133
HD66773R
Data format for Serial Peripheral Interface
Instruction
Input
1stTransfer (Upper) D7
2nd Transfer(Lower) D8 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
Input
1stTransfer (Upper) D15 D14 D13 D12 D11 D10 D9 D8 D7
2nd Transfer(Lower) D6 D5 D4 D3 D2 D1 D0
GRAM write data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 9 8 7 6 5 4 3 2 1 15 14 13 12 11 10 0
RGB pixel Assignment
R4
R3
R2
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
One pixel
66,536 colors are available in clock synchronized serial interface. Do not set DIT = "1".
Rev.1.10, Jun.21.2003, page 64 of 133
HD66773R
a) Timing Basic Data Transfer through Clock Synchronized Serial Bus Interface
Transfer start
Transfer end
CS* (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCL
(Input) MSB LSB
DB DB DB DB 9 8 7 6 DB DB DB DB DB 5 4 3 2 1 DB 0
SDI
(Input)
"0" "1" "1" "1" "0" ID Devise ID code Start byte
DB DB DB DB DB DB RS RW 15 14 13 12 11 10
RS RW Index register setting, instruction, RAM data wite
DB DB DB DB DB DB 15 14 13 12 11 10 DB DB DB DB 9 8 7 6 DB DB DB DB DB 5 4 3 2 1 DB 0
SDO
(Output)
Status read, instruction read, RAM data read
b) Timing of Consecutive Data-Transfer through Clock-synchronized serial Bus Interface CS*
(Input) 12 345 678 9 10111213141516 1718192021222324 2526272829303132
SCL
(Input)
SDI
(Input) Start
Start byte
Instruction 1: upper eight bits
Instruction 1: lower eight bits
Instruction 2: upper eight bits End
Instruction 1: execution time
Note: The first byte after the start byte is always the upper eight bits.
Rev.1.10, Jun.21.2003, page 65 of 133
HD66773R
c) RAM-Data Read-Transfer Timing CS* (input) SCL (input) SDI (input) SDO (output)
Start byte RS=1, R/W=1 RAM read: RAM read:
upper eight bits lower eight bits
Dummy read 1
Dummy read 2
Dummy read 3
Dummy read 4
Dummy read 5
Start Note: The five-byte data following the start byte are read as invalid data. The HD66773R read the 6th-byte data as normal data.
End 73R
d) Status Read / Instruction Read CS*
(Input)
SCL
(Input)
SDI
(Input)
Start byte RS = 0, R/W = 1
SDO
(Output) Start
Dummy read 1
Status read: upper 8 bits
Status read: lower 8 bits
End
Note: The one-byte data read after the start byte is invalid. The HD6677R starts to read the second-byte data as normal data.
Rev.1.10, Jun.21.2003, page 66 of 133
HD66773R
High-Speed Burst RAM Write Function
The HD66773R incorporates the high-speed burst RAM-write function, which writes data to RAM in onefourth the access time required for the standard RAM-write operation. This function is especially useful for applications which require the high-speed rewrite of the display data such as display of colored moving picture and so on. In high-speed RAM write mode (HWM), data to be written to RAM is temporarily stored to the internal register of HD66773R. The data storage in the register is executed by word. When the data storage operation is executed 4 times, all the data stored in the register is written to RAM at once. While the data is being written from the register to RAM, another set of data is being written to the register. This function enables high-speed and consecutive RAM write, which is required in displaying moving pictures and so on.
a)Operational flow of high-speed consecutive RAM write
Microcomputer
18
Address Address counter counter (AC) AC 16
Register 1
Register 2
Register 3 72
Register 4
"0000"H "0000"H "0001"H
"0002"H "0003"H "0003"H
GRAM
Rev.1.10, Jun.21.2003, page 67 of 133
HD66773R
b) Example of high-speed consecutive RAM write
CS*
(Input) 1 2 3 4 1 2 3 4 1 2 3 4
WR
(Input) Index R22
DB17-0
(Input/output)
RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM data data data data data data data data data data data data 8 1 2 3 4 5 6 7 9 10 11 12
Index
RAM write execution time RAM write data (72 bits) RAM address (AC15-0) "0000"H
RAM wite execution time
RAM write execution time*
RAM data 1 to 4
RAM data 5 to 8
RAM data 9 to 12
"0004"H
"0008"H
"000A"H
* Set the lower two bits of the address as follows in the high-speed write mode. When ID0 = "0", the lower two bits of the address must be set to "11". When ID1 = "0", the lower two bits of the address must be set to "00".
Note: When terminating high-speed RAM write, wait until RAM write execution is completed (tCYC: bus cycle time for nomal RAM write before executing a next instruction.
C) Example of high-speed consecutive RAM write
CS * (input) WR (input) DB17-10 (input/ output) Index R22
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM data data data data data data data data data data data data data data data data (1) (1) (2) (2) (3) (3) (4) (4) (1) (1) (2) (2) (3) (3) (4) (4) Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower RAM write execution time RAM write execution time
RAM write data ( 64-bit ) RAM address ( AC15-0 ) "0000"H
RAM data (1) - (4)
"0004"
RAM data (5) - (8)
* Set the lower two bits of the address as follows in the high-speed write mode. When ID0 = "0", the lower two bits of the address must be set to "11". When ID1 = "0", the lower two bits of the address must be set to "00".
Note: The high-speed burst RAM write function wirtes data to RAM every 4 words. This means in the 8-bit interface mode, RAM write is executed every 8 write operations to the internal register.
Rev.1.10, Jun.21.2003, page 68 of 133
HD66773R Conditions on using high-speed RAM write mode 1. 2. The logical/compare operations are not available. RAM write operation is executed every four words. Set the lower 2 bits of the addresses as follows when setting addresses. *When ID0=0, the lower two bits in the address must be set to 11 before RAM write. *When ID0=1, the lower two bits in the address must be set to 00 before RAM write. 3. RAM write operation is executed every four words. If RAM write operation is terminated before all four-word data is written to RAM, the last data will not be written to RAM. When the index register is set to R22H (RAM data write), the first RAM write operation is always executed. In this case, the RAM data read is not operable simultaneously. During RAM read, set the HWM to 0. The high-speed RAM write mode is not compatible with the normal RAM write mode. When the mode must be switched to the other, make a new address setting before starting RAM write. When writing data in high speed RAM write mode within the range specified with the window address, some window-address range may require dummy write operation. See "High-Speed RAM Write with Window Address Function".
4.
5.
6.
Comparison between Normal and High-Speed RAM Write Operations
Normal RAM Write (HWM=0) Logical operation Compare operation BGR function Write mask function RAM address set RAM read RAM write Window address AM Setting Available in 8-/16-bit interface Available in 8-/16-bit interface Available Available in 8-/16-bit interface Specified by one word Read by one word Write by one word Set by one word AM = 1/0 High-Speed RAM Write (HWM=1) Not available Not available Available Available ID0 bit=0: Set the lower two bits to 11 ID0 bit=1: Set the lower two bits to 00 Not available Some window-address range may require insertion of dummy write Horizontal range(HSA/HSE): 4 word or more Number of horizontal writing : 4N (N>=2) AM = 0
Rev.1.10, Jun.21.2003, page 69 of 133
HD66773R High-Speed RAM Write with Window Address To rewrite the data in an arbitrary rectangular area of RAM consecutively in high speed, the number of RAM access should be made 4 multiple times. Accordingly some window-address range may require dummy write operation to make the RAM access 4 multiple times. The horizontal window-address range specifying bits (HSA1-0, HEA1-0) specify the number of dummy write operations executed at the start and end of the data to be written to RAM. The total RAM access must be 4 multiple times per line. Number of Dummy Write Operations in High-Speed RAM Write (HSA Bits)
HSA1 0 0 1 1 HSA0 0 1 0 1 Number of Dummy Write Operations to be Inserted at the Start of a Row 0 1 2 times 3 times
Number of Dummy Write Operations in High-Speed RAM Write (HEA Bits)
HEA1 0 0 1 1 HEA0 0 1 0 1 Number of Dummy Write Operations to be Inserted at the End of a Row 3 times 2 times 1 time 0
Rev.1.10, Jun.21.2003, page 70 of 133
HD66773R
The number of RAM access when writing data in the horizontal direction must be made 4 x N times by including the dummy writes. Horizontal RAM write = start dummy write + write data + end dummy write = 4 x N (times)
An example of RAM write in high speed RAM write mode with the window address is as follows. The RAM data in the specified window-address range is written over consecutively in high speed by inserting two dummy writes at the start of the line and three dummy writes at the end of the line.
Write in the horizontal direction AM = 0, ID0 = 1
h0000 h0812
GRAM address map
Window address-range setting HSA=h12, HEA=h30 VSA=h08, VEA=hA0
Set high-speed RAM Write mode HWM = 1
Window address Range (Write-over area) hA030
Address set AD = h0810 *See Note Window address-range setting HSA=h12, HEA=h30 VSA=h08, VEA=hA0
hEFAF
Dummy RAM write x 2
RAM write x 31
x 152
*Note: Set the lower two bits of the address as follows in the high-speed write mode. When ID0 = "0", the lower two bits of the address must be set to "11". When ID1 = "0", the lower two bits of the address must be set to "00". The RAM-address range to be overwritten is limited to the area specified with the window address.
Dummy RAM write x 3
Rev.1.10, Jun.21.2003, page 71 of 133
HD66773R
Window Address Function
The window address function enables consecutive data write within the rectangular window-address area on the on-chip GRAM, which is specified with horizontal address registers (start: HSA7-0, end: HEA 7-0) and vertical address registers (start: VSA7-0, end: VEA7-0). The address transition direction is determined with AM bits (either increment or decrement). Accordingly, the data, including picture data, are written consecutively without taking the data wrap position into consideration. The window-address range must be specified within the GRAM address area. An address set must be set within the window-address range. [The condition of setting window-address range] (Horizontal direction) "00"H HSA7-0 HSA7-0 "83"H (Vertical direction) "00"H VSA7-0 VEA7-0 "AF"H [The condition of making an address set within the window-address range] (RAM address) HSA7-0 AD7-0 HEA7-0 VSA7-0 AD15-8 VEA7-0 Note: In high-speed RAM write mode, the lower two bits of the address must be set as follows. ID0=0: The lower two bits of the address must be set to 11. ID0=1: The lower two bits of the address must be set to 00.
GRAM address Map
"0000"H "0083"H
"2010"H "2110"H
"202F"H 212F"H
"5F10"H
"5F2F"H
"AF00"H
"AF83"H
Window address-range specified area HSA7-0 = "10"H HSE7-0 = "2F"H VSA7-0 = "20"H VEA7-0 = "5F"H
I/D = "1" (increment) AM = "0" (horizontal write)
Rev.1.10, Jun.21.2003, page 72 of 133
HD66773R
Graphics Operation Function
The HD66773R significantly reduces the load on the graphics-processing software in the microcomputer. The graphics operation includes: 1. The write data mask function that selectively rewrites some of the 16-bit write data. 2. Logical rewrite function to rewrite data after performing logical operation on the data from the microcomputer and graphics RAM base data. 3. The conditional rewrite function that compares the write data and the compare bit data and writes the data sent from the microcomputer only when the conditions are satisfied. The graphics bit operation is controlled by the setting of bits in the entry mode register and RAM-writedata mask register, and the write operation from the microcomputer. Graphics Operation
Bit Setting Operation Mode Write mode 1 Write mode 2 Write mode 3 Write mode 4 Read/Write mode 1 Read/Write mode 2 Read/Write mode 3 Read/Write mode 4 I/D 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 AM 0 1 0 1 0 1 0 1 LG2-0 000 000 110 111 110 111 001 010 011 001 010 011 100 101 100 101 Operation and Usage Horizontal data replacement, Draw a horizontal line Vertical data replacement, Draw a vertical line Horizontal conditional data replacement, Draw a horizontal line Vertical conditional data replacement Draw a vertical line Horizontal logical write, Draw a horizontal line Vertical logical write, Draw a vertical line Horizontal conditional data replacement, Draw a horizontal line Vertical conditional data replacement Draw a vertical line
Note ) In 18-/9-bit interface modes, only write modes 1, 2 are effective. All operations are effective in 16-/8bit interface modes.
Rev.1.10, Jun.21.2003, page 73 of 133
HD66773R Write-data Mask Function The HD66773R supports write data mask function, which controls GRAM data write by bit when 16-bit data from the microcomputer is being written to GRAM. The write data mask function write data in the bits whose corresponding bits in the write data mask resister (WM15-0) are assigned with "0". It does not write data in the bits whose corresponding bits in the write data mask register (WM15-0) are assigned with "1", and the corresponding data in GRAM are not overwritten but retained. This function is useful when only one-pixel data are rewritten or a particular color in the display is selectively changed.
DB17
Data written by the microcomputer
R04 R03 R02 R01 R00 G05 G04
DB10 DB8
G03 G02 G01 G00 B04 B03 B02 B01
DB1
B00
WM15
Write-data mask
WM0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0
1
DB15 GRAM data
DB0
*
*
*
*
*
G05
G04
G03
G02
G01 G00
*
*
*
*
B00
Note) Write data mask function is available with 8/16-bit system interface.
Rev.1.10, Jun.21.2003, page 74 of 133
HD66773R Graphics Operation Processing 1. Write mode 1: AM = 0, LG2-0 = 000 This mode is used when data are horizontally written in high-speed mode. It is also used to initialize the graphics RAM (GRAM) or to draw a line horizontally. The write-data mask function (WM15-0) is also available in these operations. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and jumps to the counter at the opposing edge of the next one-raster-row below after when the counter reaches either left or right edge of GRAM.
Operation Examples: 1) I/D = "1", AM = "0", LG2-0 = "000" 2) WM15-0 = "07FF"H 3) AC = "0000"H WM15 Write-data mask:
WM0
0 00 00 11 1
DB17 DB10
1 11 11 11 1
DB8 DB1
*Write mask and plains
Write data (1): Write data (2): "0000"H
10 0 11 11 1 11 0 00 00 0
1 00 10 10 0 0 01 10 00 0
"0001"H "0002"H
1 00 11* *** *** ** **
Write data (1)
11 000* * * * * ** * * * *
Write data (2) GRAM
Note : The data in the bit with "*" are not overwritten.
Rev.1.10, Jun.21.2003, page 75 of 133
HD66773R 2. Write mode 2: AM = 1, LG2-0 = 000 This mode is used when data are vertically written in high-speed mode. It is also used to initialize the graphics RAM (GRAM), develop font patterns or draw a line vertically. The write-data mask function (WM15-0) is also available in these operations. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (ID = 1) or the next left row (I/D = 0) according to the setting in the I/D bit, when the address reaches the bottom of GRAM.
1) I/D = "1", AM = "1", LG2-0 = "000" 2) WM15-0 = "07FF"H 3) AC = "0000"H
WM15 Write-data mask: 00000111 DB17 Write data (1): Write data (2): Write data (3): DB10
WM0 11111111 DB8 DB1
10011111 11000000 01111100
10010100 00110000 01000001
"0000"H "0100"H "0200"H
1 0 0 1 1 * * * * * * * * * * * Write data (1) 1 1 0 0 0 * * * * * * * * * * * Write data (2) 0 1 1 1 1 * * * * * * * * * * * Write data (3) GRAM
Note 1) The data in the bit with "*" are not overwritten. Note 2) When data are written to the address "AF00"H, the Address Counter (AC) jumps to "0001"H.
Rev.1.10, Jun.21.2003, page 76 of 133
HD66773R 3. Write mode 3: AM = 0, LG2-0 = 110/111 This mode is used when data are horizontally written with comparing the write data and the value set in the compare register (CP15-0). When the result of the comparison satisfies a condition, the write data sent from the microcomputer are written to GRAM. In this operation, the write-data mask function (WM15-0) is available. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and jumps to the counter at the opposing edge of the next one-raster-row below after when the counter reaches either left or right edge of GRAM.
Operation Examples: 1) I / D = "1", AM = "0", LG2-0 = "110" (matched write) 2) CP15-0 = "2860"H 2) WM15-0 = "0000"H 3) AC = "0000"H WM15 0 00 00 00 0 CP15 Compare register 0 01 0 1000 DB17 Write data (1): WM0 0 00 000 00 CP0 0 11 0 0 0 0 0 DB1 C Conditional replacement R 0 01 01 00 0 0 11 0 0 000 Replacement Compare operation
Write-data mask:
(Matched) DB10 DB8
0 01 0 10 00
01 1 00 00 0
Write data (2):
0 00 0 0111
Conditional Compare operation replacement C R 11 100 000 0
****************
"0000"H
0 0 1 0 1 0 0 0 0 1 10 0 0 0 0 Matched replacement of write data (1)
"0001"H
****************
GRAM
Rev.1.10, Jun.21.2003, page 77 of 133
HD66773R 4. Write mode 4: AM = 1, LG2-0 = 110/111 This mode is used when data are horizontally written with comparing the write data and the value set in the compare register (CP15-0). When the result of the comparison satisfies a condition, the write data sent from the microcomputer are written to GRAM. In this operation, the write-data mask function (WM15-0) is available. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (ID = 1) or the next left row (I/D = 0) according to the setting in the I/D bit, when the address reaches the bottom of GRAM.
Operation Examples: 1) I/D = "1", AM = "1", LG2-0 = "111" (unmatched write) 2) CP15-0 = "2860"H 2) WM15-0 = "0000"H 3) AC = "0000"H WM15 Write-data mask:
00 0 00 00 0
WM0
0 00 00 00 0
CP15 Compare register:
001 01 00 0
CP0
011 0000 0
DB17 Write data (1):
(Unmatched) DB10 DB8
DB1
C
Conditional replacement R Conditional replacement C R **************** 10 0 1 100 1 100 1 1 1 1 1
10 0 11 00 1
1 00 11 11 1
(Matched) Write data (2):
0 0 1 01 0 0 0
Compare operation
0 )1 1 0 0 0 0 0
Compare operation
"0000"H "0000"H "0100"H
10 01 1 001 1 0 0 11 11 1 ************ ****
"0001"H
Write data (1) Write data (2)
"AF00"H
GRAM
Note 1) The data in the bit with "*" are not overwritten. Note 2) When data are written to the address "AF00"H, the Address Counter (AC) jumps to "0001"H.
Rev.1.10, Jun.21.2003, page 78 of 133
HD66773R 5. Read/Write mode 1: AM = 0, LG2-0 = 001/010/011 This mode is used when data are horizontally written in high-speed with performing logical operation on the GRAM data (base data) and data from the microcomputer. The logical operation is performed on the GRAM read-out data and the data sent from the microcomputer, and the result of the logical operation is written to GRAM. In the read operation, the GRAM data is not read out to the microcomputer but retained temporarily in the read-data latch of the HD66773R. Accordingly, the read operation can be performed using the same pulse width with the write-access pulse (68-system: ENABLE "High" level width, 80system: ENABLE "Low" level width), but requires the same bus cycle time as the normal read operation. In this operation, the write-data mask function (WM15-0) is available. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and jumps to the counter at the opposing edge of the next one-raster-row below after when the counter reaches either left or right edge of GRAM.
Operation Examples: 1) I/D = "1", AM = "0", LG2-0 = "001"(OR) 2) WM15-0 = "0000"H 3) AC = "0000"H WM15 Write-data mask: 00 0 00 00 0 DB17 Read data (1): Write data (1): Read data (2): Write data (2): DB10 WM0 0 00 0 0 0 0 0 DB8 DB1
Logical operation(OR)
1 00 11 00 1 1 01 11 10 0 0 00 01 11 1 1 10 0 0 0 1 1
0 10 0 0 00 0 0 11 0 0 00 0 0 00 0 0 0 0 0 1 00 0 0 0 0 0
1 01 11 10 10 11 0 00 00
Logical operation(OR)
11 0 011 1 11 00 0 00 00
"0000"H 10 1 11 10 10 11 00 00 0
Read data (1) + Write data (1)
"0001"H 11 0 011 1 11 00 00 00 0
Read data (2) + Write data (2)
GRAM
Rev.1.10, Jun.21.2003, page 79 of 133
HD66773R 6. Read/Write mode 2: AM = 1, LG2-0 = 110/111 This mode is used when data are vertically written in high-speed with performing logical operation on the GRAM data (base data) and data from the microcomputer. The logical operation is performed on the GRAM read-out data and the data sent from the microcomputer, and the result of the logical operation is written to GRAM. In the read operation, the GRAM data is not read out to the microcomputer but retained temporarily in the read-data latch of the HD66773R. Accordingly, the read operation can be performed using the same pulse width with the write-access pulse (68-system: ENABLE "High" level width, 80system: ENABLE "Low" level width), but requires the same bus cycle time as the normal read operation. In this operation, the write-data mask function (WM15-0) is available. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (ID = 1) or the next left row (I/D = 0) according to the setting in the I/D bit, when the address reaches the bottom of GRAM.
Operation Examples: 1) I / D = "1", AM = "1", 2) WM15-0 = "FFE0"H 3) AC = "0000"H WM15 Write-data mask:
11 1 1111 1
LG2-0 = "001"(OR)
WM0
1 11 00 00 0
DB17 Read data (1): Write data (1):
DB10
DB8
DB1
Logical operation(OR)
1 00 0 1 0 0 1 1 01 1 1 1 0 0
0 10 11 11 1 0 11 00 00 0
10 1 1 1 1 0 1 0 1 1 11111
Read data (2): Write data (2):
0 0 001 11 1
0 00 00 00 0
Logical Operation(OR)
110 00 01 1
10 0 1 1 1 1 1
1 10 0 1 1 1 1 1 0 0 1111 1
"0000"H "0000"H "0100"H
* * * * * * * * * * * 111 1 1 * * * * * * * * * * * 00 00 0
"0001"H
Read data (1) + Write data (1) Read data (2) + Write data (2)
"AF00"H
GRAM
Note 1) The data in the bit with "*" are not overwritten. Note 2) When data are written to the address "AF00"H, the Address Counter (AC) jumps to "0001"H.
Rev.1.10, Jun.21.2003, page 80 of 133
HD66773R 7. Read/Write mode 3: AM = 0, LG2-0 = 100/101 This mode is used when data are horizontally written in high-speed with performing compare operation on the GRAM data (base data) and the value set in the compare register (CP15-0). The compare operation is performed on the GRAM read-out data and the value set in the compare register by word. When the result of the comparison satisfies a condition, the data sent from the microcomputer are written to GRAM. In the read operation, the GRAM data is not read out to the microcomputer but retained temporarily in the readdata latch of the HD66773R. Accordingly, the read operation can be performed using the same pulse width with the write-access pulse (68-system: ENABLE "High" level width, 80-system: ENABLE "Low" level width), but requires the same bus cycle time as the normal read operation. In this operation, the write-data mask function (WM15-0) is available. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and jumps to the counter at the opposing edge of the next oneraster-row below after when the counter reaches either left or right edge of GRAM.
Operation Examples: 1) I/D = "1", AM = "0", LG2-0 = "100" (matched write) 2) CP15-0 = "2860"H 2) WM15-0 = "0000"H 3) AC = "0000"H WM15 Write-data mask:
00 0 00 00 0
WM0
0 00 00 00 0
CP15 Compare register:
00 1 01 00 0
CP0
0 11 00 00 0
Compare Operation
Matched DB17 Read data (1): DB10 DB8
DB1 C Conditional replacement R
10 1 11 10 00 11 00 00 0
00 1 01 00 0 10 1 11 10 0
0 11 00 00 0 0 11 00 00 0
Write data (1):
Compare operation
Read data (2):
00 0 01 11 1
00000 00 0
C
Conditional replacement R 0 00 01 11 10 00 00 00 0
Write data (2):
11 00 00 11
10 000 00 0
"0000"H
10 1 11 10 00 11 0 00 00
Matched replacement write data (1)
"0001"H
0 00 01 11 10 00 00 00 0
GRAM
Rev.1.10, Jun.21.2003, page 81 of 133
HD66773R 8. Read/Write mode 4: AM = 1, LG2-0 = 100/101 This mode is used when data are vertically written in high-speed with performing compare operation on the GRAM data (base data) and the value set in the compare register (CP15-0). The compare operation is performed on the GRAM read-out data and the value set in the compare register by word. When the result of the comparison satisfies a condition, the data sent from the microcomputer are written to GRAM. In the read operation, the GRAM data is not read out to the microcomputer but retained temporarily in the readdata latch of the HD66773R. Accordingly, the read operation can be performed using the same pulse width with the write-access pulse (68-system: ENABLE "High" level width, 80-system: ENABLE "Low" level width), but requires the same bus cycle time as the normal read operation. In this operation, the write-data mask function (WM15-0) is available. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (ID = 1) or the next left row (I/D = 0) according to the setting in the I/D bit, when the address reaches the bottom of GRAM.
Operation Examples:
1) I / D = "1", AM = "1", LG2-0 = "101" (unmatched write) 2) CP15-0 = "2860"H 2) WM15-0 = "0000"H 3) AC = "0000"H WM15 Write-data mask:
00 0 00 00 0
WM0
0 00 00 00 0
CP15 Compare register:
00 1 01 00 0
CP0 Compare operation 01100000 DB1 C Conditional replacement R
10 1 11 10 00 11 00 00 0
DB17 Read data (1):
Unmatched DB10 DB8
10 0 11 00 1
0 10 11 11 1
Matched Write data (1):
10 1 11 10 0 0 11 00 00 0 Compare operation 0 11 0 00 00
Read data (2):
00 1 01 00 0
C
Conditional replacement R 00 1 01 00 00 11 0 00 00
Write data (2):
11 00 00 11
10 000 00 0
"0000"H "0000"H "0100"H
10 1 11 10 00 11 0 00 00
"0001"H
Write data (1) Write data (2)
00 1 01 00 00 11 0 00 00
GRAM
"AF00"H
Note 1) The data in the bit with "*" are not overwritten. Note 2) When data are written to the address "AF00"H, the Address Counter (AC) jumps to "0001"H.
Rev.1.10, Jun.21.2003, page 82 of 133
HD66773R
Scan Mode Setting
The shift direction of gate signal is changeable by the combination of SM and GS bit settings. This allows various ways of connecting a liquid crystal panel and the HD66773R.
SM
GS
Odd line G1
Scan direction
G2 Even line
TFT Panel
0
0
G175 G1 G175 G176 G176 G2
G1 G2 G3 G4 *** G173 G174 G175 G176
HD66773R
Odd line
G1
G2
Even line
TFT Panel
0
1
G175 G1 G175 G176 G176 G2
G176 G175 G174 173 *** G4 G3 G2 G1
HD66773R
G1
TFT Panel
G175
1
0
G2
G176 G1 G175 G176 G2
G1 G5 G2 G6
G3 *** G173 G175 G4 *** G174 G176
HD66773R
G1 TFT Panel G175
1
1
G2
G176 G1 G175 G176 G2
G176 G172 G175 G171
G174 *** G4 G173 *** G3
G2 G1
HD66773R
Rev.1.10, Jun.21.2003, page 83 of 133
HD66773R
-Correction Function
The HD66773R incorporates -correction function to simultaneously display 262,144 colors, by which 8level grayscale is determined by the gradient-adjustment and fine-adjustment registers. Select either positive or negative polarity of the registers according to the characteristics of a liquid crystal panel.
MSB
Graphics RAM (GRAM)
LSB
Display data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
Data expansion circui t
R5 R4 R3 R2 R1 R0
Data expansion circui t
B5 B4 B3 B2 B1 B0
PKP 02 PKP 12 PKP 22
PKP 01 PKP 11 PKP 21 PKP 31 PKP 41 PKP 51 PRP 01 PRP 11 VRP01 VRP11
PKP 00 PKP 10 PKP 20 PKP 30 PKP 40 PKP 50 PRP 00 PRP 10 VRP00 VRP10
Positive polarity register
PKP 32 PKP 42 PKP 52 PRP 02 PRP 12 VRP03 VRP02 VRP12
V0 V1 8
Grayscale amplifier
6
6
6
32
32 grayscale control 32 grayscale control 32 grayscale control
VRP14
VRP13
FRC control
V31
PKN 02 PKN 12 PKN 22 PKN 32 PKN 01 PKN 11 PKN 21 PKN 31 PKN 41 PKN 51 PRN01 PRN11 VRN01 VRN11 PKN 00 PKN 10 PKN 20 PKN 30 PKN 40 PKN 50 PRN00 PRN10 VRN00 VRN10
FRC control
LCD driver
FRC control
LCD driver
LCD driver
Nagative polarity register
PKN 42 PKN 52 PRN02 PRN12 VRN03 VRN02 VRN12
RGB
LCD
VRN14
VRN13
Note 1) 16-bit RAM data is expanded into 18-bit data through data expansion circuit.
Rev.1.10, Jun.21.2003, page 84 of 133
HD66773R Configuration of Grayscale Amplifier The gradient adjustment and fine adjustment registers determine the eight levels (VIN0-7) of grayscale. The 8 levels are then divided into 32 levels (V0-31) by the ladder resistors placed between each level.
Gradient adjustment register
Micro adjustment register (6 x 3 bits)
PKP/N0 PKP/N1 PKP/N2 PKP/N3 PKP/N4 PKP/N5
Amplitude adjustment register VRP/VRN
VREG1OUT
PRP/N0 PRP/N1
3
3
3
3
3
3
3
3
4
5
VINP0/VINN0
V0
VINP1/VINN1
8to1
selector
V1 V2 V3
VINP2/VINN2
8to1
selector
V8 V9
VINP3/VINN3
8to1
selector
V16
Grayscale amplifier
V17 V19 V20
Ladder resistor
VINP4/VINN4
8to1
selector
VINP5/VINN5
8to1
selector
V24 V25 V26
VINP6/VINN6
8to1
selector
V30
VINP7/VINN7
V31
VGS
Rev.1.10, Jun.21.2003, page 85 of 133
HD66773R
VREG1OUT
VRN0 0 to 30R KVP0 5R RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 PRP0[2:0] RP8 RP9 1R RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RP32 RP33 RP34 RP35 RP36 RP37 RP38 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 PRP1[2:0] RP39 RP40 RP41 RP42 RP43 RP44 RP45 RP46 KVP49 VRP1 0 to 31R 8R EXVR RP47 VRP1[4:0] VINP7 VRN1 0 to 31R 8R RN47 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 VINP0 PKP0[2:0] 5R RN0 RN1 RN2 RN3 RN4 RN5 RN6 RN7 KVN1 KVN2 KVN3 KVN4 8 to 1 KVN5 SEL KVN6 KVN7 KVN8 PRN0[2:0] RN8 RN9 RN10 RN11 RN12 RN13 RN14 RN15 RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN31 RN32 RN33 RN34 RN35 RN36 RN37 RN38 KVN33 KVN34 KVN35 KVN36 8 to 1 KVN37 SEL KVN38 KVN39 KVN40 PRN1[2:0] RN39 RN40 RN41 RN42 RN43 RN44 RN45 RN46 KVN49 VRN1[4:0] VINN7 KVN41 KVN42 KVN43 KVN44 8 to 1 KVN45 SEL KVN46 KVN47 KVN48 KVN25 KVN26 KVN27 KVN28 8 to 1 KVN29 SEL KVN30 KVN31 KVN32 KVN17 KVN18 KVN19 KVN20 8 to 1 KVN21 SEL KVN22 KVN23 KVN24 KVN9 KVN10 KVN11 KVN12 8 to 1 KVN13 SEL KVN14 KVN15 KVN16
VRP0 0 to 30R
VRP0[3:0]
VRN0[3:0] KVN0 VINN0 PKN0[2:0]
4R
8 to 1 SEL
VINP1
4R
VINN1
VRHP 0 to2 8R
PKP1[2:0]
VRHN 0 to 28R
PKN1[2:0]
8 to 1 SEL
VINP2
1R
VINN2
5R
PKP2[2:0]
5R
PKN2[2:0]
1R
8 to 1 SEL
VINP3
1R
VINN3
16R
PKP3[2:0]
16R
PKN3[2:0]
1R
8 to 1 SEL
VINP4
1R
VINN4
5R
PKP4[2:0]
5R
PKN4[2:0]
1R
8 to 1 SEL
VINP5
1R
VINN5
VRLP 0 to 28R
PKP5[2:0]
VRLN 0 to 28R
PKN5[2:0]
4R
8 to 1 SEL
VINP6
4R
VINN6
5R
5R
Ladder Resistors and 8-to-1 Selectors
Rev.1.10, Jun.21.2003, page 86 of 133
HD66773R -Correction Register The -adjustment register is a group of registers to set an appropriate grayscale voltage for the characteristics of a liquid crystal panel. The register group is categorized into the ones adjusting gradient, amplitude, and fine-tuning in relation to grayscale number and voltage characteristics. Each register can make an independent setting for the positive/negative polarity. The reference value and RGB are common for all registers.
Grayscale Voltage
Grayscale Voltage
Grayscale Voltage
Grayscale Number
Grayscale Number
Grayscale Number
Gradient Adjustment
Amplitude Adjustment
Fine Adjustment
-Correction Register 1. Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient around the middle of the grayscale number and voltage characteristics without changing the dynamic range. To adjust a gradient, the values of the variable resistors (VRHP (N)/VRL (N)) in the middle of the ladder resistor block for grayscale voltage generation are controlled. The registers incorporate separate registers for positive and negative polarities to be compatible with asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. To adjust the amplitude, the values of the variable resistor (VRP(N)1/0) located at the lower side of the ladder resistor block for grayscale voltage generation are adjusted. The variable resistor located at the upper side of the ladder resistor block is adjusted by the input VDH level or reference resistor. Same with the gradient registers, the registers also incorporate separate registers for positive and negative polarities. 3. Fine adjustment registers The fine adjustment register is to fine-adjust the grayscale voltage level. To fine-adjust the grayscale voltage level, each level of 8-level reference voltages generated from the ladder registers is controlled by 8to-1 selector. Same with the other registers, the registers also incorporate separate registers for positive and negative polarities.
Rev.1.10, Jun.21.2003, page 87 of 133
HD66773R -Correction Registers
Register Groups Gradient adjustment Amplitude adjustment Fine adjustment Positive Polarity PRP0 2 to 0 PRP1 2 to 0 VRP0 3 to 0 VRP1 4 to 0 PKP0 2 to 0 PKP1 2 to 0 PKP2 2 to 0 PKP3 2 to 0 PKP4 2 to 0 PKP5 2 to 0 Negative Polarity PRN0 2 to 0 PRN1 2 to 0 VRN0 3 to 0 VRN1 4 to 0 PKN0 2 to 0 PKN1 2 to 0 PKN2 2 to 0 PKN3 2 to 0 PKN4 2 to 0 PKN5 2 to 0 Description Variable resistor VRHP (N) Variable resistor VRLP (N) Variable resistor VRP (N)0 Variable resistor VRP (N)1 8-to-1 selector (voltage level of grayscale 1) 8-to-1 selector (voltage level of grayscale 8) 8-to-1 selector (voltage level of grayscale 20) 8-to-1 selector (voltage level of grayscale 43) 8-to-1 selector (voltage level of grayscale 55) 8-to-1 selector (voltage level of grayscale 62)
Ladder resistors and 8-to-1 selector Block configuration The block diagram of page 86 consists of two ladder resistors including variable resistors, and 8-to-1 selectors which select the voltage generated by the ladder resistors to output a reference voltage for the grayscale voltage. The variable resistors and the 8-to-1 selectors are controlled by the correction register. Pins to be connected to a variable resistor are provided to compensate the variation among the panels. Variable resistor There are two kinds of variable resistors for the gradient adjustment (VRHP(N)/VRLP(N)) and the amplitude adjustment (VRP(N)0/ VRP(N)1). The resistance is determined by the gradient adjustment and amplitude adjustment registers as is shown below. Gradient adjustment (1)
Register value PRP(N)0[2:0] Resistance VRHP(N)
Gradient adjustment (2)
Register value PRP(N)1[2:0] Resistance VRLP(N)
000 001 010 011 100 101 110 111
0R 4R 8R 12R 16R 20R 24R 28R
000 001 010 011 100 101 110 111
0R 4R 8R 12R 16R 20R 24R 28R
Rev.1.10, Jun.21.2003, page 88 of 133
HD66773R Amplitude adjustment (1)
Register value VRP(N)0[3:0] Resistance VRP(N)0
Amplitude adjustment (2)
Register value VRP(N)1[4:0] Resistance VRP(N)1
0000 0001 0010 * * * * 1101 1111 1111
0R 2R 4R * * * * 26R 28R 30R
00000 00001 00010 * * * * 11101 11110 11111
0R 1R 2R * * * * 29R 30R 31R
8-to-1 selector The 8-to-1 selectors select a voltage level generated by the ladder resistors according to the fine adjustment registers, and output six kinds of reference voltage, VIN1 to VIN 6. The relationship between the fine adjustment register and the selected voltage is as follows. Fine adjustment registers and selected voltage
The value of Register PKP(N)[2:0] 000 001 010 011 100 101 110 111 Selected Voltage VINP(N)1 KVP(N)1 KVP(N)2 KVP(N)3 KVP(N)4 KVP(N)5 KVP(N)6 KVP(N)7 KVP(N)8 VINP(N)2 KVP(N)9 KVP(N)10 KVP(N)11 KVP(N)12 KVP(N)13 KVP(N)14 KVP(N)15 KVP(N)16 VINP(N)3 KVP(N)17 KVP(N)18 KVP(N)19 KVP(N)20 KVP(N)21 KVP(N)22 KVP(N)23 KVP(N)24 VINP(N)4 KVP(N)25 KVP(N)26 KVP(N)27 KVP(N)28 KVP(N)29 KVP(N)30 KVP(N)31 KVP(N)32 VINP(N)5 KVP(N)33 KVP(N)34 KVP(N)35 KVP(N)36 KVP(N)37 KVP(N)38 KVP(N)39 KVP(N)40 VINP(N)6 KVP(N)41 KVP(N)42 KVP(N)43 KVP(N)44 KVP(N)45 KVP(N)46 KVP(N)47 KVP(N)48
Rev.1.10, Jun.21.2003, page 89 of 133
HD66773R The grayscale levels (V0-V31) are calculated according to the following formulas. Formulas for calculating voltage (Positive polarity) (1)
Micro-adjsting register value PKP02-00 = "000" PKP02-00 = "001" PKP02-00 = "010" PKP02-00 = "011" PKP02-00 = "100" PKP02-00 = "101" PKP02-00 = "110" PKP02-00 = "111" PKP12-10 = "000" PKP12-10 = "001" PKP12-10 = "010" PKP12-10 = "011" PKP12-10 = "100" PKP12-10 = "101" PKP12-10 = "110" PKP12-10 = "111" PKP22-20 = "000" PKP22-20 = "001" PKP22-20 = "010" PKP22-20 = "011" PKP22-20 = "100" PKP22-20 = "101" PKP22-20 = "110" PKP22-20 = "111" PKP32-30 = "000" PKP32-30 = "001" PKP32-30 = "010" PKP32-30 = "011" PKP32-30 = "100" PKP32-30 = "101" PKP32-30 = "110" PKP32-30 = "111" PKP42-00 = "000" PKP42-40 = "001" PKP42-40 = "010" PKP42-40 = "011" PKP42-40 = "100" PKP42-40 = "101" PKP42-40 = "110" PKP42-40 = "111" PKP52-50 = "000" PKP52-50 = "001" PKP52-50 = "010" PKP52-50 = "011" PKP52-50 = "100" PKP52-50 = "101" PKP52-50 = "110" PKP52-50 = "111" Reference voltage VINP0
Pins KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49
Formula VREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTV*VRP0/SUMRP V*(VRP0+5R)/SUMRP V*(VRP0+9R)/SUMRP V*(VRP0+13R)/SUMRP V*(VRP0+17R)/SUMRP V*(VRP0+21R)/SUMRP V*(VRP0+25R)/SUMRP V*(VRP0+29R)/SUMRP V*(VRP0+33R)/SUMRP V*(VRP0+33R+VRHP)/SUMRP V*(VRP0+34R+VRHP)/SUMRP V*(VRP0+35R+VRHP)/SUMRP V*(VRP0+36R+VRHP)/SUMRP V*(VRP0+37R+VRHP)/SUMRP V*(VRP0+38R+VRHP)/SUMRP V*(VRP0+39R+VRHP)/SUMRP V*(VRP0+40R+VRHP)/SUMRP V*(VRP0+45R+VRHP)/SUMRP V*(VRP0+46R+VRHP)/SUMRP V*(VRP0+47R+VRHP)/SUMRP V*(VRP0+48R+VRHP)/SUMRP V*(VRP0+49R+VRHP)/SUMRP V*(VRP0+50R+VRHP)/SUMRP V*(VRP0+51R+VRHP)/SUMRP V*(VRP0+52R+VRHP)/SUMRP V*(VRP0+68R+VRHP)/SUMRP V*(VRP0+69R+VRHP)/SUMRP V*(VRP0+70R+VRHP)/SUMRP V*(VRP0+71R+VRHP)/SUMRP V*(VRP0+72R+VRHP)/SUMRP V*(VRP0+73R+VRHP)/SUMRP V*(VRP0+74R+VRHP)/SUMRP V*(VRP0+75R+VRHP)/SUMRP V*(VRP0+80R+VRHP)/SUMRP V*(VRP0+81R+VRHP)/SUMRP V*(VRP0+82R+VRHP)/SUMRP V*(VRP0+83R+VRHP)/SUMRP V*(VRP0+84R+VRHP)/SUMRP V*(VRP0+85R+VRHP)/SUMRP V*(VRP0+86R+VRHP)/SUMRP V*(VRP0+87R+VRHP)/SUMRP V*(VRP0+87R+VRHP+VRLP)/SUMRP V*(VRP0+91R+VRHP+VRLP)/SUMRP V*(VRP0+95R+VRHP+VRLP)/SUMRP V*(VRP0+99R+VRHP+VRLP)/SUMRP V*(VRP0+103R+VRHP+VRLP)/SUMRP V*(VRP0+107R+VRHP+VRLP)/SUMRP V*(VRP0+111R+VRHP+VRLP)/SUMRP V*(VRP0+115R+VRHP+VRLP)/SUMRP V*(VRP0+120R+VRHP+VRLP)/SUMRP
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
SUMRP: Total of the positive-polarity ladder resistors = 128 R + VRHP + VRLP + VRP0 + VRP1 SUMRN: Total of the negative-polarity ladder resistors = 128 R + VRHN + VRLN + VRN0 + VRN1 V: Voltage difference between VREG1OUT - VGS
Rev.1.10, Jun.21.2003, page 90 of 133
HD66773R Formulas for calculating voltage (Positive polarity) (2)
grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20
V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31
Formula VINP0 V3D+(VINP1-V3D)*(8/24) V4+(V3D-V4)*(16/24) V4+(V3D-V4)*(8/24) VINP2 V10+(V4-V10)*(20/24) V10+(V4-V10)*(16/24) V10+(V4-V10)*(12/24) V10+(V4-V10)*(8/24) V10+(V4-V10)*(4/24) VINP3 V21+(V10-V21)*(21/24) V21+(V10-V21)*(19/24) V21+(V10-V21)*(17/24) V21+(V10-V21)*(15/24) V21+(V10-V21)*(13/24) V21+(V10-V21)*(11/24) V21+(V10-V21)*(9/24) V21+(V10-V21)*(7/24) V21+(V10-V21)*(5/24) V21+(V10-V21)*(3/24)
VINP4 V27+(V21-V27)*(20/24) V27+(V21-V27)*(16/24) V27+(V21-V27)*(12/24) V27+(V21-V27)*(8/24) V27+(V21-V27)*(4/24) VINP5 VINP6+(V27-VINP6)*(780/960) VINP6+(V27-VINP6)*(600/960) VINP6+(V27-VINP6)*(280/960) VINP7
V3D: V3D = V4+(VINP1-V4)*(540/960)
Rev.1.10, Jun.21.2003, page 91 of 133
HD66773R Formulas for calculating voltage (Negative polarity) (1)
Table 40 Voltage Formula: Negative Polarity Pins Formula KVN0 KVN1 KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 KVN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16 KVN17 KVN18 KVN19 KVN20 KVN21 KVN22 KVN23 KVN24 KVN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32 KVN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40 KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 KVN49 VREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTVREG1OUTV*VRN0/SUMRN V*(VRN0+5R)/SUMRN V*(VRN0+9R)/SUMRN V*(VRN0+13R)/SUMRN V*(VRN0+17R)/SUMRN V*(VRN0+21R)/SUMRN V*(VRN0+25R)/SUMRN V*(VRN0+29R)/SUMRN V*(VRN0+33R)/SUMRN V*(VRN0+33R+VRHN)/SUMRN V*(VRN0+34R+VRHN)/SUMRN V*(VRN0+35R+VRHN)/SUMRN V*(VRN0+36R+VRHN)/SUMRN V*(VRN0+37R+VRHN)/SUMRN V*(VRN0+38R+VRHN)/SUMRN V*(VRN0+39R+VRHN)/SUMRN V*(VRN0+40R+VRHN)/SUMRN V*(VRN0+45R+VRHN)/SUMRN V*(VRN0+46R+VRHN)/SUMRN V*(VRN0+47R+VRHN)/SUMRN V*(VRN0+48R+VRHN)/SUMRN V*(VRN0+49R+VRHN)/SUMRN V*(VRN0+50R+VRHN)/SUMRN V*(VRN0+51R+VRHN)/SUMRN V*(VRN0+52R+VRHN)/SUMRN V*(VRN0+68R+VRHN)/SUMRN V*(VRN0+69R+VRHN)/SUMRN V*(VRN0+70R+VRHN)/SUMRN V*(VRN0+71R+VRHN)/SUMRN V*(VRN0+72R+VRHN)/SUMRN V*(VRN0+73R+VRHN)/SUMRN V*(VRN0+74R+VRHN)/SUMRN V*(VRN0+75R+VRHN)/SUMRN V*(VRN0+80R+VRHN)/SUMRN V*(VRN0+81R+VRHN)/SUMRN V*(VRN0+82R+VRHN)/SUMRN V*(VRN0+83R+VRHN)/SUMRN V*(VRN0+84R+VRHN)/SUMRN V*(VRN0+85R+VRHN)/SUMRN V*(VRN0+86R+VRHN)/SUMRN V*(VRN0+87R+VRHN)/SUMRN V*(VRN0+87R+VRHN+VRLN)/SUMRN V*(VRN0+91R+VRHN+VRLN)/SUMRN V*(VRN0+95R+VRHN+VRLN)/SUMRN V*(VRN0+99R+VRHN+VRLN)/SUMRN V*(VRN0+103R+VRHN+VRLN)/SUMRN V*(VRN0+107R+VRHN+VRLN)/SUMRN V*(VRN0+111R+VRHN+VRLN)/SUMRN V*(VRN0+115R+VRHN+VRLN)/SUMRN V*(VRN0+120R+VRHN+VRLN)/SUMRN
Micro-adjsting register value PKN02-00 = "000" PKN02-00 = "001" PKN02-00 = "010" PKN02-00 = "011" PKN02-00 = "100" PKN02-00 = "101" PKN02-00 = "110" PKN02-00 = "111" PKN12-10 = "000" PKN12-10 = "001" PKN12-10 = "010" PKN12-10 = "011" PKN12-10 = "100" PKN12-10 = "101" PKN12-10 = "110" PKN12-10 = "111" PKN22-20 = "000" PKN22-20 = "001" PKN22-20 = "010" PKN22-20 = "011" PKN22-20 = "100" PKN22-20 = "101" PKN22-20 = "110" PKN22-20 = "111" PKN32-30 = "000" PKN32-30 = "001" PKN32-30 = "010" PKN32-30 = "011" PKN32-30 = "100" PKN32-30 = "101" PKN32-30 = "110" PKN32-30 = "111" PKN42-00 = "000" PKN42-00 = "001" PKN42-00 = "010" PKN42-00 = "011" PKN42-00 = "100" PKN42-00 = "101" PKN42-00 = "110" PKN42-00 = "111" PKN52-50 = "000" PKN52-50 = "001" PKN52-50 = "010" PKN52-50 = "011" PKN52-50 = "100" PKN52-50 = "101" PKN52-50 = "110" PKN52-50 = "111" -
Reference voltage VINN0
VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
SUMRP: Total of the positive-polarity ladder resistors = 128 R + VRHP + VRLP + VRP0 + VRP1 SUMRN: Total of the negative-polarity ladder resistors = 128 R + VRHN + VRLN + VRN0 + VRN1 V: Voltage difference between VREG1OUT - VGS
Rev.1.10, Jun.21.2003, page 92 of 133
HD66773R Formulas for calculating voltage (Negative polarity) (2)
grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 Formula VINN0 V3D+(VINN1-V3D)*(8/24) V4+(V3D-V4)*(16/24) V4+(V3D-V4)*(8/24) VINN2 V10+(V4-V10)*(20/24) V10+(V4-V10)*(16/24) V10+(V4-V10)*(12/24) V10+(V4-V10)*(8/24) V10+(V4-V10)*(4/24) VINN3 V21+(V10-V21)*(21/24) V21+(V10-V21)*(19/24) V21+(V10-V21)*(17/24) V21+(V10-V21)*(15/24) V21+(V10-V21)*(13/24) V21+(V10-V21)*(11/24) V21+(V10-V21)*(9/24) V21+(V10-V21)*(7/24) V21+(V10-V21)*(5/24) V21+(V10-V21)*(3/24)
V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31
VINN4 V27+(V21-V27)*(20/24) V27+(V21-V27)*(16/24) V27+(V21-V27)*(12/24) V27+(V21-V27)*(8/24) V27+(V21-V27)*(4/24) VINN5 VINN6+(V27-VINN6)*(780/960) VINN6+(V27-VINN6)*(600/960) VINN6+(V27-VINN6)*(280/960) VINN7
V3D: V3D = V4+(VINN1-V4)*(540/960)
Rev.1.10, Jun.21.2003, page 93 of 133
HD66773R Relationship between RAM data and output level The relationship between the RAM data and the source output level is as follows.
Relationship between RAM data and source output level
V0
Negative Polarity
Output Level
Positive Polarity
V31
G pixel data 000000 R,B pixel data 00000
RAM Data
Relationship between Vcom and source output level
Sn
Negative Polarity
Vcom
Positive Polarity
Rev.1.10, Jun.21.2003, page 94 of 133
G pixel data 111111 R,B pixel data 11111
HD66773R
8-color Display Mode
The HD66773R incorporates 8-color display mode. The available grayscale levels are V0 and V31, and the voltages for the other levels (V1-V30) are halted to reduce power consumption. The -fine-adjustment registers, PKP0-PKP5 and PKN0-PKN5 are not available in the 8-color display mode. Since the power supply for the levels V1-V30 are halted, R and B data in GRAM should be set to either "00000" or "11111" and G data in GRAM to either "000000" or "111111" before setting this mode so that V0 or V31 is selected.
MSB
Graphics RAM (GRAM)
LSB
Display data
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
Data expansion circuit
R5
PKP 02 PKP 12 PKP 22 PKP 32 PKP 01 PKP 11 PKP 21 PKP 31 PKP 41 PKP 51 PRP 01 PRP 11 VRP01 VRP11 PKP 00 PKP 10 PKP 20 PKP 30
Data expansion circuit
R0 B5 B4 B3 B2 B1 B0
R4
R3
R2
R1
Positive polarity register
V0
PKP 42 PKP 52 PRP 02 PRP 12 VRP03 VRP02 VRP12 PKP 40 PKP 50 PRP 00 PRP 10 VRP00 VRP10
6 8
Grayscale amplifier
6
2 grayscale control
6
2 grayscale control
2
2 grayscale control
V31 LCD driver
LCD driver
LCD driver
VRP14
VRP13
PKN 02 PKN 12 PKN 22 PKN 32
PKN 01 PKN 11 PKN 21 PKN 31 PKN 41 PKN 51 PRN01 PRN11 VRN01 VRN11
PKN 00 PKN 10 PKN 20 PKN 30 PKN 40 PKN 50 PRN00 PRN10 VRN00 VRN10
Nagative polarity register
PKN 42 PKN 52 PRN02 PRN12 VRN03 VRN02 VRN12
RGB
LCD
VRN14
VRN13
Rev.1.10, Jun.21.2003, page 95 of 133
HD66773R To switch between the 262, 144-color mode and the 8-color mode, make settings according to the following sequences.
262,144 colors 8 colors 8 colors 262,144 colors
Display OFF GON = "1" DTE = "1" D1-0 = "10", DIT = "0"
Wait (2 frame or more)
Display OFF GON = "1" DTE = "1" D1-0 = "10", DIT = "1"
Wait (2 frame or more)
Display OFF GON = "1" DTE = "0" D1-0 = "10", DIT = "0"
Wait (2 frame or more)
Display OFF GON = "1" DTE = "0" D1-0 = "10", DIT = "1"
Wait (2 frame or more)
Display OFF GON = "0" DTE = "0" D1-0 = "00", DIT = "0"
Display OFF GON = "0" DTE = "0" D1-0 = "00", DIT = "1"
RAM setting Cl = "1"
RAM setting Cl = "0"
Wait (40ms or more)
Wait (40ms or more)
Display OFF GON = "0" DTE = "0" D1-0 = "01", DIT = "0"
Wait (2 frame or more)
Display OFF GON = "0" DTE = "0" D1-0 = "01", DIT = "1"
Wait (2 frame or more)
Display OFF GON = "1" DTE = "0" D1-0 = "01", DIT = "0" Display OFF GON = "1" DTE = "0" D1-0 = "11", DIT = "0"
Display OFF GON = "1" DTE = "0" D1-0 = "01", DIT = "1" Display OFF GON = "1" DTE = "0" D1-0 = "11", DIT = "1"
Wait (2 frame or more)
Wait (2 frame or more)
Display OFF GON = "1" DTE = "1" D1-0 = "11", DIT = "0"
Display OFF GON = "1" DTE = "1" D1-0 = "11", DIT = "1"
8-color mode display
262,141-color mode display
Rev.1.10, Jun.21.2003, page 96 of 133
HD66773R
Instruction Setting Flow
Make the setting for each instruction according to the following sequence. Display ON/OFF
Display off
EQ = 0 Display off GON = "1" DTE = "1" D1-0 = "10" Wait (2 frames or more) Display off GON ="1" DTE = "0" D1-0 = "10" Wait (2 frames or more) Display on GON = "0" DTE = "0" D1-0 = "01" Wait (2 frames or more) Display on GON ="1" DTE = "0" D1-0 = "01" Display on GON ="1" DTE = "0" D1-0 = "11" Wait (2 frames or more) Display on GON ="1" DTE = "1" D1-0 = "11"
Display on
Power On sequence
see Note 1
Display off GON ="0" DTE = "0" D1-0 = "00"
Power OFF sequence
see Note 2)
Display OFF
Display ON
To Display ON flow
To Display OFF flow
Note 1) See Page 99, "Power Supply Setting Flow". Execute the power on sequence. Note 2) See Page 99, "Power Supply Setting Flow". Execute the power off sequence.
Rev.1.10, Jun.21.2003, page 97 of 133
HD66773R Standby and Sleep
Standby
Display OFF flow Set standby
Sleep
Display OFF flow
Set sleep Power supply OFF sequence Note 2)
Power supply OFF sequence Note 2)
Set standby(STB = "1")
Set sleep (SLP = "1")
Oscillation start Wait 10 ms
Set standby(STB = "0")
Release standby
Release sleep (SLP = "0")
Release sleep
Power ON Sequence
Note 1)
Power ON Sequence
Note 1)
Display on flow
Display on flow
Note 1) See Page 99, "Power Supply Setting Flow". Execute the power on sequence. Note 2) See Page 99, "Power Supply Setting Flow". Execute the power off sequence.
Rev.1.10, Jun.21.2003, page 98 of 133
HD66773R
Power Supply Setting Flow
When turning on the power supply, follow the sequence below. The stabilization time for the oscillation circuits, step-up circuits, and operation amplifiers may vary depending on the external resistors and capacitors.
Power OFF sequence
Power ON sequence
Power ON (Vcc On)
1ms
Power-on reset & Display OFF
10ms or more Time for oscillation circuit to stabilize
Display-OFF bit DTE = "0", D1-0 = "00" GON = "0", PON = "0", VcomG = "0"
Issue Instruction (1) for Power setting
Power-initialization setting bit Set VC2-0, VRH3-0, CAD, VRL3-0, VCM4-0, VDV4-0
Normal Display
Display-ON bit DTE = "1", D1-0 = "11" GON = "1"
Display OFF sequence
Issue Instruction (2) for Power setting
Power-operation start setting bit Set BT2-0, DC2-0, AP2-0
Display OFF
Display-OFF bit DTE = "0", D1-0 = "00" GON = "0"
Power On Sequence
40ms or more Time for step-up circuits 1,2 to stabilize
Issue Instruction (1) for Power setting
Step-up1 halt setting bit BT2-0 ="110"
Issue Instruction (3) for Power setting
Step-up circuit 4 operation start setting bit Set VCOMG = "1" (Not required if VcomL = GND)
Wait 100ms or more
Issue Instruction (2) for Power setting
Step-up3,4 halt setting bit PON="0", VCOMG="0"
Power Off Sequence
40ms or mor Time for step-up circuit 4 to stabilize
Issue Instruction (4) fo r for Power setting
Step-up circuit 3 operation start setting bit Set PON = "1"
Issue Instruction (3) for Power setting
Step-up2, amp halt setting bit BT2-0="000", AP2-0="000"
100ms or more Time for step-up circuits & ope-amps to stabilize
Power OFF (Vcc OFF) Issue Instruction for other mode settings
Display-ON sequence Display-ON bit DTE = "1", D1-0 = "11" GON = "1"
Display ON
Rev.1.10, Jun.21.2003, page 99 of 133
HD66773R
Oscillation Circuit
1) External clock mode
Clock
Damping resistor (2k )
OSC1 OSC2 HD66773R
2) External resistor oscillation mode
OSC1
Rf
OSC2 HD66773R
Place the Rf resistor as close as possible to the OSC1, OSC2 pins
OSC1
Rf
OSC2 HD 66773R
other wiring
Place the Rf oscillation resistor as close as possible to the OSC1, OSC2 pins. Do not arrange other wiring beneath OSC1-OSC2 wiring to avoid effects from coupling.
Rev.1.10, Jun.21.2003, page 100 of 133
HD66773R
n-raster-row Inversion AC Drive
The HD66773R, in addition to LCD inversion AC drive by frame, supports n-raster-row inversion AC drive where alternation occurs by n raster-rows, where n takes a number between 1 to 64. The n-raster-row inversion AC drive allows overcoming the problems related to display quality. In determining n (the value set in the NW bit +1), the number of raster-rows by which alternation occurs, check the display quality on the actual liquid crystal panel. Setting a small number of raster-rows will raise the AC frequency of the liquid crystal and increase the charge/discharge current on the liquid crystal cells.
1 frame
Blank period 1 2 3 4 175 176 184 1 2 3 4
1 frame
Blank period 175 176 184 1 2
Frame AC / waveform drive 176-raster-row drive
n-raster-row AC waveform drive 176-raster-row drive 3-raster-row inversion EOR - "1"
Make sure that EOR = "1" in n-raster-row drive to prevent the direct bias on liquid crystal.
Rev.1.10, Jun.21.2003, page 101 of 133
HD66773R
Interlaced Drive
The HD66773R supports interlaced drive, which divide one frame into n fields and then drive to prevent flickers. To determine the number of fields (n: value set in the FLD bits), check the display quality on the actual liquid crystal panel. The following table shows the gate selection for each number of fields, 1 to 3. The figure illustrates the output waveforms of the 3-field interlaced drive. Gate selection
GS = 0 FLD1-0 Field Gate G1 G2 G3 G4 G5 G6 G7 G8 G9 * * * G173 G174 G175 G176 O O O O O O O O O * * * O O O O O O * * * * * * O O O O O * * * O O O O O O 01 1 11 2 3 Gate G176 G175 G174 G173 G172 G171 G170 G169 G168 * * * G4 G3 G2 G1 O O O O O O O O O * * * O O O O O O * * * * * * O O O O O * * * O O O O O O GS = 1 FLD1-0 Field 01 1 11 2 3
Rev.1.10, Jun.21.2003, page 102 of 133
HD66773R
1 frame Blank period Field (1) AC polarity G1 G2 G3 G4 G5 G6 Field (2) Field (3) Field (1)
G3n+1 G3n+2 G3n+3
Gate output timing during 3-field interlaced drive
Rev.1.10, Jun.21.2003, page 103 of 133
HD66773R
AC Timing
The AC timings of frame inversion AC drive, 3-field interlaced drive, and n-raster-row inversion drive are illustrated as follows. In case of frame inversion AC drive, alternation occurs at the completion of drawing one frame, followed by a blank, which lasts for 16H periods. AC Timing The AC timings of frame inversion AC drive, 3-field interlaced drive, and n-raster-row inversion drive are illustrated as follows. In case of frame inversion AC drive, alternation occurs at the completion of drawing one frame, followed by a blank, which lasts for 8H periods. In this case, all the outputs from the gate are Vgoff outputs. In case of interlaced drive, alternation occurs at the completion of drawing one field, followed by a blank. The total period of the blanks in one frame amounts to 8 period. In case of n-rasterrow, a blank lasting 8H period is inserted after drawing a full screen.
Frame inversion AC drive 3-field interlace drive n-raster-row inversion AC drive n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row Blank period n-raster-row
A/C A/C
Field 1 A/C
Blank period 1
A/C A/C A/C A/C A/C A/C A/C A/C A/C A/C
1 frame period
1 frame period
Frame 1
A/C
Field 2
Blank period 2
A/C timing Blank period A/C
Field 3
Blank period 3
Blank period = 8H period
Blank period = Blank period 1 + Blank period 2 + Blank period 3 =8H period
Blank period =8H period
Rev.1.10, Jun.21.2003, page 104 of 133
1 frame period
HD66773R
Frame-Frequency Adjustment Function
The HD66773R incorporates frame frequency adjustment function. The frame frequency during the liquid crystal drive is adjusted by the instruction setting (DIV, RTN) while keeping the oscillation frequency fixed. Setting the oscillation frequency high in advance allows switching the frame frequency in accordance to the kind of picture to be displayed (i.e. moving/still picture). When displaying a still picture, set the frame frequency low to save power consumption, while setting the frame frequency high for displaying a moving picture which requires high-speed switching of screens. Relationship between Liquid Crystal Drive Duty and Frame Frequency The relationship between the liquid crystal drive duty and the frame frequency is calculated by the following formula. The frame frequency is adjusted through instruction setting with the 1-H period adjustment bit (RTN bit) and the operation clock division bit (DIV bit). (Formula for the frame frequency) fosc Frame frequency = Clock cycles per raster-row x division ratio x (Line+8) fosc: R-C oscillation frequency Line: number of drive raster-rows (NL bit) Clock cycles per raster-row: RTN bit Division ratio: DIV bit [Hz]
Calculation Example
The maximum frame frequency = 60 Hz
Number of drive raster-rows: 176 1-H period: 16 clock cycles (RTN3-0 = 0000) Operation clock division ratio: 1 division fosc = 60 Hz x (0 + 16) clock x 1 division x (176 + 8) lines = 177 (kHz) In this case, the R-C oscillation frequency becomes 177 kHz. Adjust the resistance of external resistor for the R-C oscillator to177 kHz.
Rev.1.10, Jun.21.2003, page 105 of 133
HD66773R
Screen -split Drive Function
The HD66773R allows selectively driving two screens at arbitrary positions with the screen-drive position registers (R42 and R43). Only the raster-rows required to display two screens at arbitrary positions are selectively driven to reduce power consumption. The first screen drive position register (R42) specifies the start line (SS17-10) and the end line (SE17-10) for displaying the first screen. The second screen drive position register (R43) specifies the start line (SS27-20) and the end line (SE27-20) for displaying the second screen. The second screen control is effective when the SPT bit is set to 1. The total number of raster-rows driven for displaying the first and second screens must be less than the number of liquid crystal drive raster-rows.
G1 G7
1st screen: 7 raster-row driving Non-display area
G26
2nd screen: 17 raster-row driving
G42
Non-display area
Driven raster-rows: Nl4-0 = "10101" (176 raster-rows) First screen setting : SS17-10 = "00"H, SE17-10 - "06"H Second screen setting : SS27-20 = "19"H, SE27-20 - "29"H, SPT = "1"
Rev.1.10, Jun.21.2003, page 106 of 133
HD66773R Conditions on Setting the 1st/2nd Screen Drive Position Register When making settings for the start line (SS17-10) and end line (SE17-10) of the first screen drive position register (R42), and the start line (SS27-20) and end line (SE27-20) of the second screen drive position register (R43) with the HD66773R, it is necessary to satisfy the following conditions to display screens correctly. One-screen Drive (SPT = 0)
Register Settings (SE17-10) - (SS17-10) = NL (SE17-10) - (SS17-10) < NL Display Operation Full screen display The area of (SE17-10) - (SS17-10) is normally displayed. Partial screen display The area of (SE17-10) - (SS17-10) is normally displayed. The rest of the area is white display irrespective of data in RAM. Setting disabled
(SE17-10) - (SS17-10) > NL
Note 1) SS17-10 SE17-0 "AF"H Note 2) Setting disabled for SS27-20 and SE27-20.
Two-screen Drive (SPT = 1)
Register Settings ((SE17-10) - (SS17-10)) + ((SE27-20) - (SS27-20)) = NL ((SE17-10) - (SS17-10)) + ((SE27-20) - (S27-20)) < NL ((SE17-10) - (SS17-10)) + ((SE27-20) - (SS27-20)) > NL Display Operation Full screen display The area of (SE27-20) - (SS17-10) is normally displayed. Partial screen display The area of (SE27-10) - (SS17-10) is normally displayed. The rest of the area is white display irrespective of data in RAM. Setting disabled
Note 1) Make sure that SS17-10 SE17-10 < SS27-20 SE27-20 "AF"H. Note 2) Make sure that ((SE27-20) - (SS17-10)) NL.
The setting for the driver output in the non-display area during the partial display is changeable according to the characteristics of the display panel. Source outputs in non-display area
Source Output for Non-display Area PT1 0 0 1 1 PT0 0 1 0 1 Positive Polarity V31 V31 GND High-Z Negative Polarity V0 V0 GND High-Z Normal drive Vgoff Vgoff Vgoff Source Output for Non-display Area
Rev.1.10, Jun.21.2003, page 107 of 133
HD66773R To make a setting for the partial display, follow the sequence below.
Full screen display
PT1 - 0 = 00
Set SS/SE bits Screen division drive Wait (more than 2 frames) Set up flow Set if necessary
PT1 - 0 = 01
or
PT1 - 0 = 10 or PT1 - 0 = 11
Partial display on Full screen drive Set up flow
Set SS/SE bits
Full screen display
Rev.1.10, Jun.21.2003, page 108 of 133
HD66773R
Internal Configuration of Power Generation Circuit
The internal configuration of power generation circuit of HD66773R is as follows. The step-up circuit is comprised of the step-up circuit 1 which boost 2 to 3 times the voltage supplied with Vci1, the step-up circuit 2 which further boost 2 to 4 times the voltage boosted by the step-up circuit 1, the step-up circuit 3 which invert the VGH-level voltage with the GND level as the axis and output the VGL-level voltage, and the step-up circuit 4 which invert the Vci-level voltage with the GND level as the axis and output the VCLlevel voltage. The step-up circuit generates the voltage to drive a TFT LCD. Reference voltagea VDH, Vcom and Vgoff for the grayscale voltage are generated either by being adjusted in the internal voltage adjustment circuit or from the voltage at REGP, which is amplified in the amplifiers 1, 2. The Vcom, Vgoff voltages can alternate at an arbitrary voltage level. Vcom must be connected to the panel.
Rev.1.10, Jun.21.2003, page 109 of 133
HD66773R
VREG1 OUT VREG2 OUT Amplifier 2 Vgoff adjustment
V ci
Ampifier 1 VDH adjustment VcomH Adjustment circuit Vci Vci Volume adjsutment circuit
V0P Vcom Amplitude Adjustment circuit Grayscale Voltage Generating circuit V0N V31P V31N VMONI adjustment circuit VcomH output amplifier
*VcomH voltage Adjustment (with external resistors)
REGP
VcomR Vci1 C11*In case of using VciOUT output amplifier Vci C11+ C12C12+ DDVDH Vci2 C21C21+ C22C22+ C23C23+ VGH Note 2
VciOUT output amplifier
Source driver VcomH
Step-up Circuit 1 Vgoff Amplitude Adjustment circuit Vcom L output amplifier VgoffH Output Amplifier
Vcom
VcomL
VgoffH VgoffOUT
Step-up Circuit 2 VgoffL output amplifier Vgoff VgoffL TESTA1 TESTA 2 TESTA 3
Vci3 C31C31+ VGL Step-up Circuit 3
TESTA 4
Note1
Vcc GND
Note 2
Vci
Vci4 C41C41+ VCL Step-up Circuit 4 Gate driver
Vci
GND
HD66773R
Note 1) Use a capacitor of 0.1F (B characteristics). Other capacitors must be 1F (B characteristics). Connect stabilizing capacitors to TESTA1 ~ TESTA4 depending on the display quality or power consumption. Note 2) Place a shot key barrier diode (VF = 0.4V/around 20mA, VR >= 30V
Internal configuration of power supply circuit
Rev.1.10, Jun.21.2003, page 110 of 133
HD66773R
Specification of External Elements Connected to HD66773R
The following table shows specifications of external elements connected to HD66773R power supply. Capacitor
Capacity 1 F (B characteristic) Recommended voltage 6V 10V 25V 0.1 F (B characteristic) 0.1 F (B characteristic) 25V 6V Connect pins VREG1OUT, Vci1, C41-/+ Note 1),VCL Note 1), VcomH, VcomL Note 1) DDVDH, C11+/-, C12+/-, C21+/-, C22+/-, C23+/VREG2OUT, VGH, VGL, C31-/+, VgoffH Note 1), VgoffL (TESTA3) Note 2) V0P, V0N, V31P, V31N, (TESTA4) Note 2)
Note 1) These pins may not be required for some mode setting. Note 2) Connect to a stabilizing capacitor depending on the display quality or power consumption.
Rev.1.10, Jun.21.2003, page 111 of 133
HD66773R
Pattern Diagram for Voltage Setting
The following figures are the pattern diagram of voltage setting for the HD66733R and the voltage waveforms.
VGH(+9~16.5V)
VGH
BT2-0
VREG1OUT
BT2-0 VRH3-0 VCM4-0
DDVDH(+4.5 ~ 5.5V) DDVDH VREG1OUT(3.0 ~ DDVDH+0.5V) VcomH(3.0 ~ VREG1OUT)
Vci (2.5~ 3.3V) Vcc (2.2~3.3V) GND (0V
VCi1
VC2-0
VDV4-0
(-1
)
VcomL(VCL+0.5 ~ 1.0V) VCL(- 3.6 ~ 2.5V)
VCL
VRL3-0
( x -1)
VgoffH(VGL+4.0 ~ 5.0V)
VREG2OUT
VgoffL(VGL+0.5 ~ 5.0V) VGL(- 9 ~ -16.5V)
VGL
Note: The relationships DDVDH-VREG1OUT>0.5V, VcomL-VCL>0.5V,Vgoff-VGL>0.5V are changeable depeinding on the load on the panel to be driven. Make an appropriate setting for the voltage. It is possible to directly imput Vci to Vci1.
VGH
VREG1OUT VcomH Vcom Sn VgoffH Gn VgoffL VcomL
Rev.1.10, Jun.21.2003, page 112 of 133
HD66773R
Absolute Maximum Ratings
Item Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Power supply voltage (4) Power supply voltage (5) Power supply voltage (6) Power supply voltage (7) Input voltage Operating temperature Storage temperature Symbol Vcc Vci - GND DDVDH - GND GND -VCL DDVDH - VCL VGH - GND GND - VGL Vt Topr Tstg Unit V V V V V V V V C C Value -0.3 ~ + 4.6 -0.3 ~ + 4.6 -0.3 ~ + 6.0 -0.3 ~ + 4.6 -0.3 ~ + 9.0 -0.3 ~ + 18.5 -0.3 ~ + 18.5 -0.3 ~ Vcc + 0.3 -40 ~ + 85 -55 ~ + 110 Notes 1, 2 1, 2 1, 2 1, 2 1 1, 2 1, 2 1 1, 3 1
Note 1) The LSI may be permanently damaged if it is used under the condition exceeding the above absolute maximum ratings. It is also recommended to use the LSI within the limit of its electric characteristics during normal operation. Exceeding the conditions may lead to malfunction of LSI and affect its credibility. Note 2) The voltage from GND. Note 3) The DC and AC characteristics of chip and wafer products are guaranteed at 85 C.
Rev.1.10, Jun.21.2003, page 113 of 133
HD66773R
Electric Characteristics
DC Characteristics (VCC = 1.8 to 3.7 V, Ta = -40 ~ +85C Note 1 )
Item Input high voltage Input low voltage (1) (OSC1 pin) Input low voltage (2) (Except OSC1 pin) Output high voltage (1) (DB0-17 pins) Output low voltage (1) (DB0-17 pins) VOH1 VOL1 V V
Symbol Unit Test Condition
Min 0.7 VCC -0.3 -0.3 -0.3
Typ -- -- -- --
Max VCC
Notes 2, 3
VIH VIL1 VIL2
V V V
VCC = 2.2 to 3.3 V VCC = 2.2 to 3.3 V VCC = 2.2 to 2.4 V Vcc = 2.4 to 3.3V I0H = -0.1mA Vcc = 2.2V to 2.4V, IOL =0.1mA Vcc = 2.4V to 3.3V, IOL =0.1mA
0.15VCC 2, 3 0.15VCC 2, 3 0.2 VCC 2, 3 -- 2
-0.75Vcc -- -- -- -1 -- -- -- 90
0.2Vcc 2 0.15Vc 2 c 1 200 4 5
I/O leakage current
ILi
A A
Vin = 0 to Vcc
Current consumption during IOP normal operation (Vcc - GND)
Ta = 25C, 260,000 colors -- display, Vcc = 3V, CR oscillation; fosc = 176kHz (176 line drive), RAM data: 0000h, AP=001, CAD=1, VCOMG=1
Current consumption during Ici Normal operation (Vci - GND) Current consumption during Standby mode (Vcc - GND) Output voltage difference Average output voltage fluctuation Vo V IST
VCI1 = 0.92 x VCI (VC2-0 = 001), DDVDH = 2 x VCI1, VGH = 3 x VCI2 (BT2-0 = 000), Step up circuit 1 = 60 divided cycle, Step up circuit 2, 3, and 4 = 240 divided cycle (DC2-0 = 000), VREG1OUT = REGP x 1.65 = 4.55V, (VRH = 0011) VCOMH = VREG1OUT x 0.76 = 3.46V, (VCM = 10011), VCOML = 3.46 - (VREG1OUT x 1.23) = -2.13V, (VDV = 10110), VREG2OUT = VCI x - 5.5 = -16.5V, (VRL = 1001), mA VgoffL = -16.5V, VgoffH = -- 16.5V + 5.59V = -10.9V A Vcc = 3V, Ta <=50C Vcc = 3V, Ta >50C
m m
1.25 0.1 -- 5 --
1.5 5 20 -- 35
5
-- -- -- --
5 6 7
V V
-- --
Rev.1.10, Jun.21.2003, page 114 of 133
HD66773R AC Characteristics (VCC = 2.2 to 3.3 V, Ta = -40 to +85C*1) Clock Characteristics (VCC = 2.2 to 3.3 V)
Item External clock frequency External clock duty ratio External clock rise time External clock fall time R-C oscillation clock
Symbol Unit
Test Condition VCC = 2.2 to 3.3 V VCC = 2.2 to 3.3 V VCC = 2.2 to 3.3 V VCC = 2.2 to 3.3 V Rf = 240k, VCC = 3 V
Min 100 45 -- -- 184
Typ 176 50 -- -- 229
Max 600 55 0.2 0.2 274
Notes 8 8 8 8 9
Fcp Duty Trcp Tfcp fOSC
kHz % s s kHz
Rev.1.10, Jun.21.2003, page 115 of 133
HD66773R 68system Bus Interface Timing Characteristics Normal Write Mode (HWM=0) (Vcc = 2.2 to 2.4 V)
Item Enable cycle time Enable "High" level pulse width Enable "Low" level pulse width Inable rising and falling time Set up time (RS, R/W, to E, CS*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Symbol Write Read Write Read Write Read tCYCE PWEH PWEL tEr, tEf tASE tAHE tDSWE tHE tDDRE tDHRE Unit ns ns ns ns ns ns ns ns ns ns ns Timing diagram Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Min 600 800 90 350 300 400 -- 10 5 60 15 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 200 --
High-Speed Write Mode (HWM=1) (Vcc = 2.2 to 2.4 V)
Item Enable cycle time Enable "High" level pulse width Enable "Low" level pulse width Inable rising and falling time Set up time (RS, R/W, to E, CS*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Symbol Write Read Write Read Write Read tCYCE PWEH PWEL tEr, tEf tASE tAHE tDSWE tHE tDDRE tDHRE Unit ns ns ns ns ns ns ns ns ns ns ns Timing diagram Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Min 200 800 90 350 90 400 -- 10 5 60 15 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 200 --
Rev.1.10, Jun.21.2003, page 116 of 133
HD66773R Normal Write Mode (HWM=0) (Vcc = 2.4 to 3.3 V)
Item Enable cycle time Enable "High" level pulse width Enable "Low" level pulse width Inable rising and falling time Set up time (RS, R/W, to E, CS*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Write Read Write Read Write Read
Symbol Unit
tCYCE PWEH PWEL tEr, tEf tASE
ns ns ns ns ns ns
Timing diagram Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1
Min 200 300 40 150 100 100 -- 10 0 2 60 2 -- 5
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- 25 -- -- -- -- -- 100 --
Note -- -- -- -- -- -- with status read without status read -- -- -- -- --
tAHE tDSWE tHE tDDRE tDHRE
ns ns ns ns ns
Figure 1 Figure 1 Figure 1 Figure 1 Figure 1
High-Speed Write Mode (HWM=1) (Vcc = 2.4 to 3.3 V)
Item Enable cycle time Enable "High" level pulse width Enable "Low" level pulse width Inable rising and falling time Set up time (RS, R/W, to E, CS*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Write Read Write Read Write Read Symbol tCYCE PWEH PWEL tEr, tEf tASE Unit ns ns ns ns ns ns Timing diagram Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Min 100 300 40 150 40 100 -- 10 0 2 60 2 -- 5 Typ -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- Note
with status read without status read
tAHE tDSWE tHE tDDRE tDHRE
ns ns ns ns ns
Figure 1 Figure 1 Figure 1 Figure 1 Figure 1
-- -- -- -- --
-- -- -- 100 --
Rev.1.10, Jun.21.2003, page 117 of 133
HD66773R 80-system Bus Interface Timing Characteristics Normal Write Mode (HWM=0) (Vcc = 2.2 to 2.4 V)
Item Bus cycle time Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*, WR*, RD*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Write Read Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr, WRf tAS tAH tDSW tHWR tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Timing diagram Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 600 800 90 350 300 400 -- 10 5 60 15 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 200 --
High-Speed Write Mode (HWM=1) (Vcc = 2.2 to 2.4 V)
Item Bus cycle time Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Set up time (RS to CS*, WR*, RD*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Write Read Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr, WRf tAS tAH tDSW tHWR tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Timing diagram Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 200 800 90 350 90 400 -- 10 5 60 15 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- 200 --
Rev.1.10, Jun.21.2003, page 118 of 133
HD66773R Normal Write Mode (HWM=0) (Vcc = 2.4 to 3.3 V)
Item Bus cycle time Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Set up time (RS to CS*, WR*, RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time Write Read Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr, WRf tAS tAH tDSW tHWR tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Timing diagram Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 200 300 40 150 100 100 -- 10 0 2 60 2 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- 100 -- with status read without status read Notes
High-Speed Write Mode (HWM=1) (Vcc = 2.4 to 3.3 V)
Item Bus cycle time Write low-level pulse width Read low-level pulse width Write high -level pulse width Read high -level pulse width Write/Read rise/fall time Set up time (RS to CS*, WR*, RD*) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Write Read Symbol tCYCW tCYCR PWLw PWLR PWHW PWHR t WRr, WRf tAS tAH tDSW tHWR tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Timing diagram Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 100 300 40 150 40 100 -- 10 0 2 60 2 -- 5 -- -- -- -- -- -- -- -- 100 -- Typ -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- with status read without status read Notes
Rev.1.10, Jun.21.2003, page 119 of 133
HD66773R Serial Peripheral Interface timing characteristics (Vcc = 2.2V to 2.4V)
Item Serial clock cycle time Serial clock hith-level pulse width Serial clock low-level pulse width Write (received) Read (transmitted) Write (received) Read (transmitted) Write (received) Read (transmitted) Symbol tSCYC tSCYC tSCH tSCH tSCL tSCL tscr, tscf tCSU tCH tSISU tSIH tSOD tSOH Unit us us ns ns ns ns ns ns ns ns ns ns ns Timing diagram Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Min 0.1 0.25 40 120 40 120 -- 20 60 30 30 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 20 20 -- -- -- -- 20 -- -- -- -- 130 --
Serial clock rise/fall time Chip select set up time Chip select hold time Serial input data set up time Serial input data hold time Serial output data delay time Serial output data hold time
(Vcc = 2.4V to 3.3V)
Item Serial clock cycle time Serial clock hith-level pulse width Serial clock low-level pulse width Write (received) Read (transmitted) Write (received) Read (transmitted) Write (received) Read (transmitted) Symbol tSCYC tSCYC tSCH tSCH tSCL tSCL tscr, tscf tCSU tCH tSISU tSIH tSOD tSOH Unit us us ns ns ns ns ns ns ns ns ns ns ns Timing diagram Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Min 0.076 0.15 40 70 35 70 -- 20 60 30 30 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 20 20 -- -- -- -- 20 -- -- -- -- 130 --
Serial clock rise/fall time Chip select set up time Chip select hold time Serial input data set up time Serial input data hold time Serial output data delay time Serial output data hold time
Reset Timing Characteristics (VCC = 2.2 to 3.3 V)
Item Reset low-level width Reset rise time Symbol tRES trRES Unit ms s Timing diagram Figure 4 Figure 4 Min 1 -- Typ -- -- Max -- 10
Rev.1.10, Jun.21.2003, page 120 of 133
HD66773R Notes to Electrical Characteristics 1. The DC/AC electrical characteristics of bare die and wafer products are guaranteed at 85C. 2. The following figures illustrate the configurations of I pin, I/O pin, and O pin.
Pins: OSC2
Pins: RESET*, CS*, E/WR/SCL, RW/RD, RS, OSC1, IM3-1, IM0/ID, TEST1, TEST2, TESTV1, DCTEST V cc
Vcc
PMOS PMOS NMOS NMOS GND GND
Pins: DB17 -DB2, DB1/SD0, DB0/SDI Vcc PMOS
(Input circuit )
NMOS Vcc PMOS
(Output circuit: 3 states)
Output ENABLE Output data
NMOS GND
Rev.1.10, Jun.21.2003, page 121 of 133
HD66773R 3. TEST, IM1, IM0/ID pins must be grounded or connected to Vcc. 4. This excludes the current through output drive MOS. 5. This excludes the current through the input/output units. The input level must be fixed to a certain level because penetrating current increases in the input circuit when CMOS input level takes a middle level. The current consumption is unchanged irrespective of "High" or "Low" of CS*pin while the HD66773R is not accessed through interface pins. 6. The output voltage difference is the difference in the voltages of neighboring source outputs for a same display (within a chip). This value is just for a referential purpose. 7. The average output voltage fluctuation is the difference in the average source output voltages among different chips. The average output voltage is an average source voltage within a chip for a same display. 8. This applies to the case when clocks are supplied externally.
2k
Oscillator
OSC1 Open OSC2
0.7Vcc 0.5Vcc 0.3Vcc trcp tfcp
Duty =
Th x 100% Th+ Tl
9.
This applies to the internal oscillator when external oscillation resistor Rf is used.
OSC1 Rf OSC2
The oscillation frequency may change according to the capacitors of OSC1 and OSC2 pins. Connect the OSC1 and OSC2 pins with the possible shortest wiring.
Rev.1.10, Jun.21.2003, page 122 of 133
HD66773R Referential data
Oscillation Resistance (k) 110k 150k 180k 200 k 240 k 270 k 300 k 390 k 430 k Vcc = 1.8 V 329.6 260.7 230.9 213.0 187.7 168.6 154.5 125.4 115.9 Vcc = 2.0 V 362.6 285.4 252.2 230.4 201.3 181.3 166.1 133.7 121.6 Vcc = 2.4 V 399.4 313.3 274.0 251.5 216.8 195.1 178.2 142.3 129.0 Vcc = 3.0V 438.5 337.4 294.9 268.7 229.4 206.9 187.5 148.9 135.2 Vcc = 3.3V 447.6 343.4 302.1 274.8 234.8 210.2 191.1 151.6 137.3
Rev.1.10, Jun.21.2003, page 123 of 133
HD66773R
VCI adjustment circuit - Load characteristics 3.0
VCI1 [V]
VCI1 = 1.00 x Vci VCI1 = 0.92 x Vci VCI1 = 0.87 x Vci VCI1 = 0.83 x Vci VCI1 = 0.76 x Vci
2.8 2.6 2.4 2.2 2.0 1.8 0.0 0. 3 0.6 0.9 1.2 1.5 Load current [mA]
VCI1 = 0.73 x Vci VCI1 = 0.68 x Vci Conditions TYP, room temperature VCC = VCI = 3.0V, fOSC = 240kHz AP = 011 Medium current mode
Step- up1 - Load characteristics 5.5
DDVDH [V]
5.3 5.1 4.9 4.7 4.5 0.0 0. 3 0.6 0.9 1.2 1.5 1/16 cycle 1/32 cycle 1/64 cycle Conditions TYP, room temperature VCC = VCI = 3.0V, fOSC = 240kHz, AP = 011 Medium current mode VCI1 = 0.92 x VCI, Step-up 1 : x2
Load current [mA]
Step- up2 - Load characteristics 17 16
VGH [V]
1/64 cycle 1/124 cycle 1/256 cycle
15 14 13 12 11 0 100 200 Load current [mA] 300 400
Conditions TYP, room temperature VCC = VCI = 3.0V, fOSC = 240kHz AP = 011 Medium current mode VCI1 = 0.92 x VCI, Step up1: x2 (1/32 cycle) Step up 2: x3
Rev.1.10, Jun.21.2003, page 124 of 133
HD66773R
Step- up3 - Load characteristics - 16 - 15
VGL [V]
1/64 cycle 1/128 cycle
- 14 -13 - 12 - 11 0 10 0 200 300 400 1/256 cycle Conditions TYP, room temperature VCC = VCI = 3.0V, fOSC = 240kHz AP = 011 Medium current mode VCI1 = 0.92 x VCI, Step up1: x2 (1/32 cycle) Step up 2: x3
Load current [mA]
Step-up 4 - Load characteristics
- 3.0
VGL [V]
- 2.8 - 2.6 -2.4 - 2.2 0 10 0 200 300 400
1/64 cycle 1/128 cycle 1/256 cycle
Load current [mA]
Conditions TYP, room temperature VCC = VCI = 3.0V, fOSC = 240kHz AP = 011 Medium current mode VCI1 = 0.92 x VCI, Step up1: x2 (1/32 cycle) Step up 2: x3
Rev.1.10, Jun.21.2003, page 125 of 133
HD66773R
Current consumption - Frame frequency dependence 1.6 Normal display 1.4 1.2 1.0 0.8 0.6 0.4 60 80 100 120 Frame frequency [Hz] Conditions TYP, room temperature VCC = VCI = 3.0V, 140 fOSC = 240kHz 176 duty, B waveform AC, RAM = h'0000 AP = 001 Small current mode VCI1 = 0.92 x VCI, Step up1: x2 (1/64 cycle) Step up2: x3 (1/256 cycle) CAD mode VREG1OUT = REGP x 1.65 VREG2OUT = VCI x (-5.5), VCOMH = VREG1OUT x 0.76, VCOML = VCOMH - (VREG1OUT x 1.23) 8-color di splay
Current consumption - Write cycle dependency
Current consumption [mA] Current consumption [mA]
30 25 20 15 10 5 0 0 2 4 6 8 10 Conditions TYP, room temperature VCC = VCI = 3.0V, fOSC = 240kHz 176 duty, B waveform AC, RAM = h'0000 AP = 001 Small current mode VCI1 = 0.92 x VCI, Step up1: x2 (1/64 cycle) Step up2: x3 (1/256 cycle) CAD mode VREG1OUT = REGP x 1.65 VREG2OUT = VCI x (-5.5), VCOMH = VREG1OUT x 0.76, VCOML = VCOMH - (VREG1OUT x 1.23) High-speed write Normal write
Write cycle [MHz]
Rev.1.10, Jun.21.2003, page 126 of 133
HD66773R
Data bus: DB17 ~ DB0 Test point
50pF
Load circuit for AC characteristics test
Rev.1.10, Jun.21.2003, page 127 of 133
HD66773R Timing characteristics diagram 68-system bus interface operation
RS R/W
VIH VIL tASE
VIH VIL tAHE
CS*
VIL Note 1) PWEH VIH VIH VIL
VIL PWEL
E
VIL
VIL
tEr
tEf tCYCE tDSWE tHE
VIH VIL tDHRE
Note 2)
DB0 to DB17
tDDRE
VIH VIL
Wrire data
Note 2) DB0 to DB17 VOH1 Read data VOL1 VOH1 VOL1
Note 1) PWEH is determined by the overlapping period when CS* is "Low" and E is "High". Note 2) Parallel data transfer with DB17-0 pins through 18-bit bus interface. Parallel data transfer with DB17-10, DB8-1 pins through 16-bit bus interface. Fix unused DB9,0 pins to "GND". Parallel data transfer with DB17-9 pins through 9-bit bus interface. Fix unused DB8-0 pins to "GND". Parallel data transfer with DB17-10 pins through 8-bit bus interface. Fix unused DB9-0 pins to "GND".
Figure 1
Rev.1.10, Jun.21.2003, page 128 of 133
HD66773R 80-system bus interface operation
RS
VIH VIL
tAS
VIH VIL
tAH
VIH CS* VIL Note1
PWLW, PWLR PWHW, PWHR
WR* RD* tWRr
VIH VIL
VIH VIL tWRf
tCYCW, tCYCR
VIH
Note 2 DB0 to DB 17
tDDR
tDSW VIH VIL
tHWR VIH VIL
tDHR
Wrire data
Note : 2 DB0 to DB 17 VOH1 VOL1 Read data VOH1 VOL1
Note 1) PWEH is determined by the overlapping period when CS* is "Low" and E is "High". Note 2) Parallel data transfer with DB17-0 pins through 18-bit bus interface. Parallel data transfer with DB17-10, DB8-1 pins through 16-bit bus interface. Fix unused DB9,0 pins to "GND". Parallel data transfer with DB17-9 pins through 9-bit bus interface. Fix unused DB8-0 pins to "GND". Parallel data transfer with DB17-10 pins through 8-bit bus interface. Fix unused DB9-0 pins to "GND".
Figure 2
Rev.1.10, Jun.21.2003, page 129 of 133
HD66773R Serial Peripheral Interface Operation
Start: S
CS* VIL tSCYC tscf tSCH SCL VIH VIL tSISU SDI VIH VIL tSOD SDO VOH1 VOL1 Output data Output data tSIH VIH VIL VIL VIH VIH VIL VIL tSCL VIH
End: P
VIH VIL
tCSU
tscr
tCH
Input data
Input data
tSOH VOH1 VOL1
Figure 3 Reset operation
trRES
tRES VIH
RESET*
VIL
VIL
Figure 4
Rev.1.10, Jun.21.2003, page 130 of 133
HD66773R
Insert Wiring example
Rev.1.10, Jun.21.2003, page 131 of 133
HD66773R
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Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Rev.1.10, Jun.21.2003, page 132 of 133
HD66773R
Revision Record
Rev. 1.01 Date 2003.Jan. Contents of Modification Page 112. Delete "DB1SD0" and "DB0/SD1" in the figure. Page 113. Change Note 6. Change "R1" to "%RF" in the figure. 1.2 2003.Jun. Page 7. Add "or DDVDH". Page 8. Error corrections. Page 9. Error corrections. Add descriptions to "DUMMY1, 21, 23, 39" and "DUMMY 2-21, 24-38". Page 21. Specify the instruction accessible during the standby mode: R03h Page 73. Error correction. Page 77. Add the power off sequence. Page 78. Add the power off sequence. Page 79. Correction to the Figure: Power Off Sequence. Page 89. Change the recommended voltage for TEST4. Page 90. Error correction. Page 95, 96. Error corrections. Change Figure 1 to Figure 2, "tH" to "THWR" Page 97. Error correction. Page 99. Specify the application of notes 6, 7. Drawn by Approved by
Rev.1.10, Jun.21.2003, page 133 of 133

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