| PART |
Description |
Maker |
| K4D623238B-GQC |
512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM wi Extended Data Out Data Sheet
|
Samsung Electronic
|
| W9725G6KB25A W9725G6KB-25 W9725G6KB-18 W9725G6KB-3 |
DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
|
Winbond
|
| MC74HC354DW MC54_74HC354 ON1412 MC54HC354 MC74HC35 |
8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs
8-INPUT DATA SELECTOR/MULTLPLEXER WLTH DATA AND ADDRESS LATCHER AND 3-STATE OUTPUTS
From old datasheet system
|
Motorola, Inc.
ON Semi
MOTOROLA[Motorola, Inc]
|
| HI-8685PST-10 HI-8685PJI HI-8685PJI-10 HI-8685PJT- |
System component for interfacing incoming ARINC 429 signals to 16-bit parallel data
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC28
384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN
ARINC 429 & 561 SerialDatato16-BitParallelData
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA
|
Holt Integrated Circuit...
HOLT INTEGRATED CIRCUITS INC
Holt Integrated Circuits, Inc.
http://
|
| M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| F-137G |
High Frequency Data Line Filter 3 Coils 6 Data Lines
|
Rhombus Industries Inc.
|
| K4D263238M K4D263238M-QC45 K4D263238M-QC50 K4D2632 |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
|
Samsung Electronic
SAMSUNG[Samsung semiconductor]
|
| MC68HC908JB12 MC68HC908JB12DW MC68HC908JB12JDW MC6 |
Addendum to MC68HC908JB16 Technical Data
This section updates data sheet information and introduces the 20-pin SOIC
|
FREESCALE[Freescale Semiconductor, Inc]
|
| S5T0167X01 |
DTMF DIALER FOR BINARY DATA-IN Data Sheet
|
Samsung Electronic
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
| HSP9501 |
Programmable Data Buffer(???绋??????插?)
Data Buffer, Programmable, 32MHz, Data Word to 10-Bits
|
Intersil Corporation
|
