| PART |
Description |
Maker |
| CY7C1511V18-250BZC CY7C1511V18-167BZC |
72-Mbit QDRII SRAM 4-Word Burst Architecture 8M X 8 QDR SRAM, 0.5 ns, PBGA165
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY7C1268XV18-600BZXC CY7C1270XV18-600BZXC CY7C1268 |
36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor
|
| CY7C2562XV18 CY7C2562XV18-366BZXC CY7C2562XV18-450 |
72-Mbit QDR? II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
Cypress Semiconductor
|
| CY7C2568XV18-600BZXC CY7C2570XV18-600BZXC CY7C2568 |
72-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
Cypress Semiconductor
|
| CY7C1143KV18-450BZC CY7C1145KV18-400BZXI CY7C1145K |
18-Mbit QDRII SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
|
Cypress
|
| CY7C1163KV18-550BZC CY7C1165KV18-400BZC CY7C1165KV |
18-Mbit QDRII SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress
|
| CY7C2163KV18-450BZXI CY7C2163KV18-550BZXI CY7C2165 |
18-Mbit QDRII SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
Cypress
|
| UPD44325084 UPD44325084F5-E50-EQ2 UPD44325094F5-E5 |
CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, RG142B/U COAX, DOUBLE SHIELDED
36M-BIT QDRII SRAM 4-WORD BURST OPERATION 36M条位推出QDRII SRAM4个字爆发运作
36M-BIT QDRII SRAM 4-WORD BURST OPERATION 36M条位推出QDRII SRAM个字爆发运作
4M X 8 QDR SRAM, 0.45 ns, PBGA165 13 X 15 MM, PLASTIC, FBGA-165
|
NEC Corp.
NEC, Corp.
|
| CY7C1387F-167BGC CY7C1387F-167BGI CY7C1387F-167BGX |
Replacement for Intersil part number 8100604EA. Buy from authorized manufacturer Rochester Electronics.
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA165
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM 1M X 18 CACHE SRAM, 3 ns, PBGA165
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM 18兆位（为512k × 36 / 1兆位× 18）流水线双氰胺同步静态存储器
|
Cypress Semiconductor Corp.
|
| CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
18-Mbit DDR-II SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM
SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
