| PART |
Description |
Maker |
| M2V64S50ETP-I |
64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range)
|
Elpida Memory
|
| HYB25D512160BC-6 HYB25D512800BC-6 |
512-Mbit Double-Data-Rate SDRAM 32M X 16 DDR DRAM, 0.7 ns, PBGA60
512-Mbit Double-Data-Rate SDRAM 64M X 8 DDR DRAM, 0.7 ns, PBGA60
|
Qimonda AG
|
| M390S6450BT1 |
64M x 72 SDRAM DIMM with PLL & Register based on 64M x 4, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD Data Sheet
|
Samsung Electronic
|
| 106414-1205 |
QSFP to MPO Quad Data Rate PSM4 Active Optical Cable, 40 Gbps Data Rate, 2dB Loss Budget, Cable Length 5.0m
|
Molex Electronics Ltd.
|
| IS42S16160C IS42S16160C-6TL IS42S16160C-6TLI IS42S |
256 Mb Single Data Rate Synchronous DRAM
|
Integrated Silicon Solution, Inc
|
| IDT5T907PAI IDT5T907 |
2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER
|
IDT[Integrated Device Technology]
|
| K4D26323RA-GC |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| K4D28163HD |
2M x 16Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| IDT723643 IDT723633 IDT723623 IDT723623L15 IDT7236 |
HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP 0 to 70
High-Slew-Rate, Single-Supply Operational Amplifier 8-PDIP -40 to 105
Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70
CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36
HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-PDIP 0 to 70 的CMOS总线匹配SyncFIFOTM 256 × 3612 × 36024 × 36
|
济南固锝电子器件有限公司
Jinan Gude Electronic Device Co., Ltd.
|
| M13S2561616A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12 |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| W9412G6JH W9412G6JH-5 |
2M ?4 BANKS ?16 BITS DDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
|
Winbond
|
