| PART |
Description |
Maker |
| NB6L16 |
Clock or Data Receiver / Driver / Translator Buffer, 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL
|
ON Semiconductor
|
| NB7L216MNEVB |
2.5 V / 3.3 V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination
|
ON Semiconductor
|
| 74279PC 74155PC 7439PC 7432PC 7473PC 7438PC 7432DC |
S-R-Type Latch
Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four
LVTTL/TTL/CMOS-to-Differential LVECL/ECL Translators
DirectDrive Video Amplifier with Reconstruction Filter and Analog Switch
Quad 2-input NAND Gate
Quad 2-input OR Gate
Decoder/Driver
Dual 4-input NOR Gate
Ultra-Low-Power, Low-Cost Comparators with 2% Reference
Hex Buffer
1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver
J-K-Type Flip-Flop
2.5V Video Amplifier with Reconstruction Filter
1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
Differential LVPECL/LVECL/HSTL Receiver/Drivers
16-Input Digital Multiplexer 16输入数字复接
1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver 16输入数字复接
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers 十六进制逆变
2-To-4-Line Demultiplexer 2线复用器
|
Rochester Electronics, LLC
TE Connectivity, Ltd.
|
| R2705E |
27.195MHz FSK Radio Data Receiver for Manchester Data Format
|
List of Unclassifed Manufacturers
|
| SRM-155 SRM-155A SRM-155B SRM-155C |
Telecomm/Datacomm
SONET/SDH Fiber-Optic Receiver Module with SAW Filter Clock Recovery and Data Retiming(SONET/SDH 光纤接收模块(带SAW滤波时钟恢复和数据重定时功能))
|
Vectron International, Inc.
|
| AK2124 |
Radio Controlled Clock Receiver
Receiver/Demodulator for time code signals transmitted by the transmitters 接收解调器的时间码信号传输的发射
|
List of Unclassifed Manufacturers
ETC[ETC]
Electronic Theatre Controls, Inc.
Gunter Seniconductor GmbH.
|
| ADN2811ACP-CML ADN2811 |
Dual Rate Limiting Amplifier and Clock and Data Recovery IC
OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
|
Analog Devices, Inc.
|
| GTLP6C817 GTLP6C817MTCX |
Low Drive GTLP-to-LVTTL 1:6 Clock Driver; Package: TSSOP; No of Pins: 24; Container: Tape & Reel GTLP SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Low Drive GTLP/LVTTL 1:6 Clock Driver
|
Fairchild Semiconductor, Corp.
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
