| PART |
Description |
Maker |
| AN1475 |
DEVELOPING AN ST7265xMASS STORAGE APPLICATION
|
STMicroelectronics
|
| ANT4-M24LR-A |
2 x 64 Kbit multibank antenna reference board for the M24LR64-R Dual Interface EEPROM
|
STMicroelectronics
|
| AT91SAM9261-EK |
The AT91SAM9261-EK evaluation kit is an effective platform for evaluating chip performance and developing code for applications based on the AT91SAM92
|
ATMEL Corporation
|
| M50753-PGYS |
Piggyback
The M50753-PGYS is an EPROM mounted-type microcomputer employing a silicon gate CMOS process and was designed for developing programs for single-chip 在M50753 - PGYS是存储器安装型微机采用硅栅CMOS工艺，并负责制定项目设计的单芯片
|
Mitsubishi Electric, Corp.
Mitsubishi Electric Corporation
Mitsubishi Electric Semiconductor
|
| K4D26323RA-GC |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| HI-8684PST-10 HI-8683 HI-8683PJI HI-8683PJT HI-868 |
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA
384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN
(HI-8683 / HI-8684) ARINC INTERFACE DEVICE ARINC 429 & 561 SERIAL DATA TO 8-BIT PARALLEL DATA
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA
System component for interfacing incoming ARINC 429 signals to 8-bit parallel data
|
http://
HOLTIC[Holt Integrated Circuits]
HOLT INTEGRATED CIRCUITS INC
Holt Integrated Circuit...
|
| M13S2561616A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12 |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| NT5DS4M32EG-5 NT5DS4M32EG-5G NT5DS4M32EG-6 |
1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL
|
NanoAmp Solutions, Inc.
|
