| PART |
Description |
Maker |
| HCTS74KTR HCTS74T HCTS74DTR |
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS 20-LCCC -55 to 125
Radiation Hardened Dual-D Flip-Flop with
Set and Reset(抗辐射双D触发器（带置位、复位）)
Radiation Hardened Dual-D Flip-Flop with Set and Reset
HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
|
Intersil Corporation
|
| MC74VHCT574A MC74VHCT74A ON1761 MC74VHCT74AD MC74V |
From old datasheet system
Dual D-Type Flip-Flop with Set and Reset
OCTAL D-TYPE FLLP-FLOP WITH SET AND RESET
|
ON Semiconductor
Motorola
|
| MC74HC109 ON1335 |
Dual J-K Flip-Flop with Set and Rest
From old datasheet system
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
Motorola, Inc
ON Semi
|
| HCF4013 HCF4013M013TR HCF4013B HCF4013BEY HCF4013B |
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
DUAL 'D' - TYPE FLIP-FLOP
DUAL D-TYPE FLIP FLOP
|
STMICROELECTRONICS[STMicroelectronics]
|
| MC100ELT23 MC100EL12DTR2 MC10H131FNR2 MC100H640FNR |
5V Dual Differential PECL to TTL Translator
5V ECL Low Impedance Driver
Dual Type D Master-Slave Flip-Flop
ECL/TTL Clock Driver
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V / 5V ECL ÷4 Divider
Quad 2-Input NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V / 5V Triple ECL Input to LVPECL/PECL Output Translator
|
ON Semiconductor
|
| ACTS74HMSR-02 |
Dual D Type Flip Flop with Set and Reset, Advanced Logic, CMOS; Temperature Range: -55°C to 125°C; Package: Die (Military Visual) ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
|
Intersil, Corp.
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| 74LVC74ABQ-Q100 74LVC74AD-Q100 74LVC74APW-Q100 |
Dual D-type flip-flop with set and reset; positive-edge trigger
|
NXP Semiconductors
|
| 74ALVC74PW 74ALVC74 74ALVC74BQ 74ALVC74D |
Dual D-type flip-flop with set and reset; positive-edge trigger
|
PHILIPS[Philips Semiconductors]
|
| 74HC74DR2 74HC74DR2G 74HC74D 74HC74 74HC74DTR2G 74 |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
Dual D Flip-Flop with Set and Reset(带设置和复位的双D触发 双D触发器的设置和复位（带设置和复位的双触发器）
|
ONSEMI[ON Semiconductor]
|
| 5962F9863201VCC 5962F9863201V9A 5962F9863201VXC AC |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
Radiation Hardened Dual J-K Flip-Flop with Set and Reset 辐射硬化的设置和复位JK触发
|
Intersil Corporation
Intersil, Corp.
|
| 74HC74DR2 74HC74DG |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
ON Semiconductor
|
