| PART |
Description |
Maker |
| GS820H32Q-5I GS820H32T-150I GS820H32GT-5I GS820H32 |
100MHz 12ns 64K x 32 2M synchronous burst SRAM
64K x 32 2M Synchronous Burst SRAM 64K X 32 CACHE SRAM, 12 ns, PQFP100
64K x 32 2M Synchronous Burst SRAM 64K X 32 CACHE SRAM, 9 ns, PQFP100
117MHz 11ns 64K x 32 2M synchronous burst SRAM
138MHz 9.7ns 64K x 32 2M synchronous burst SRAM
|
GSI Technology, Inc.
|
| AS7C3364PFS36A-166TQI AS7C3364PFS32A AS7C3364PFS32 |
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 36 STANDARD SRAM, 9 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 36 STANDARD SRAM, 10 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 32 STANDARD SRAM, 10 ns, PQFP100
DIODE ZENER SINGLE 1000mW 16Vz 15.5mA-Izt 0.05 5uA-Ir 12.2Vr DO41-GLASS 5K/REEL 64K X 36 STANDARD SRAM, 12 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 32 STANDARD SRAM, 12 ns, PQFP100
|
Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
|
| GS82032AT-100 GS82032AT-150 GS82032AT-150I GS82032 |
GS820(E)32A
64K x 32 2Mb Synchronous Burst SRAM
|
GSI[GSI Technology]
|
| GS82032AGT-166I GS82032AGT-180 GS82032AGT-133IT |
64K x 32 2Mb Synchronous Burst SRAM 64K X 32 CACHE SRAM, 8.5 ns, PQFP100
64K x 32 2Mb Synchronous Burst SRAM 64K X 32 CACHE SRAM, 8 ns, PQFP100
64K X 32 CACHE SRAM, 10 ns, PQFP100
|
GSI Technology, Inc.
|
| IDT71V633 IDT71V633S11PF IDT71V633S11PFI |
64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect 64K X 32 CACHE SRAM, 11 ns, PQFP100
|
Integrated Device Technology, Inc.
|
| K7A203600 K7A203600A K7A203600B-QCI14 |
64K x 36-Bit Synchronous Pipelined Burst SRAM Rev. 2.0 (Dec. 1999)
64Kx36 & 64Kx32-Bit Synchronous Pipelined Burst SRAM
64Kx36-Bit Synchronous Pipelined Burst SRAM
|
Samsung Electronic
SAMSUNG[Samsung semiconductor]
SAMSUNG SEMICONDUCTOR CO. LTD.
|
| M58CR032C100ZB6T M58CR032C120ZB6T M58CR032C85ZB6T |
32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory
32 Mbit 2Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory
32 Mbit 2Mb x 16 / Dual Bank / Burst 1.8V Supply Flash Memory
From old datasheet system
|
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| EDI2DL32256V EDI2DL32256V35BC EDI2DL32256V40BC EDI |
TMS320C6202. TMS320C6203. TMS320C6204. TMS320C6 Families
x32 Fast Synchronous SRAM
256Kx32 Synchronous Pipline Burst SRAM 3.3V(3.3V,4.0ns,256Kx32同步流水线脉冲静态RAM)
256Kx32 Synchronous Pipline Burst SRAM 3.3V(3.3V,3.5ns,256Kx32同步流水线脉冲静态RAM)
256Kx32 Synchronous Pipline Burst SRAM 3.3V(3.3V,3.8ns,256Kx32同步流水线脉冲静态RAM)
|
WEDC[White Electronic Designs Corporation]
|
| MT55L64L32P1 MT55L128L18P |
64K x 32,3.3V I/O, ZBT SRAM( 2Mb,3.3V输入/输出，静态RAM)
128K x 18, 3.3V I/O, ZBT SRAM(2Mb,3.3V输入/输出，静态RAM) 128K的18.3V的I / O的ZBT SRAM的（处理器，3.3V的输输出，静态内存）
|
Micron Technology, Inc.
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| CY7C0430V 7C0430V CY7C0430V-133BGI CY7C0430V-133BG |
3.3V 64K x 18 Synchronous QuadPort⑩ Static RAM
3.3V 64K X 18 SYNCHRONOUS QUADPORT⒙ STATIC RAM
From old datasheet system
3.3V 64K x 18Synchronous QuadPort?Static RAM
|
CYPRESS[Cypress Semiconductor]
|
| MT58L128L18FT-10 MT58L128L18FT-7.5 MT58L128V18F MT |
2MB: 128K X 18, 64K X 32/36 FLOW-THROUGH SYNCBURST SRAM
|
MICRON[Micron Technology]
|
|
