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CY7C1303BV2512 - 18-Mbit Burst of Two-Pipelined SRAM with QDR? Architecture

CY7C1303BV2512_5781254.PDF Datasheet


 Full text search : 18-Mbit Burst of Two-Pipelined SRAM with QDR? Architecture
 Product Description search : 18-Mbit Burst of Two-Pipelined SRAM with QDR? Architecture


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128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 256K X 18 CACHE SRAM, 4.2 ns, PBGA165
128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 128K X 36 CACHE SRAM, 4.2 ns, PBGA119
128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 128K X 36 CACHE SRAM, 4.2 ns, PBGA165
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128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 128K X 36 CACHE SRAM, 3.8 ns, PBGA119
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