| PART |
Description |
Maker |
| HM66AQB18204BP-33 HM66AQB36104BP-40 HM66AQB9404BP- |
Memory>Fast SRAM>QDR SRAM
36-Mbit QDRTMII SRAM 4-word Burst
|
Renesas Technology / Hitachi Semiconductor
|
| LC3564B LC3564BM LC3564BS LC3564BT LC3564BT-10 LC3 |
x8 SRAM
64K (8192-word 8-bit) SRAM with OE, CE1, and CE2 Control Pins
64K (8192-word ? 8-bit) SRAM with OE, CE1, and CE2 Control Pins
64K (8192-word x8-bit) SRAM with NOT OE, NOT CE1, and CE2 Control Pins
64K (8192-word x 8-bit) SRAM with NOT OE, NOT CE1, and CE2 Control Pins
64K (8192-word 8-bit) SRAM with OE / CE1 / and CE2 Control Pins
64K (8192-word ′ 8-bit) SRAM with OE, CE1, and CE2 Control Pins
64K (8192-word 8-bit) SRAM with OE, CE1, and CE2 Control Pins 64K的（8192字?8位）与光电，CE1上SRAM和控制引脚铈
|
SANYO[Sanyo Semicon Device]
Sanyo Electric Co.,Ltd.
Sanyo Electric Co., Ltd.
|
| LC35256DM LC35256DT-10 LC35256DT-70 LC35256D-10 25 |
x8 SRAM
Dual Control Pins: OE and CE 256K (32768-word X 8-bit) SRAM
|
SANYO[Sanyo Semicon Device]
Sanyo Electric Co.,Ltd.
|
| CAT93C46AJ CAT93C46AJI CAT93C46AJI-2.5 CAT93C46AJ- |
72-Mbit QDR™-II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
72-Mbit QDR™-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
256K (32K x 8) Static RAM
256 Kb (256K x 1) Static RAM
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Microwire Serial EEPROM 微型导线串行EEPROM
|
Atmel, Corp.
|
| CY7C1141V18 CY7C1145V18 CY7C1156V18 CY7C1143V18 CY |
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 2M X 9 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor Corp.
|
| CY7C1565V18-300BZI |
72-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 36 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1568KV18-500BZXC CY7C1568KV18-500BZC CY7C1570K |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| CAT64LC20ZS CAT64LC20ZP CAT64LC20J-TE7 CAT64LC20J- |
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
36-Mbit QDR™-II SRAM 2-Word Burst Architecture
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture
4-Mbit (128K x 36) Flow-through SRAM with NoBL™ Architecture
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture
SPI Serial EEPROM SPI串行EEPROM
36-Mbit QDR™-II SRAM 2-Word Burst Architecture SPI串行EEPROM
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM SPI串行EEPROM
256K (32K x 8) Static RAM SPI串行EEPROM
|
Analog Devices, Inc.
Electronic Theatre Controls, Inc.
|
| M5M4V16169DRT-10 M5M4V16169DRT-15 M5M4V16169DRT-7 |
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
|
Mitsubishi Electric Corporation
Mitsubishi Electric Semiconductor
|
| CY7C1315AV18-250BZC CY7C1311AV18 CY7C1311AV18-167B |
18-Mb QDR(TM)-II SRAM 4-Word Burst Architecture
18-Mb QDRTM-II SRAM 4-Word Burst Architecture
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1314BV18 CY7C1312BV18 |
18-Mbit QDR庐 II SRAM Two-Word Burst Architecture
18-Mbit QDR? II SRAM Two-Word Burst Architecture
|
Cypress Semiconductor
|
