| PART |
Description |
Maker |
| WED2ZLRSP01S42BC WED2ZLRSP01S50BI WED2ZLRSP01S38BC |
512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM
|
WEDC[White Electronic Designs Corporation]
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| AS5SP256K36DQ AS5SP256K36DQ-30ET AS5SP256K36DQ-30I |
Plastic Encapsulated Microcircuit 9.0Mb, 256K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect
|
Austin Semiconductor
|
| WED2ZL361MV50BC WED2ZL361MV38BC WED2ZL361MV42BC WE |
1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,5.0ns同步脉冲流水线静态RAM(无总线等待时间 100万36同步管道爆裂NBL的静态存储器00万x 36,5.0纳秒同步脉冲流水线静态随机存储器(无总线等待时间)) 1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,3.8ns同步脉冲流水线静态RAM(无总线等待时间 100万36同步管道爆裂NBL的静态存储器00万x 36,3.8纳秒同步脉冲流水线静态随机存储器(无总线等待时间)) 1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,4.2ns同步脉冲流水线静态RAM(无总线等待时间 100万36同步管道爆裂NBL的静态存储器00万x 36,4.2纳秒同步脉冲流水线静态随机存储器(无总线等待时间)) 1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,3.5ns同步脉冲流水线静态RAM(无总线等待时间 100万36同步管道爆裂NBL的静态存储器00万x 36,3.5纳秒同步脉冲流水线静态随机存储器(无总线等待时间))
|
Vicor, Corp.
|
| EUA6210 EUA6210MIR1 |
128K x 36, 3.3V, Sync Burst Pipeline Output Capacitor-less 67mW Stereo Headphone Amplifier 128K x 32, 3.3V, Sync Burst Pipeline
|
寰蜂俊绉???′唤?????? Eutech Microelectronics Inc 德信科技股份有限公司
|
| AS7C33512PFS16A |
3.3V 512K x 16/18 pipeline burst synchronous SRAM 3.3V 512K×16 Pipeline Burst Synchronous SRAM(3.3V 512K×16流水线脉冲同步静态RAM) 3.312k × 16管道爆裂同步SRAM的电压(3.3V12k × 16流水线脉冲同步静态内存)
|
Alliance Semiconductor, Corp.
|
| GS88132BT-150IV |
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 256K X 32 CACHE SRAM, 7.5 ns, PQFP100
|
GSI Technology, Inc.
|
| GS84032T-166 GS84032B-100 GS84032B-166 GS84032B-15 |
128K X 32 CACHE SRAM, 8 ns, PBGA119 4Mb56K x 18Bit) Synchronous Burst SRAM(4M位(256K x 18位)同步静态RAM(带2位脉冲地址计数器)) 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
|
GSI Technology
|
| IS61NLP25636 IS61NLP25632 IS61NLP51218 IS61NP51218 |
256K x 32 pipeline no wait state bus sram 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K x 32 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM
|
ISSI[Integrated Silicon Solution Inc] ISSI[Integrated Silicon Solution, Inc]
|
| 7C33128PFS36A |
3.3V 128K x 32/36 pipeline burst synchronous SRAM
|
Alliance Semiconductor
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation. Renesas Electronics, Corp.
|
| MCM72PB8ML3.5R MCM72PB8ML4 MCM72PB8ML4R MCM72FB8ML |
256K x 72 Bit Burst RAM Multichip Module 256K X 72 CACHE SRAM MODULE, 3.5 ns, PBGA209 256K x 72 Bit Burst RAM Multichip Module 256K X 72 CACHE SRAM MODULE, 4 ns, PBGA209 CAP CER 680PF 100V C0G 0603 256K X 72 CACHE SRAM MODULE, 7.5 ns, PBGA209
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Motorola, Inc. Electronic Theatre Controls, Inc. Motorola Mobility Holdings, Inc.
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