| PART |
Description |
Maker |
| IDT5T9050PGI IDT5T9050 |
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERJR 2.5V的单数据传输速率1:5时钟缓冲器TERABUFFER⑩JR
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER⑩ JR
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.
|
Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
|
| M13S5121632A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W972GG6JB W972GG6JB-25 |
16M ?8 BANKS ?16 BIT DDR2 SDRAM
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| NB6L11 NB6L11DTR2 NB6L11D NB6L11DR2 NB6L11DT |
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
6GHz 2.5V/3.3V Multilevel Input to Differential LVNECL/LVPECL 1:2 Clock or Data Fanout Buffer/Transl
From old datasheet system
|
ONSEMI[ON Semiconductor]
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
| MAX3991 MAX3991UTG |
DC to 4-GBPS Dual 1:2 MUX/Repeater/Equalizer 48-VQFN -40 to 85
10Gbps Clock and Data Recovery with Limiting Amplifier
10 Gbps clock and data recovery with limiting amplifier
|
Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
|
| NBSG53AMNG NBSG53AMNR2G NBSG53A_06 NBSG53ABA NBSG5 |
2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS
|
ONSEMI[ON Semiconductor]
|
| SY100EL90VZG SY100EL90VZG-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
