| PART |
Description |
Maker |
| HCTS112MS HCTS112D HCTS112DMSR HCTS112HMSR HCTS112 |
Radiation Hardened Dual JK Flip-Flop HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16
|
Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| 74FR1074 74FR1074SCX |
FR/FASTR SERIES, DUAL NEGATIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 0.150 INCH, MS-012, SOIC-14
From old datasheet system
Dual D-Type Flip-Flop
|
Fairchild Semiconductor, Corp.
|
| 74VHCT74A 74VHCT74AM 74VHCT74ASJ 74VHCT74 74VHCT74 |
Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-SOIC -40 to 85 AHCT/VHCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
Dual D-Type Flip-Flop with Preset and Clear AHCT/VHCT/VT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| 74LV107 74LV107D 74LV107DB 74LV107N 74LV107PW 74LV |
CLP SINE LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| MC74HC109 ON1335 |
Dual J-K Flip-Flop with Set and Rest
From old datasheet system
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
Motorola, Inc
ON Semi
|
| ACTS74HMSR-02 |
Dual D Type Flip Flop with Set and Reset, Advanced Logic, CMOS; Temperature Range: -55°C to 125°C; Package: Die (Military Visual) ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
|
Intersil, Corp.
|
| 57401AJ/883B C57401AJ/883B 57401J 57401L 57402J 57 |
DUAL 'D' - TYPE FLIP-FLOP
x5 Asynchronous FIFO
7 STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDERS
QUAD BILATERAL SWITCH
DUAL-J-K MASTER-SLAVE FLIP-FLOP X5的异步FIFO
x4 Asynchronous FIFO x4异步FIFO
|
Atmel, Corp.
NIC Components, Corp.
|
| DM74AS74 DM74AS74SJX DM74AS74M DM74AS74N DM74AS74S |
Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear AS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| 74F11200 74F112SJ 74F112 74F112PC 74F112SC 74F112S |
From old datasheet system
Dual JK Negative Edge-Triggered Flip-Flop; Package: SOP; No of Pins: 16; Container: Tape & Reel F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| 74LVX112SJ 74LVX112 74LVX112M 74LVX112MTC 74LVX112 |
LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
Low Voltage Dual J-K Flip-Flops with Preset and Clear
|
FAIRCHILD SEMICONDUCTOR CORP
FAIRCHILD[Fairchild Semiconductor]
|
| U74HC74-15 U74HC74G-P14-R U74HC74G-S14-R |
DUAL D FLIP-FLOP
DUAL D FLIP-FLOP WITH SET AND RESET,POSITIVE-EDGEN TRIGGER
|
Unisonic Technologies
|
