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CY2SSTU87706 - 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer SSTU SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52

CY2SSTU87706_4488995.PDF Datasheet
 
Part No. CY2SSTU87706 CY2SSTU877BVXC-43 CY2SSTU877BVXC-43T CY2SSTU877BVXI-32 CY2SSTU877BVXI-32T CY2SSTU877BVXI-43 CY2SSTU877BVXI-43T CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T
Description 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
SSTU SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
File Size 193.45K  /  9 Page  

Maker

Cypress Semiconductor
CYPRESS SEMICONDUCTOR CORP

Homepage http://www.cypress.com/
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 Full text search : 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer SSTU SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
 Product Description search : 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer SSTU SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52

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