| PART |
Description |
Maker |
| CAT64LC20ZS CAT64LC20ZP CAT64LC20J-TE7 CAT64LC20J- |
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
36-Mbit QDR™-II SRAM 2-Word Burst Architecture
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture
4-Mbit (128K x 36) Flow-through SRAM with NoBL™ Architecture
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture
SPI Serial EEPROM SPI串行EEPROM
36-Mbit QDR™-II SRAM 2-Word Burst Architecture SPI串行EEPROM
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM SPI串行EEPROM
256K (32K x 8) Static RAM SPI串行EEPROM
|
Analog Devices, Inc.
Electronic Theatre Controls, Inc.
|
| BBF2805SE BBF2815S BBF2812S BBF2805SK BBF2803SH BB |
3.3V, 20W DC-DC converter
15V, 20W DC-DC converter
12V, 20W DC-DC converter
Analog IC
18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit QDR™-II SRAM 2-Word Burst Architecture
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture
20W DC-DC Converter(输出功率20WDC-DC转换
|
M.S. Kennedy Corp.
M.S. Kennedy Corporation
|
| CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
18-Mbit DDR-II SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM
SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
| CY7C1472BV25-167BZXC CY7C1472BV25-167BZXI CY7C1472 |
2M X 36 ZBT SRAM, 3 ns, PBGA165
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL垄芒 Architecture
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL?/a> Architecture
|
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1302DV25-167BZC CY7C1302DV25-167BZI CY7C1302DV |
9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture
9-Mbit Burst of Two Pipelined SRAMs with QDR垄芒 Architecture
9-Mbit Burst of Two Pipelined SRAMs with QDR⑩ Architecture
|
Cypress Semiconductor
|
| CY7C1518KV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1350 7C1350 |
128Kx36 Pipelined SRAM with NoBL Architecture(带NoBL结构28Kx36流水线式 SRAM) 128K × 36至流水线与总线延迟静态存储器体系结构（带总线延迟结构28K × 36至流水线式的SRAM
128Kx36 Pipelined SRAM with NoBL Architecture(B>NoBL结构28Kx36流水线式 SRAM)
From old datasheet system
|
Cypress Semiconductor Corp.
|
| CY7C1303AV18-167BZC CY7C1306AV18-167BZC CY7C1303AV |
18-Mb Burst of 2 Pipelined SRAM with QDR(TM) Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR垄芒 Architecture
|
Cypress Semiconductor
|
| CY7C1426BV18 CY7C1413BV18 CY7C1411BV18 |
36-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture
36-Mbit QDR?II SRAM 4-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1351 7C1351 CY7C1351-66AC 7C1351-40 7C1351-50 |
128Kx36 Flow-Through SRAM with NoBL TM Architecture
From old datasheet system
128Kx36 Flow-Through SRAM with NoBL Architecture
|
CYPRESS[Cypress Semiconductor]
|
