| PART |
Description |
Maker |
| IDT5T9050PGI IDT5T9050 |
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERJR 2.5V的单数据传输速率1:5时钟缓冲器TERABUFFER⑩JR
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER⑩ JR
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.
|
Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
|
| PSI-REP-DNET-CAN |
Automatic data rate detection or fixed data rate setting via DIP switches
|
PHOENIX CONTACT
|
| 106414-1401 |
QSFP to MPO Quad Data Rate PSM4 Active Optical Cable, 40 Gbps Data Rate, 4dB Loss Budget, Cable Length 1.0m
|
Molex Electronics Ltd.
|
| 106414-1403 |
QSFP to MPO Quad Data Rate PSM4 Active Optical Cable, 40 Gbps Data Rate, 4dB Loss Budget, Cable Length 3.0m
|
Molex Electronics Ltd.
|
| MB81ES171625-15WFKT-X MB81ES173225-15WFKT-X |
SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP 单数据传输速率女的FCRAM消费/嵌入式SIP应用程序特定的内
SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP 1M X 16 SYNCHRONOUS DRAM, 12 ns, UUC84
SINGLE DATA RATE I/F FCRAM Consumer/Embedded Application Specific Memory for SiP 512K X 32 SYNCHRONOUS DRAM, 12 ns, UUC84
|
Fujitsu, Ltd.
Fujitsu Limited
Fujitsu Component Limited.
|
| IDT5T9050PGGI IDT5T9050PGGI8 IDT5T9050PGI8 |
2.5V Single Data Rate 1:5 Clock Buffer TeraBuffer Jr.
|
IDT
|
| IDT5T9070PAI IDT5T9070 IDT5T9070PAI8 |
2.5V Single Data Rate 1:10 Clock Buffer TeraBuffer Jr.
|
IDT[Integrated Device Technology]
|
| PCS2P5T907A PCS2I5T907AG-48TR PCS2P5T907AG-48TR PC |
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
|
PulseCore Semiconductor
|
| K4D26323AA-GL |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| GS8170DD18GC-333IT GS8170DD18C-333I GS8170DD18C-25 |
333MHz 1M x 18 18MB double data rate sigmaRAM SRAM
300MHz 1M x 18 18MB double data rate sigmaRAM SRAM
250MHz 1M x 18 18MB double data rate sigmaRAM SRAM
1M X 18 STANDARD SRAM, 1.6 ns, PBGA209
|
GSI TECHNOLOGY
|
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
