| PART |
Description |
Maker |
| ISPLSI2096VE-100LT128 ISPLSI2096VE-135LT128 ISPLSI |
3.3V In-System Programmable SuperFAST?/a> High Density PLD
CRYSTAL 24.0 MHZ 20PF SMD
3.3V In-System Programmable SuperFASTHigh Density PLD
3.3V In-System Programmable SuperFAST High Density PLD
3.3V In-System Programmable SuperFAST⑩ High Density PLD
3.3VIn-SystemProgrammableSuperFASTHighDensityPLD
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Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
|
| 1024-60LH_883 ISPLSI1024-60LH_883 1024 1024-60LH/8 |
60 MHz in-system prommable high density PLD
In-System Programmable High Density PLD EE PLD, 25 ns, PQCC68
:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:120ohm RoHS Compliant: Yes
|
Lattice Semiconductor, Corp.
Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
http://
|
| QL2003 QL2003_DS QL2003-0PF100C QL2003-0PF100I QL2 |
3.3V and 5.0V pASIC2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pASICò 2 FPGA
From old datasheet system
3.3V AND 5.0V PASIC-R 2 FPGA COMBINING SPEED, DENSITY, LOW COST AND FLEXIBILITY
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pASIC 2系列场可编程逻辑器件)
FPGA, 192 CLBS, 5000 GATES, 200 MHz, PQCC84
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List of Unclassifed Manufacturers
ETC
QuickLogic Corp.
|
| 1032-60LG_883 1032-60LJ 1032-60LJI 1032-60LT 1032- |
High-Density Programmable Logic
In-System Programmable High Density PLD
|
LATTICE[Lattice Semiconductor]
|
| ISPLSI2032A-110LT48I ISPLSI2032A-135LJI ISPLSI2032 |
In-System Programmable High Density PLD EE PLD, 8 ns, PQFP44
In-System Programmable High Density PLD 在系统可编程高密度可编程逻辑器件
In-System Programmable High Density PLD EE PLD, 10 ns, PQCC44
In-System Programmable High Density PLD EE PLD, 10 ns, PQFP48
In-System Programmable High Density PLD EE PLD, 7.5 ns, PQFP44
|
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| SMB10J6.0 SMB10J6.0A SMB10J6.5 SMB10J6.5A SMB8J8.0 |
High Power Density Surface Mount TRANSZORB㈢ Transient Voltage Suppressors
High Power Density Surface Mount TRANSZORB垄莽 Transient Voltage Suppressors
High Power Density Surface Mount TRANSZORB庐 Transient Voltage Suppressors
High Power Density Surface Mount TRANSZORB? Transient Voltage Suppressors
|
Vishay Siliconix
http://
|
| ISOPAC01 ISOPAC0103 ISOPAC0104 ISOPAC0111 ISOPAC01 |
High Current High density Isolated Silicon Power Rectifier(????靛?600V锛?ぇ?垫?锛??瀵?害锛??绂诲?锛??????存???
High Current High density Isolated Silicon Power Rectifier(????靛?1000V锛?ぇ?垫?锛??瀵?害锛??绂诲?纭?????娴??)
High-Current Isolated Rectifier Assemblies. 150 V-1000 V. 10 nS - 2 microseconds 大电流隔离整流器大会150 V000五，10纳秒- 2微秒
HIGH CURRENT ISOLATED RECTIFIER ASSEMBLY
High Current High density Isolated Silicon Power Rectifier(????靛?1000V锛?ぇ?垫?锛??瀵?害锛??绂诲?锛??????存???
|
International Rectifier, Corp.
Semtech Corporation
|
| LC4128X LC4256ZC-45M132C1 LC4256ZC-75M132C1 LC4032 |
3.3V/2.5V/1.8V在系统可编程超快高密PDLs
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs EE PLD, 4.2 ns, PQFP100
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs EE PLD, 7.5 ns, PBGA56
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs EE PLD, 7.5 ns, PQFP48
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs EE PLD, 3.7 ns, PQFP48
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs EE PLD, 5 ns, PBGA56
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs EE PLD, 5 ns, PQFP48
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs EE PLD, 7.5 ns, PQFP100
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
|
Lattice Semiconductor Corporation
http://
Lattice Semiconductor, Corp.
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| CY14B104NA-ZSP20XCT CY14B104NA-ZSP20XIT CY14B104LA |
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP 256K X 16 NON-VOLATILE SRAM, 20 ns, PDSO54
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 512Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: FBGA
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: FBGA
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| ISPLSI5512VE-155LF256 ISPLSI5512VE-155LB272 ISPLSI |
In-system programmable 3.3V SuperWIDE high density PLD. fmax 155 MHz, tpd 6.5 ns.
In-system programmable 3.3V SuperWIDE high density PLD. fmax 125 MHz, tpd 7.5 ns.
EE PLD, 10 ns, PBGA388
In-system programmable 3.3V SuperWIDE high density PLD. fmax 100 MHz, tpd 10 ns.
In-system programmable 3.3V SuperWIDE high density PLD. fmax 80 MHz, tpd 12 ns.
|
LATTICE SEMICONDUCTOR CORP
|
| ISPLSI5256VE-125LT100I ISPLSI5256VE-100LF256I ISPL |
In-system programmable 3.3V SuperWIDE high density PLD. fmax 80 MHz, tpd 12 ns.
EE PLD, 10 ns, PBGA256
In-system programmable 3.3V SuperWIDE high density PLD. fmax 100 MHz, tpd 10 ns.
In-system programmable 3.3V SuperWIDE high density PLD. fmax 125 MHz, tpd 7.5 ns.
In-system programmable 3.3V SuperWIDE high density PLD. fmax 165 MHz, tpd 6.0 ns.
|
Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
|
