| PART |
Description |
Maker |
| BS62LV8005 BS62LV8005BC BS62LV8005BI BS62LV8005EC |
DDR-II, 25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer
Very Low Power/Voltage CMOS SRAM 1M X 8 bit
|
BRILLIANCE SEMICONDUCTOR, INC.
BSI[Brilliance Semiconductor]
|
| ICSSSTUAF32866C |
25-BIT CONFIGURABLE REGISTERED BUFFER
|
IDT
|
| SSTU32866EC_G SSTU32866EC SSTU32866EC/G SSTU32866E |
1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications
|
Philips
NXP Semiconductors N.V.
|
| SSTUA32866EC-G |
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications
|
NXP Semiconductors
|
| ICSSSTUB32864A ICSSSTUB32864AZLFT |
25-Bit Configurable Registered Buffer for DDR2
|
Integrated Device Technology
|
| IDT74SSTUAE32866A IDT74SSTUAE32866ABFG |
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
|
Integrated Device Technology
|
| ICSSSTUAF32868B ICSSSTUAF32868BHLF |
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
|
Integrated Device Technology
|
| ICSSSTUAF32868BHLF |
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
|
Integrated Device Technology, Inc.
|
| ICSSSTUAH32865A ICSSSTUAH32865AHLFT |
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
|
Integrated Device Technology, Inc.
|
| PI74SSTU32864A PI74SSTU32864ANB PI74SSTU32864ANBE |
25-Bit 1:1 or 14-Bit 1:2 Configurable Registered BufferTOOTHERCHANNELSCKCKRST1DC1RQCKEAQCKEB
|
Pericom Semiconductor Corporation
|
| GS8161E32D-166 GS8161E32D-166I GS8161E3T-200 GS816 |
14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TVSOP 0 to 70 100万1812k × 32的，12k × 36 35.7同步突发静态存储器
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 1M×18512k×32512k×36 18M位同步突发静态存储器
20-Bit SSTL_3 Interface Buffer With 3-State Outputs 64-TSSOP 0 to 70 100万1812k × 32的，12k × 36 35.7同步突发静态存储器
25-Bit Configurable Registered Buffer With Address-Parity Test 96-LFBGA 0 to 70 100万1812k × 32的，12k × 36 35.7同步突发静态存储器
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 1M×1812k×3212k×36 18M位同步突发静态存储器
Quad 2-input Exclusive-OR gates 14-PDIP 0 to 70 100万1812k × 32的，12k × 36 35.7同步突发静态存储器
25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70 100万1812k × 32的，12k × 36 35.7同步突发静态存储器
20-Bit SSTL_3 Interface Universal Bus Driver With 3-State Outputs 64-TSSOP 0 to 70
Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70
13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
|
http://
GSI Technology
Electronic Theatre Controls, Inc.
|
