| PART |
Description |
Maker |
| P1480 |
LAN CAM 1KX64 BIT CMOS CONTENT ADDRESSABLE MEMORY
|
Zarlink Semiconductor Inc.
|
| MU9C1480A MU9C1480A-12DC MU9C1480A-12DI MU9C1480A- |
THE 1024 X 64-BIT LANCAM FACILITATES NUMEROUS 1024 X 64-BIT CMOS CONTENT-ADDRESSABLE MEMORY (CAM)
|
ETC
|
| MU9C1480L-12DC MU9C1480L-12DI MU9C1480L-70DC MU9C1 |
90ns 3.3V 8192 x 64 MU9C1480A/L LANCAM
70ns 3.3V 8192 x 64 MU9C1480A/L LANCAM
120ns 3.3V 8192 x 64 MU9C1480A/L LANCAM
90ns 5.0V 8192 x 64 MU9C1480A/L LANCAM
70ns 5.0V 8192 x 64 MU9C1480A/L LANCAM
120ns 5.0V 8192 x 64 MU9C1480A/L LANCAM
The 1024 x 64-bit LANCAM facilitates numerous 1024 x 64-bit CMOS content-addressable memory (CAM)
Content Addressable Memory 内容可寻址存储
|
MUSIC Semiconductors
List of Unclassifed Manufacturers
Atmel, Corp.
|
| R8A20410BG |
20Mbit QUAD-Search Content Addressable Memory
|
Renesas Electronics Corporation
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| SPT9712 SPT9712AIP SPT9712BIP |
12-BIT, 100 MWPS ECL D/A CONVERTER PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 12-BIT DAC, PQCC28
12-BIT 100 MWPS ECL D/A CONVERTER
From old datasheet system
SPT9712
|
Fairchild Semiconductor, Corp.
Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
|
| PDU54-1500 PDU54-2000 PDU54-1200M PDU54-1200MC4 PD |
Delay 1500 /-200 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 2000 /-400 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 1200 /-200 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 1000 /-200 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 200 /-60 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 100 /-50 ns, 4-BIT, ECL-interfaced programmable delay line
|
Data Delay Devices Inc
|
| MC100EP35DR2 MC100EP33D NB100LVEP17MN |
3.3V / 5V ECL JK Flip Flop
3.3V / 5V ECL ÷4 Divider
2.5 V / 3.3 V ECL Quad Differential Driver/Receiver
|
ON Semiconductor
|
| MC100LVE310FN MC100LVE31006 MC100LVE310FNG MC100LV |
3.3V ECL 2:8 Differential Fanout Buffer(3.3V ECL 2 差分输出缓冲 3.3V的差分ECL 2:8扇出缓冲器（3.3 ECL 2:8差分输出缓冲器）
|
ONSEMI[ON Semiconductor]
|
| ECLSOIC8EVB NB6L16D MC100EL01D MC100EL04D MC100EL0 |
3.3V / 5V ECL JK Flip Flop
5V ECL 2-Input XOR/XNOR
5V ECL Divide by 2 Divider
Evaluation Board Manual for High Frequency SOIC 8
|
ONSEMI[ON Semiconductor]
|
| MC100EL07DTR2 MC100EP33DR2 MC100EL38 |
5V ECL 2-Input XOR/XNOR
3.3V / 5V ECL ÷4 Divider
5V ECL Divide by 2, Divide by 4/6 Clock Generation Chip
|
ON Semiconductor
|
