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  lvttl-interface Datasheet PDF File

For lvttl-interface Found Datasheets File :: 6279    Search Time::4.703ms    
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    ASM2P5T905A ASM2I5T905AF-28TR ASM2P5T905AF-28TR ASM2I5T905AF-28TT ASM2P5T905AF-28TT ASM2I5T905AG-28TR ASM2P5T905AG-28TR

PulseCore Semiconductor
Part No. ASM2P5T905A ASM2I5T905AF-28TR ASM2P5T905AF-28TR ASM2I5T905AF-28TT ASM2P5T905AF-28TT ASM2I5T905AG-28TR ASM2P5T905AG-28TR ASM2I5T905AG-28TT ASM2P5T905AG-28TT
OCR Text ...ctable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface Selectable differential or single-ended inputs and five single ended outputs 2.5V Supply Voltage Available in TSSOP Package to five single-ended outputs buffer built on ad...
Description 2.5V Single Data Rate 1:5 Clock Buffer Terabuffer

File Size 682.71K  /  19 Page

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    Integrated Device Techn...
Part No. 8T49N028
OCR Text ...ter power-up via i 2 c. lvcmos/lvttl interface levels. 00 = configuration 0 (default) 01 = configuration 1 10 = configuration 2 11 = configuration 3 20 addr_sel input pulldown i 2 c address select pin. lvcmos/lvttl interface levels. 26, 27...
Description Fourth Generation FemtoClock NG PLL technology

File Size 982.96K  /  36 Page

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    Integrated Device Techn...
Part No. IDT8T49N008I
OCR Text ...ter power-up via i 2 c. lvcmos/lvttl interface levels. 00 = configuration 0 (default) 01 = configuration 1 10 = configuration 2 11 = configuration 3 17 addr_sel input pulldown i 2 c address select pin. lvcmos/lvttl interface levels. 19, 3...
Description Fourth Generation FemtoClock NG PLL technology

File Size 478.65K  /  38 Page

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    Integrated Device Techn...
Part No. IDT8T49N004I
OCR Text ...fter power-up via i 2 c. lvcmos/lvttl interface levels. 00 = configuration 0 (default) 01 = configuration 1 10 = configuration 2 11 = configuration 3 16, 31 v cc power core supply pins. 19, 20 nq3, q3 output differential output pair. lvpecl...
Description Fourth Generation FemtoClock NG PLL technology

File Size 762.11K  /  37 Page

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    Integrated Device Techn...
Part No. 8T49N012
OCR Text ...r pairs of complementary lvcmos/lvttl outputs bank b: two pairs of lvpecl outputs bank c: six pairs of lvpecl outputs ? selectable clock inp...interface levels. see the function configuration tables section. 2v cc power core power supply pins....
Description Fourth Generation FemtoClock NG PLL technology

File Size 639.53K  /  28 Page

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    CY28325OXC-3 CY28325-3 CY28325OC-3 CY28325OC-3T CY28325OXC-3T

SpectraLinear Inc
Part No. CY28325OXC-3 CY28325-3 CY28325OC-3 CY28325OC-3T CY28325OXC-3T
OCR Text ...Table. CPU Output Control: 3.3V LVTTL-compatible input that disables CPUT_CS, CPUC_CS, CPUT_0:1 and CPUC_0:1. PCI Output Control: 3.3V LVTTL...interface. SMBus Data Input: Data pin for serial interface. X2 REF/FS4 5 1 O I/O CPUT_0:...
Description FTG for VIA Pentium 4?Chipsets
FTG for VIA⑩ Pentium 4⑩ Chipsets

File Size 202.56K  /  18 Page

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    CY28443OXC-2 CY28443OXC-2T CY28443-2

Cypress Semiconductor
Part No. CY28443OXC-2 CY28443OXC-2T CY28443-2
OCR Text ...on CY28443-2 I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) or 100-MHz serial reference clock. Default function...interface is optional. Clock device register changes are normally made upon system initialization, i...
Description Clock Generator for Intel㈢ Calistoga Chipset

File Size 455.77K  /  24 Page

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