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IXYS CORP
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| Part No. |
GX60N60C2D1
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| Description |
Fast sram > Late Write Synchronous sram; organization (word): 512K; organization (bit): x 36; Memory capacity (bit): 16M; Supply voltage (V): 150; Operating temperature (°C): 1.5; Package: BGA (119)
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| File Size |
615.83K /
5 Page |
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Seiko NPC Corporation
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| Part No. |
CF5015 CF5015AL2 CF5015AL1-2 CF5015AL2-2
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| Description |
low power sram; organization (word): 1M; organization (bit): x 16; Memory capacity (bit): 16M; Access time (ns): 55; Supply voltage (V): 2.7 to 3.6; Operating temperature (°C): 0 to 70; Package: FBGA (48)
low power sram; organization (word): 1M; organization (bit): x 16; Memory capacity (bit): 16M; Access time (ns): 85; Supply voltage (V): 2.7 to 3.6; Operating temperature (°C): -40 to 85; Package: FBGA (48)
low power sram; organization (word): 1M; organization (bit): x 16; Memory capacity (bit): 16M; Access time (ns): 70; Supply voltage (V): 2.7 to 3.6; Operating temperature (°C): 0 to 70; Package: FBGA (48)
low power sram; organization (word): 1M; organization (bit): x 16; Memory capacity (bit): 16M; Access time (ns): 85; Supply voltage (V): 2.7 to 3.6; Operating temperature (°C): 0 to 70; Package: FBGA (48)
low power sram; organization (word): 1M; organization (bit): x 16; Memory capacity (bit): 16M; Access time (ns): 70; Supply voltage (V): 2.7 to 3.6; Operating temperature (°C): -40 to 85; Package: FBGA (48)
low power sram; organization (word): 1M; organization (bit): x 16; Memory capacity (bit): 16M; Access time (ns): 85; Supply voltage (V): 2.7 to 3.6; Operating temperature (°C): 0 to 70; Package: FBGA (48)
low power sram; organization (word): 1M; organization (bit): x 16; Memory capacity (bit): 16M; Access time (ns): 70; Supply voltage (V): 2.7 to 3.6; Operating temperature (°C): 0 to 70; Package: FBGA (48)
low power sram; organization (word): 1M; organization (bit): x 16; Memory capacity (bit): 16M; Access time (ns): 70; Supply voltage (V): 2.7 to 3.6; Operating temperature (°C): -40 to 85; Package: FBGA (48)
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| File Size |
94.87K /
10 Page |
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it Online |
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
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| Part No. |
M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M38232G4-XXXFP M38232G4-XXXHP M38233G4-XXXFP M38233G4-XXXHP M38234G4-XXXFP M38234G4-XXXHP M38235G4-XXXFP M38230G6-XXXFP M38230G6-XXXHP M38231G6-XXXFP M38231G6-XXXHP M38232G6-XXXFP M38232G6-XXXHP M38233G6-XXXFP M38233G6-XXXHP M38234G6-XXXFP M38234G6-XXXHP M38235G6-XXXFP M38235G6-XXXHP M38236G6-XXXHP M38237G6-XXXFP M38237G6-XXXHP M38238G6-XXXFP M38230G7-XXXFP M38230G7-XXXHP M38231G7-XXXFP M38231G7-XXXHP M38232G7-XXXFP M38232G7-XXXHP M38233G7-XXXFP M38233G7-XXXHP M38234G7-XXXFP M38234G7-XXXHP M38235G7-XXXFP M38235G7-XXXHP M38236G7-XXXFP M38236G7-XXXHP M38237G7-XXXFP M38237G7-XXXHP M38238G7-XXXFP M38238G7-XXXHP M38239G7-XXXFP M38239G7-XXXHP M38230G8-XXXFP M38230G8-XXXHP M38231G8-XXXFP M38231G8-XXXHP M38232G8-XXXFP M38232G8-XXXHP M38233G8-XXXFP M38233G8-XXXHP M38234G8-XXXFP M38234G8-XXXHP M38235G8-XXXFP M38235G8-XXXHP M38236G8-XXXFP M38236G8-XXXHP M38237G8-XXXFP M38237G8-XXXHP M38238G8-XXXFP M38238G8-XXXHP M38230GA-XXXFP M38230GA-XXXHP M38231GA-XXXFP M38231GA-XXXHP M38232GA-XXXFP M38232GA-XXXHP M38233GA-XXXFP M38233GA-XXXHP M38234GA-XXXFP M38234GA-XXXHP M38235GA-XXXFP M38235GA-XXXHP M38236GA-XXXFP M38236GA-XXXHP M38237GA-XXXFP M38237GA-XXXHP
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| Description |
18-Mbit (512K x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II sram 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 36 Mb; organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II sram 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined sram; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II sram 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II sram 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through sram with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II sram 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 72 Mb; organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II sram 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 72 Mb; organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync sram; Architecture: QDR-II, 2 word Burst; Density: 36 Mb; organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II sram 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 36 Mb; organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II sram 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 72 Mb; organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II sram 4-word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 word Burst; Density: 72 Mb; organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II sram 2-word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 word Burst; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II sram 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 72 Mb; organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II sram 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II sram 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II sram 4-word Burst Architecture; Architecture: QDR-II, 4 word Burst; Density: 36 Mb; organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync sram; Architecture: QDR-II, 2 word Burst; Density: 36 Mb; organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II sram 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 36 Mb; organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II sram 2-word Burst Architecture; Architecture: DDR-II CIO, 2 word Burst; Density: 72 Mb; organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II sram 2-word Burst Architecture; Architecture: QDR-II, 2 word Burst; Density: 36 Mb; organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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| File Size |
901.80K /
76 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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