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				Integrated Device Technology
Part No.	IDT72255LA20TFG IDT72265LA20TFG IDT72255LA10TFG IDT72265LA10TFG IDT72255LA10TFGI IDT72265LA10TFGI
OCR Text	... flag can default to one of two preselected offsets Program partial flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts dat...
Description	CMOS SuperSync FIFO
File Size	327.69K / 27 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDT72T36105L7BBI
OCR Text	...lag can default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for Almost- * * * * * * * * * * * * * * * Empty and Almost-Full flag...
Description	2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
File Size	549.01K / 57 Page	View it Online	Download Datasheet

				Renesas Electronics Corporation
Part No.	HA16103FPJ HA16103FPK
OCR Text	...hen input pulses are not at the preselected frequency (at either a higher or lower frequency). The RC characteristic of the bandpass filter may be set with external components Rf and Cf. Equation 3 specifies how to determine the minimum pul...
Description	Watchdog Timer
File Size	349.11K / 19 Page	View it Online	Download Datasheet

				IDT Integrated Device Technology
Part No.	IDT72V7230 IDT72V7240L15BB IDT72V7230L10BB
OCR Text	...lag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF an...
Description	512 X 72 SuperSync II FIFO, 3.3V 1K x 72 SuperSync II FIFO, 3.3V 3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
File Size	436.29K / 42 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc. Integrated Device Techn...
Part No.	IDT72T3675L4BB IDT72T3685L7BBI IDT72T3695L5BBI IDT72T3695L7BB IDT72T3695L6BB IDT72T3645L4BBI IDT72T3665L4BB IDT72T3665L4BBI IDT72T3675L7BB IDT72T3675L6BBI IDT72T3675L10BBI IDT72T3675L5BBI IDT72T36125L6BB IDT72T3685L10BB IDT72T3685L4BB IDT72T3685L5BBI IDT72T3685L6BB IDT72T3685L4BBI
OCR Text	...lag can default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for Almost- * * * * * * * * * * * * * * * Empty and Almost-Full flag...
Description	2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS 8K X 36 OTHER FIFO, 3.6 ns, PBGA208 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS 2.5伏高速TeraSyncTM FIFO6位配
File Size	560.20K / 57 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc. Integrated Device Technolog... Integrated Device Techn...
Part No.	IDT72V273L6PF IDT72V243 IDT72V223 IDT72V253 IDT72V263 IDT72V283 IDT72V233 IDT72V243L6PF IDT72V243L6PFI IDT72VL15PF IDT72V253L15PF IDT72V223L6BCI IDT72V223L10BC IDT72V243L10PFI IDT72V243L15PFI IDT72V273L15PFI IDT72VL6BCI IDT72VL6PF IDT72VL6PFI IDT72V223L10BCI IDT72V223L10PF
OCR Text	...lag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF an...
Description	3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO 2K X 18 OTHER FIFO, 6.5 ns, PQFP80 3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO 4K X 18 OTHER FIFO, 10 ns, PQFP80 3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO 3.3伏高密度SUPERSYNC窄总线先进先出 RECEPTACLE, EMI, BACKSHELL, 360DEG; Gender:Receptacle; Ways, No. of:1; Series:RJF TV RoHS Compliant: No PLUG ASSEMBLY, 360DEG, EMI, BACKSHELL; Gender:Plug; Ways, No. of:1; Series:RJF TV RoHS Compliant: No
File Size	436.88K / 45 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc. Integrated Device Techn...
Part No.	IDT72271L15G IDT72271L20PF IDT72261L10G IDT72271L10G IDT72261L20G IDT72261L15G IDT72261L25G IDT72261L12G IDT72271L25TFB IDT72271L25PFB IDT72261L10TFB IDT72261L12PF IDT72261L15PF IDT72261L15PFB
OCR Text	... flag can default to one of two preselected offsets Program partial flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Easily expandable in d...
Description	CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 的CMOS SUPERSYNC FIFOO 16,384 × 92768 × 9 CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
File Size	395.41K / 30 Page	View it Online	Download Datasheet

For preselected Found Datasheets File :: 227 Search Time::5.422ms
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