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Integrated Device Techn...
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| Part No. |
87339AMI-11LFT 87339AGI-11LFT
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| OCR Text |
...iv_selb0 input pulldown selects divide value for bank b outputs as described in table 3. lvcmos / lvttl interface levels. 4 clk input pulldo...by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to th... |
| Description |
Low Skew, Differential-to-3.3V LVPECL Clock Generator
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| File Size |
193.97K /
15 Page |
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it Online |
Download Datasheet
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PEREGRINE[Peregrine Semiconductor Corp.]
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| Part No. |
PE3513-EK 3513-00 3513-01 3513-02 3513-51 3513-52 513 PE3513
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| OCR Text |
...raCMOSTM prescaler with a fixed divide ratio of 8. Its operating frequency range is DC to 1500 MHz. The PE3513 operates on a nominal 3 V sup...by-8 Prescaler Features
* DC to 1500 MHz operation * Fixed divide ratio of 8 * Low-power consumptio... |
| Description |
1500 MHz Low Power UltraCMOS divide-by-8 Prescaler 1500 MHz Low Power UltraCMOSdivide-by-8 Prescaler 1500 MHz Low Power UltraCMOS⑩ divide-by-8 Prescaler
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| File Size |
218.38K /
8 Page |
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it Online |
Download Datasheet
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IDT
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| Part No. |
IDT5V996BBI8
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| OCR Text |
... l h +7t u h m l inverted h m m divide by 2 h m h divide by 4 comments timing unit calculation (t u ) 1/(16 x f nom ) vco frequency range (f nom ) (1) 100 to 225 mhz skew adjustment range (2) max adjustment: 4.375ns ns 157.5 phase degrees 4... |
| Description |
3.3V Programmable Skew PLL Clock Driver Turboclock II Plus
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| File Size |
64.76K /
9 Page |
View
it Online |
Download Datasheet
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Price and Availability
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