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Cypress
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| Part No. |
CY3140 3140
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| OCR Text |
... and ABEL-6 -- Schematic entry, vhdl, and ABEL-HDL for SynarioTM * Full integration supporting all ABELTM and SynarioTM design features * Supports the full family of FLASH370iTM devices * Graphical device simulator included (CYPSIM) * Autom... |
| Description |
ABELSynario Design Kit for FLASH370i From old datasheet system
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| File Size |
21.36K /
1 Page |
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quicklogic
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| Part No. |
QL5020
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| OCR Text |
... with a top-level Verilog(R) or vhdl file, then you would use a structural instantiation of this PCIT32N block, instead of a graphical symbol.
2 * www.quicklogic.com *
* * *
*
(c) 2003 QuickLogic Corporation
QL5020 QuickPCI Dat... |
| Description |
33 MHz/32-bit PCI with Embedded Programmable Logic
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| File Size |
584.44K /
21 Page |
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Lineage Power
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| Part No. |
M16550
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| OCR Text |
... to 58 MHz -7 : up to 74 MHz
vhdl Source code vhdl Test Bench for behavioral and gate level simulation. Data Sheet Design Document : features, architecture, interfaces and operation. User's guide : simulation, synthesis and Place and Rou... |
| Description |
Universal Asynchronous Receiver/Transmitter(通用异步接收传送器)
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| File Size |
125.43K /
11 Page |
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it Online |
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Atmel
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| Part No. |
ATL60
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| OCR Text |
...mbit) ModelSim(R) - Verilog and vhdl (VITAL) Simulator Leonardo SpectrumTM - Logic Synthesis Design CompilerTM - Synthesis DFT Compiler - 1-Pass Test Synthesis BSD Compiler - Boundary Scan Synthesis TetraMax(R) - Automatic Test Pattern Gene... |
| Description |
The ATL60 series CMOS Gate Arrays are fabricated using a 0.6 micron drawn gate, oxide isolated, triple level metal process. Extensive cell libraries are available and support the major CAD software tools.
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109.90K /
14 Page |
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Triscend
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TA7S20
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...y standard logic design tools - vhdl and Verilog logic synthesis - Schematic entry - vhdl and Verilog simulation ! High performance dedicated system bus * Configurable System Interconnect (CSI) bus integrates CSL matrix, CSoC system * 455Mb... |
| Description |
(TA7S04 / TA7S20) Triscend A7S Configurable System-on-Chip Platform
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1,611.14K /
198 Page |
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it Online |
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Atmel
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| Part No. |
ATL35
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| OCR Text |
...mbit) ModelSim(R) - Verilog and vhdl (VITAL) Simulator Leonardo SpectrumTM - Logic Synthesis Design CompilerTM - Synthesis DFT Compiler - 1-Pass Test Synthesis BSD Compiler - Boundary Scan Synthesis TetraMax(R) - Automatic Test Pattern Gene... |
| Description |
The ATL35 series ASIC family is fabricated on a 0.35 micron CMOS process with up to four levels of metal. This family features arrays with up to 2.7 million routable gates and 976 pins. The high density and high pin count capabilities of t
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268.46K /
21 Page |
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Cypress
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| Part No. |
CY3112J 3110
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| OCR Text |
...6V8, 20V8, 22V10) * Verilog and vhdl timing model output for use with third-party simulators * Timing simulation provided with Active-HDLTM Sim Release 3.3 from Aldec (PC only) including: -- Graphical waveform simulator -- Entry and modific... |
| Description |
Warp2 Verilog Development System for CPLDs DESIGN ENTRY COMPILATION VERFICA TION From old datasheet system
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| File Size |
94.00K /
5 Page |
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Lineage Power
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| Part No. |
SLC1655
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vhdl Core
Product Overview
The Silicore SLC1655 is an 8-bit RISC microcontroller. It is delivered as a vhdl soft core module, and is intended for use in both FPGA and ASIC type devices. It is useful for microprocessor based embedded contr... |
| Description |
8-bit RISC Microcontroller(8位RISC微控制器)
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| File Size |
123.83K /
6 Page |
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Altera Corp
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| Part No. |
EPM7512AEBC256-10 EPM7256AEFC100-10
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...zed modules (LPM), Verilog HDL, vhdl, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with Altera's Master Programm... |
| Description |
COMPLEX-EEPLD,512-CELL,10NS PROP DELAY,BGA,256PIN,PLASTIC COMPLEX-EEPLD,256-CELL,10NS PROP DELAY,BGA,100PIN,PLASTIC
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| File Size |
529.99K /
60 Page |
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Altera Corporation http://
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| Part No. |
EPF10K130E EPF10K100E EPF10K30E EPF10K50EFC484-1 EPF10K50SFC484-2X
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...gnWare components, Verilog HDL, vhdl, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Notes (1), (2) 600-Pin 672-Pin BGA Fin... |
| Description |
Embedded Programmable Logic Device
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| File Size |
597.44K /
100 Page |
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Price and Availability
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