| |
|
 |
QLogic
|
| Part No. |
FAS368M
|
| OCR Text |
...ata is valid around the rising (trailing) edge of DBRD or DBWR. DMA transfers are terminated by deasserting DREQ. Deassertion of DREQ is triggered by the leading edge of DBRD or DBWR (see timing parameter t1 in figures 2 and 3) under any of... |
| Description |
Fast Architecture SCSI Precossor
|
| File Size |
64.93K /
8 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
QLogic
|
| Part No. |
FAS366U
|
| OCR Text |
...ata is valid around the rising (trailing) edge of DBRD or DBWR. DMA transfers are terminated by deasserting DREQ. Deassertion of DREQ is triggered by the leading edge of DBRD or DBWR (see timing parameter t1 in figures 2 and 3) under any of... |
| Description |
Fast Architecture SCSI Precossor
|
| File Size |
85.37K /
8 Page |
View
it Online |
Download Datasheet |
| |
|
|
Maxim Integrated Products, Inc.
|
| Part No. |
DS1013
|
| OCR Text |
...and voltage range ? leading and trailing edge accuracy ? economical ? auto-insertable, low profile ? standard 14-pin dip, 8-pin dip, or 16-pin soic ? low-power cmos ? ttl/cmos-compatible ? vapor phase, ir and wave solderable ? custom delays... |
| Description |
3-in-1 Silicon Delay Line(片内集成3个独立的硅延迟线)
|
| File Size |
41.14K /
5 Page |
View
it Online |
Download Datasheet |
| |
|
|
Maxim Integrated Products, Inc.
|
| Part No. |
DS1035
|
| OCR Text |
...ature and voltage ? leading and trailing edge precision preserves the input symmetry ? standard 8pin dip and 8pin soic (150 mil) ? vapor phasing, ir and wave solderable ? available in tape and reel pin assignment v cc 1 2 3 4 8 7 6 5 out1 o... |
| Description |
3-in-1 High-Speed Silicon Delay Line(片内集成3个独立的高速硅延迟
|
| File Size |
38.63K /
6 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
