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				ETC[ETC]
Part No.	DRX3960A DRP3510 DRX3960
OCR Text	... a standard TV tuner, it can be preselected and further down-mixed by the DRX 3960A. Thus, a succeeding sound demodulator, e.g. the MSP, will be able to demodulate that channel. The DRX 3960A operates with its own quartz or with appropriate...
Description	Digital Receiver Front-end
File Size	241.83K / 30 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT72T2098L7BBI IDT72T20108 IDT72T20108L10BB IDT72T20108L10BBI IDT72T20108L4BB IDT72T20108L4BBI IDT72T20108L5BB IDT72T20108L5BBI IDT72T20108L6BB IDT72T20108L6BBI IDT72T20108L7BB IDT72T20108L7BBI IDT72T20118 IDT72T20118L10BB IDT72T20118L10BBI IDT72T20118L4BB IDT72T20118L4BBI IDT72T20118L5BB IDT72T20118L5BBI IDT72T20118L6BB IDT72T20118L6BBI IDT72T20118L7BB IDT72T20118L7BBI IDT72T20128 IDT72T20128L10BB IDT72T20128L10BBI IDT72T20128L4BB IDT72T20128L4BBI IDT72T20128L5BB IDT72T20128L5BBI IDT72T20128L6BB IDT72T20128L6BBI IDT72T20128L7BB IDT72T20128L7BBI IDT72T2098 IDT72T2098L10BB IDT72T2098L10BBI IDT72T2098L4BB IDT72T2098L4BBI IDT72T2098L5BB IDT72T2098L5BBI IDT72T2098L6BB IDT72T2098L6BBI IDT72T2098L7BB
OCR Text	...flag can default to one of four preselected offsets Dedicated serial clock input for serial programming of flag offsets User selectable input and output port bus sizing -x20 in to x20 out -x20 in to x10 out -x10 in to x20 out -x10 in to x10...
Description	2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
File Size	475.63K / 51 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT72T7295L7BBI IDT72T72105 IDT72T72105L10BB IDT72T72105L10BBI IDT72T72105L4BB IDT72T72105L4BBI IDT72T72105L5BB IDT72T72105L5BBI IDT72T72105L6BB IDT72T72105L6BBI IDT72T72105L7BB IDT72T72105L7BBI IDT72T72115 IDT72T72115L10BB IDT72T72115L10BBI IDT72T72115L4BB IDT72T72115L4BBI IDT72T72115L5BB IDT72T72115L5BBI IDT72T72115L6BB IDT72T72115L6BBI IDT72T72115L7BB IDT72T72115L7BBI IDT72T7285 IDT72T7285L10BB IDT72T7285L10BBI IDT72T7285L4BB IDT72T7285L4BBI IDT72T7285L5BB IDT72T7285L5BBI IDT72T7285L6BB IDT72T7285L6BBI IDT72T7285L7BB IDT72T7285L7BBI IDT72T7295 IDT72T7295L10BB IDT72T7295L10BBI IDT72T7295L4BB IDT72T7295L4BBI IDT72T7295L5BB IDT72T7295L5BBI IDT72T7295L6BB IDT72T7295L6BBI IDT72T7295L7BB
OCR Text	...lag can default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Separate SCLK input for Serial programm...
Description	2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
File Size	517.71K / 53 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT72V2113L7PFI IDT72V2103 IDT72V2103L10BC IDT72V2103L10BCI IDT72V2103L10PFI IDT72V2103L15BC IDT72V2103L15BCI IDT72V2103L15PF IDT72V2103L15PFI IDT72V2103L5BC IDT72V2103L5BCI IDT72V2103L5PF IDT72V2103L5PFI IDT72V2103L6BC IDT72V2103L6BCI IDT72V2103L6PF IDT72V2103L6PFI IDT72V2103L7-5BC IDT72V2103L7-5BCI IDT72V2103L7-5PF IDT72V2103L7-5PFI IDT72V2103L7BC IDT72V2103L7BCI IDT72V2103L7PF IDT72V2103L7PFI IDT72V2113 IDT72V2113L10BC IDT72V2113L10BCI IDT72V2113L10PF IDT72V2113L15BC IDT72V2113L15BCI IDT72V2113L15PF IDT72V2113L15PFI IDT72V2113L5BC IDT72V2113L5BCI IDT72V2113L5PF IDT72V2113L5PFI IDT72V2113L6BC IDT72V2113L6BCI IDT72V2113L6PF IDT72V2113L6PFI IDT72V2113L7-5BC IDT72V2113L7-5BCI IDT72V2113L7-5PF IDT72V2113L7-5PFI IDT72V2113L7BC IDT72V2113L7BCI IDT72V2113L7PF
OCR Text	...lag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF an...
Description	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
File Size	424.60K / 46 Page	View it Online	Download Datasheet

				Atmel Corp. ATMEL[ATMEL Corporation]
Part No.	U6084B_05 U6084B U6084B-MFPG3Y
OCR Text	...s. For constant brightness, the preselected duty cycle can be reduced automatically as a function of the supply voltage. PWM Power Control with Automatic Duty-cycle Reduction U6084B Figure 1-1. Block Diagram with External Circuit ...
Description	PWM Power Control with Automatic Duty-cycle Reduction
File Size	178.42K / 11 Page	View it Online	Download Datasheet

				SEMTECH[Semtech Corporation]
Part No.	UR6HCPS2-SP40-FG UR6HCPS2-SP40
OCR Text	...mplements the ASI mode at fixed preselected baud rates: 300bps, 600bps, 1200bps, 9600bps, 19200bps, 31250bps and 62500bps, depending on the Configuration pins' state on power up. In ASI mode, the UR6HCPS2-SP40 deploys the _RTS & _CTS as add...
Description	Converts PS/2 Data to Serial or SPI
File Size	130.67K / 22 Page	View it Online	Download Datasheet

				IDT Integrated Device Technology
Part No.	IDT72V273L7BC IDT72V273L7BCI IDT72V273L7PF IDT72V273L7PFI IDT72V223L7-5BC IDT72V223L7-5BCI IDT72V223L7-5PF IDT72V223L7-5PF8 IDT72V223L7-5PFI IDT72V233L7-5BC IDT72V233L7-5BCI IDT72V233L7-5PF IDT72V233L7-5PF8 IDT72V233L7-5PFI IDT72V243L7-5BC IDT72V243L7-5BCI IDT72V243L7-5PF IDT72V243L7-5PF8 IDT72V253L7-5BC IDT72V253L7-5BCI IDT72V263L7-5BC IDT72V263L7-5BCI IDT72V273L7-5BC IDT72V273L7-5BCI IDT72V283L7-5BC IDT72V283L7-5BCI IDT72V293L7-5BC IDT72V293L7-5BCI IDT72V243L7-5PFI IDT72V253L7-5PF IDT72V253L7-5PF8 IDT72V253L7-5PFI IDT72V263L7-5PF IDT72V263L7-5PF8 IDT72V263L7-5PFI IDT72V273L7-5PF IDT72V273L7-5PF8 IDT72V273L7-5PFI IDT72V283L7-5PF IDT72V283L7-5PF8 IDT72V283L7-5PFI IDT72V293L7-5PF IDT72V293L7-5PF8 IDT72V293L7-5PFI IDT72V233L6BC IDT72V223L6PF8 IDT72V233L6PF IDT72V233L6PF8 IDT72V273L10PF IDT72V273L10PFI
OCR Text	...lag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF an...
Description	64K x 18 / 128K x 9 SuperSync II FIFO, 3.3V 32K x 18 / 64K x 9 SuperSync II FIFO, 3.3V 16K x 18 / 32K x 9 SuperSync II FIFO, 3.3V 8K x 18 / 16K x 9 SuperSync II FIFO, 3.3V 4K x 18 / 8K x 9 SuperSync II FIFO, 3.3V 2K x 18 / 4K x 9 SuperSync II FIFO, 3.3V 1K x 18 / 2K x 9 SuperSync II FIFO, 3.3V 512 x 18 / 1K x 9 SuperSync II FIFO, 3.3V 3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO
File Size	428.03K / 45 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC Integrated Device Technology, Inc. IDT
Part No.	IDT72V271LA IDT72V271LA10PF IDT72V271LA10PFI IDT72V271LA10TFI IDT72V271LA15PF IDT72V271LA20PF IDT72V271LA20PFI IDT72V271LA20TF IDT72V271LA20TFI IDT72V271 IDT72V261LA20TF IDT72V261LA10TF IDT72V271LA10PF8 IDT72V271LA10TF8 IDT72V261LA10TF8
OCR Text	... flag can default to one of two preselected offsets * * * * * * * * Program partial flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) ...
Description	3.3 VOLT CMOS SuperSync FIFO 16K X 9 OTHER FIFO, 12 ns, PQFP64 32K x 9 SuperSync FIFO, 3.3V 16K x 9 SuperSync FIFO, 3.3V
File Size	298.14K / 27 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDT72T36135M IDT72T36135ML5BBG IDT72T36135ML5BBGI IDT72T36135ML6BBG IDT72T36135ML6BBGI
OCR Text	...lag can default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Separate SCLK input for Serial progr...
Description	2.5V 18M-BIT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS 524,288 x 36
File Size	478.45K / 48 Page	View it Online	Download Datasheet

For preselected Found Datasheets File :: 227 Search Time::1.828ms
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