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AGERE[Agere Systems]
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| Part No. |
LCK4310 LCK4310GF-DT LCK4310GF-DB
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| OCR Text |
...he backplane or the board. In a pecl environment (series or Thevenin), line terminations are typically used since they require no additional...ecl) fanout buffer designed with clock distribution in mind. The device features fully differential ... |
| Description |
Low-Voltage PLL Clock Driver
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| File Size |
63.46K /
10 Page |
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Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
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| Part No. |
CY2DP314 CY2DP314OI CY2DP314OIT CY2DP314OXI CY2DP314OXIT
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| OCR Text |
pecl differential outputs * One ecl/pecl differential or single-ended inputs (CLKA) * One HSTL differential or single-ended inputs (CLKB) * Hot-swappable/-insertable * 50-ps output-to-output skew * 150-ps device-to-device skew * 400-ps prop... |
| Description |
VGA VIDEO SPLITTER 10-CH INCLU 1 of 2:4 Differential Clock/Data Fanout Buffer
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| File Size |
211.09K /
9 Page |
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it Online |
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MOTOROLA[Motorola Inc]
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| Part No. |
MC10LVELT23D
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| OCR Text |
...tion IOH = -3.0mA IOL = 24mA
pecl INPUT DC CHARACTERISTICS (VCC = 3.0V to 3.6V; TA = -40C to 85C)
-40C Symbol IIH IIL VCMR Characteristic Input HIGH Current Input LOW Current Common Mode Range D0, D1 D0, D1 -100 -100 1.2 VCC Min Max 150... |
| Description |
Dual Differential LVpecl to TTL Translator
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| File Size |
61.86K /
3 Page |
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it Online |
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ONSEMI[ON Semiconductor]
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| Part No. |
MC100EP139 MC100EP139DW MC100EP139DWR2 MC100EP139DTR2 ON0490 MC100EP139DT
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| OCR Text |
...*
50ps Output-to-Output Skew pecl mode: 3.0V to 5.5V VCC with VEE = 0V ecl mode: 0V VCC with VEE = -3.0V to -5.5V Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips Q Output will default LOW with inputs open or... |
| Description |
±2/4, ±4./5/6 Clock Generation Chip From old datasheet system 2/4 4./5/6 Clock Generation Chip
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| File Size |
139.59K /
8 Page |
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it Online |
Download Datasheet
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Price and Availability
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