| |
|
 |
XILINX
|
| Part No. |
XCS05-3VQ100C XCS20XL
|
| OCR Text |
...termine the logic functions and interconnections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA fro... |
| Description |
From old datasheet system Spartan and Spartan-XL Families
Field Programmable Gate Arrays
|
| File Size |
654.75K /
82 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
Fairchild Semiconductor Corporation FAIRCHILD[Fairchild Semiconductor]
|
| Part No. |
9403APC 9403A
|
| OCR Text |
.../parallel input and output. The interconnections necessary to form a 31-word by 16-bit FIFO are shown in Figure 6. Using the same technique, any FIFO of (15m + 1)-words by (4n)-bits can be constructed, where m is the number of devices in a ... |
| Description |
First-In First-Out (FIFO) Buffer Memory
|
| File Size |
155.21K /
16 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
ZARLINK[Zarlink Semiconductor Inc]
|
| Part No. |
ZL60304 ZL60304MJDA
|
| OCR Text |
...erver Clusters, Super-computing interconnections InfiniBand 4x-SX compliant Fibre Channel connections XAUI based interconnections Proprietary backplanes Interconnects rack-to-rack, shelf-to-shelf, board-to-board, board-to-optical backplane
... |
| Description |
From old datasheet system Parallel Fiber Optic Transceiver (4 4) x 3.125 Gbps
|
| File Size |
372.36K /
19 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
Atmel Corp
|
| Part No. |
ATF2500C
|
| OCR Text |
...nal logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the single global bus. The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numb... |
| Description |
2500 gate, 24 Macrocell, 48 Register, standard, quarter and low power, 40 and 44 pin CPLD
|
| File Size |
480.24K /
37 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
Atmel Corp
|
| Part No. |
ATV2500B
|
| OCR Text |
...nal logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the single global bus. The ATV2500Bs are straightforward and uniform PLDs. The 24 macrocells are numb... |
| Description |
2500 gate high-speed CPLD, standard & low power, 40 & 44 pins From old datasheet system
|
| File Size |
615.64K /
21 Page |
View
it Online |
Download Datasheet
|
|

Price and Availability
|