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100BZ NTE2959 LNK302 0805L010 EP16VZ E7500 2SB1683 X013B19
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    DM74LS503 DM74LS503N

FAIRCHILD[Fairchild Semiconductor]
Part No. DM74LS503 DM74LS503N
OCR Text ...GH and prevents the device from accepting serial data. With the E input of an DM74LS503 connected to the CC output of a preceding (more significant) device, the DM74LS503 will be inhibited until the preceding device is filled, causing its C...
Description 8-Bit Successive Approximation Register (with Expansion Control)

File Size 45.11K  /  4 Page

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    MC100EP14 MC100EP14D MC100EP14DT MC100EP14DTR2

ONSEMI[ON Semiconductor]
Part No. MC100EP14 MC100EP14D MC100EP14DT MC100EP14DTR2
OCR Text ...ith clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating u...
Description 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver 100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20

File Size 67.05K  /  8 Page

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    N.A.
Part No. AIT2139
OCR Text ...es. The processor is capable of accepting the multi-sync inputs in the master mode operation. The processor provides a clock and an odd/even signal to the FIFO or the external memory devices. The VGA data read-in time is not necessary to be...
Description VGA to NTSC/PAL Encoder

File Size 1,985.51K  /  36 Page

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    Hynix
Part No. GL3276A
OCR Text ...iving preamplifiers. Capable of accepting a photodiode directly, these ICs house a high gain initial amplifier, a limiter, a band-pass filter, a detection circuit and a waveform shaping circuit assembled on a single chip. Pin configurati...
Description IC,REMOTE-CONTROL AMPLIFIER/PREAMPLIFIER,SINGLE,BIPOLAR,SOP,8PIN,PLASTIC

File Size 32.63K  /  4 Page

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    Zarlink
Part No. SP5610
OCR Text ...o the read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates ...
Description 1.3GHz BI–DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER

File Size 446.78K  /  14 Page

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    Zarlink
Part No. SL2100
OCR Text ... into read mode, the controller accepting the data must pull the 4 SL2100 Datasheet Charge pump current The charge pump current can be programmed by bits C1 & C0 within data byte 4, as defined in figure (24). The test modes are de...
Description Single chip synthesised broadband converter

File Size 268.25K  /  25 Page

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    AT28C256-15PI AT28C256-15PC AT28C256E AT28C256E-15PC AT28C256E-15PI AT28C256E-15SC AT28C256E-15SI AT28C256E-15TI AT28C25

ATMEL[ATMEL Corporation]
Part No. AT28C256-15PI AT28C256-15PC AT28C256E AT28C256E-15PC AT28C256E-15PI AT28C256E-15SC AT28C256E-15SI AT28C256E-15TI AT28C256E-20JC AT28C256E-20JI AT28C256E-20PC AT28C256E-20SC AT28C256-20PI AT28C256-20PC AT28C256F-15JC AT28C256-15JC AT28C256E-25DM_883 AT28C256-20JC AT28C256 DOC226 AT28C256-20LM_883 AT28C256-15DM_883 AT28C256-25DM_883 AT28C256-15JI AT28C256-20DM_883 AT28C256-35 AT28C256F-35UM_883 28C256 AT28C256-15 AT28C256-15FM_883 AT28C256-15LM_883 AT28C256-15SC AT28C256-15SI AT28C256-15TC AT28C256-15TI AT28C256-15UM_883 AT28C256-20 AT28C256-20FM_883 AT28C256-20JI AT28C256-20SC AT28C256-20SI AT28C256-20TC AT28C256-20TI AT28C256-20UM_883 AT28C256-25 AT28C256-25FM_883 AT28C256-25JC AT28C256-25JI AT28C256-25LM_883 AT28C256-25PC AT28C256-25PI AT28C256-25UM_883 AT28C256-35UM_883 AT28C256E-15DM_883 AT28C256E-15FM_883 AT28C256E-15JC AT28C256E-15JI AT28C256E-15LM_883 AT28C256E-15TC AT28C256E-15UM_883 AT28C256E-20DM_883 AT28C256E-20FM_883 AT28C256E-20LM_883 AT28C256E-20PI AT28C256E-20SI AT28C256E-20TC AT28C256E-20TI AT28C256E-20UM_883 AT28C256E-25FM_883 AT28C256E-25JC AT28C256E-25JI AT28C256E-25LM_883 AT28C256E-25PC AT28C256E-25PI AT28C256E-25UM_883 AT28C256E-35UM_883 AT28C256F AT28C256F-15DM
OCR Text ...xceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low tra...
Description 256K 32K x 8 Paged CMOS E2PROM
256K (32K x 8) Paged CMOS
From old datasheet system

File Size 217.15K  /  14 Page

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    CHRONTEL
Part No. CH7017
OCR Text ...0 pixels. * LVDS low jitter PLL accepting EMI reduction input. * LVDS 18-bit and 24-bit outputs. * 2D dither engine. * Panel protection and Power-Down sequencing. * Programmable power management. * * * * * * Support for second CRT DAC bypas...
Description Display Controller Device Which Accepts Two Digital Graphics Input Data Streams

File Size 205.59K  /  8 Page

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    ICS
Part No. MK1575-01
OCR Text ... bandwidth which is needed when accepting low frequency input clocks such as those listed in the tables on page 1. page 3) the output clock frequency can be increased. Refer to the Output Frequency Calculation table below. CLK1 to FBI...
Description Low Cost Clock Recovery PLL

File Size 127.56K  /  12 Page

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