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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1514KV18 CY7C1514KV18-300BZXC CY7C1512KV18-300BZXC CY7C1512KV18-300BZC CY7C1514KV18-300BZC CY7C1514KV18-250BZC CY7C1514KV18-250BZI CY7C1514KV18-250BZXC CY7C1514KV18-333BZC CY7C1514KV18-333BZI CY7C1514KV18-333BZXC CY7C1514KV18-333BZXI CY7C1514KV18-250BZXI CY7C1525KV18 CY7C1512KV18-350BZC
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| OCR Text |
...8 ? 4m x 18 cy7c1514kv18 ? 2m x 36 functional description the cy7c1510kv18, cy7c1525kv18, cy7c1512kv18, and cy7c1514kv18 are 1.8 v synchronous pipelined srams, equipped with qdr ii architecture . qdr ii architecture consists of two separate... |
| Description |
72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 QDR SRAM, 0.45 ns, PBGA165
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4mb x 18; Vcc (V): 1.7 to 1.9 V 4m X 18 QDR SRAM, 0.45 ns, PBGA165
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| File Size |
603.26K /
33 Page |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1518KV18-300BZXC
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| OCR Text |
... (8m x 8, 8m x 9, 4m x 18, 2m x 36) 333 mhz clock for high bandwidth two-word burst for reducing address bus frequency double data rate (ddr) interfaces (data transferred at 666 mhz) at 333 mhz two input clocks (k and k ) for precise... |
| Description |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4mb x 18; Vcc (V): 1.7 to 1.9 V 4m X 18 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
973.05K /
33 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1518JV18-250BZC CY7C1518JV18-300BZXC
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| OCR Text |
... 72-mbit density (4m x 18, 2m x 36) 300 mhz clock for high bandwidth 2-word burst for reducing address bus frequency double data rate (ddr) interfaces (data transferred at 600 mhz) at 300 mhz two input clocks (k and k ) for precise d... |
| Description |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4mb x 18; Vcc (V): 1.7 to 1.9 V 4m X 18 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
895.67K /
23 Page |
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it Online |
Download Datasheet |
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